Changes
Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.
Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]
<br>
<pre>
di
ld bc,#BCFF
ld hl,%1001000011101010
out (c),c
ld a,h:rlca:ld h,l:ld l,a
ld c,a
cp #4D
jr nz,.loop
ld a,#CD ; a=#CD for unlock, another value for lock
out (c),a:out (c),a
ei
<pre>
di ; v2v3.0 1 -> 31 30 bytes!
ld bc,#BCFF
out (c),c
out (c),0 ; db #ED,#71
ld a,c
out (c),a
ld h,a ; H h = 7654 3210rra ; A = *765 4321add hl,hl ; H h = 6543 210-*push af rra ; Carry flag (bit 7) preserveda = 7765 4321add hl,hl ; H h = 5432 10--**add hl,hl xor h:and #F7:xor h ; H a = 4321 0---pop af ; Carry flag (bit 7) recovered7765 1321ld l,a ; L l = *765 43217765 1321ld a,h ; A a = 4321 0---rra ; A = 7432 5432 10--**xor h rla ; A a = (7 xor 4)*** (1 xor 4321 0)***xor l:and #88:xor l ; A a = (7 xor 4)765 (1 xor 0)321
cp c
jr nz,.loop
ei
ret
</pre>
== [[Longshot]] version ==
Interleave keys here
28 bytes - 349 nops
<pre>
Asic_Unlock
ld de,#533e ; interleave key 32 bits
ld hl,#849 ; interleave key (#841 to lock)
ld a,#ff
ld bc,#bcef ; crtc input io address and 1st nibbles
out (c),a ; RQ00 <>0
out (c),0 ; defb #ed,#71 ; Send 00 (out (c),0
Asic_Unlock_Loop:
out (c),a ; Send 2 nibbles
xor h ; Put bit 12 of the key in the bit 4 of A for high nibble
and c ; erase bit 4 to put key bit instead
xor h
adc hl,hl ; Extract left incoming bit of high nibble of interleave key
ret z ; exit when key is empty (extra value sent to io address)
ex de,hl ; Switch the interleave key (add hl,hl is good for you)
rra ; Bit 7 high nibble=Cf and rotate the complete byte
add hl,hl ; Extract left incoming bit of low nibble of interleave key
jr Asic_Unlock_Loop ; Send at last 18 values to crtc input io address
</pre>
while True:
out(b, a)
# a = (7 xor 4)765 (1 xor 0)321 a = ((a >> 1) & 0x77) | ((((a >> 7) & 1) ^ ((a >> 4<< 3)) & 1)) << 70x80) | ((((a >> 1) & 1<< 2) ^ (a & 1)) << 3)) & 0x08)
if a == c: break
def out(port, value):
print(f"Port: {hex(port)} xx Out: {hex(value)}")
unlock_asic()
= Patent =
For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
On the [[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, it is precised at §2.11 "Locking of enhanced features":
</code>
According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
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[[Category:Programming]]
[[Category:CPC Plus]]
