Changes

In Z80 Assembler:It still uses some magic numbers. 

.loop:

jr nz,.loop

ld a,#CD ; a=#CD for unlock, another value for lock

In Python:<pre>def unlock_asic(): b, c, h, l = 0xBC, 0xFF, 0x90, 0xEA # Initialize registers port_out(b, c) port_out(b, 0)= [[Urusergi]] version ==

di ; v3.1 -> 30 bytes!

out (c),0 ; db #ED,#71

.loop:

ld dh,a ; D h = 7654 3210rlca:rlca add hl,hl ; h = 6543 210*rra ; a = 7765 4321add hl,hl ; A h = 5432 107610**xor dh:and #7FF7:xor d h ; A a = 7432 10767765 1321ld el,arlca ; A l = 4321 07677765 1321xor e ld a,h ; A a = 7432 1076 XOR 4321 07675432 10**rrc d rla ; D a = 0765 43210***xor d:and #88:xor d l ; A a = (7 xor 4)765 (1 xor 0)321

jr nz,.loop

In Python:== [[Longshot]] version == Interleave keys here28 bytes - 349 nops 

Asic_Unlock ld de,#533e ; interleave key 32 bits ld hl,#849 ; interleave key (#841 to lock)ld a,#ffld bc,#bcef ; crtc input io address and 1st nibblesout (c),a ; RQ00 <>0out (c),0 ; defb #ed,#71 ; Send 00 (out (c),0Asic_Unlock_Loop:out (c),a ; Send 2 nibblesxor h ; Put bit 12 of the key in the bit 4 of A for high nibbleand c ; erase bit 4 to put key bit insteadxor hadc hl,hl ; Extract left incoming bit of high nibble of interleave keyret z ; exit when key is empty (extra value sent to io address)ex de,hl ; Switch the interleave key (add hl,hl is good for you) rra ; Bit 7 high nibble=Cf and rotate the complete byteadd hl,hl ; Extract left incoming bit of low nibble of interleave key jr Asic_Unlock_Loop ; Send at last 18 values to crtc input io address</pre> == Algorithm == <pre>def unlock_sequenceunlock_asic():

port_outout(b, c) port_outout(b, 0)

port_outout(b, a) d # a = a(7 xor 4)765 (1 xor 0)321 a = (a << 2 | (a >> 61) & 0xFF a = 0x77) | ((a ^ d(a << 3)) & 0x7F0x80) ^ d e = a a = | (((a << 1 | a >> 72) & 0xFF a = a ^ e d = (d >> 1 | d a << 73) & 0xFF a = ((a ^ d) & 0x880x08) ^ d

def port_outout(port, value): print(f"Port: {hex(port)}xx Out: {hex(value)}")

unlock_sequenceunlock_asic()

For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.