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ASIC

53 bytes added, 22:11, 5 July 2024
/* DMA commands */
A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:

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* The Bits2..0 are the channel enable bits in this register enable each . When set to "1" it enables the corresponding DMA" channel separately, and . It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.* The Bits7..4 are the interrupt bits are . An interrupt bit is set to "0" when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is "0" if at least one of the interrupt bits is "0".
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