Changes
ASIC
,/* Vectored Interrupt */
In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
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The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1.
Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.
