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Gate Array

No change in size, 11:29, 4 July 2024
/* Register RMR2 (ASIC & Advanced ROM mapping) */
-Mode- ROM address ASIC I/O Page

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0 0 00 &0000-&3FFF Disabled 0 1 01 &4000-&7FFF Disabled 1 0 10 &8000-&BFFF Disabled 1 1 11 &0000-&3FFF &4000-&7fff
The physicial lower ROMs are also accessible as logical upper ROMs with the RMR register.
Phi2x
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