Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.
Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]
<br>
ld hl,sequence
ld e,17
.seq
ld a,(hl)
dec e
jr nz,seq
ei
ret
<br>
= Optimized Z80 Assembler version versions =
The unlocking sequence can be reconstituted from simple bit operations instead of being stored in memory.
This allowed == [[Madram]] to create this optimized unlock routine:version == It still uses some magic numbers.
<pre>
UnlockAsicdi
ld bc,#BCFF
out (c),c
out (c),0
ld hl,%1001000011101010
.loop:
out (c),c
ld a,h:rlca:ld h,l:ld l,a
srl c:res 3,cxor c:and #88or :xor c
ld c,a
cp #4D
jr nz,.loop ld a,#CD ; a = #CD for unlock, another value for lockout (c),a : out (c),aei
ret
</pre>
== [[Urusergi]] version ==
No magic numbers here.
<pre>
di ; v3.1 -> 30 bytes!
ld bc,#BCFF
out (c),c
out (c),0 ; db #ED,#71
ld a,c
loop:
out (c),a
ld h,a ; h = 7654 3210
add hl,hl ; h = 6543 210*
rra ; a = 7765 4321
add hl,hl ; h = 5432 10**
xor h:and #F7:xor h ; a = 7765 1321
ld l,a ; l = 7765 1321
ld a,h ; a = 5432 10**
rla ; a = 4321 0***
and #88:xor l ; a = (7 xor 4)765 (1 xor 0)321
cp c
jr nz,loop
ei
ret
</pre>
== [[Longshot]] version ==
Interleave keys here
28 bytes - 349 nops
<pre>
Asic_Unlock
ld de,#533e ; interleave key 32 bits
ld hl,#849 ; interleave key (#841 to lock)
ld a,#ff
ld bc,#bcef ; crtc input io address and 1st nibbles
out (c),a ; RQ00 <>0
out (c),0 ; defb #ed,#71 ; Send 00 (out (c),0
Asic_Unlock_Loop:
out (c),a ; Send 2 nibbles
xor h ; Put bit 12 of the key in the bit 4 of A for high nibble
and c ; erase bit 4 to put key bit instead
xor h
adc hl,hl ; Extract left incoming bit of high nibble of interleave key
ret z ; exit when key is empty (extra value sent to io address)
ex de,hl ; Switch the interleave key (add hl,hl is good for you)
rra ; Bit 7 high nibble=Cf and rotate the complete byte
add hl,hl ; Extract left incoming bit of low nibble of interleave key
jr Asic_Unlock_Loop ; Send at last 18 values to crtc input io address
</pre>
== Algorithm ==
<pre>
def unlock_asic():
b, c = 0xBC, 0xFF
out(b, c)
out(b, 0)
a = c
while True:
out(b, a)
# a = (7 xor 4)765 (1 xor 0)321
a = ((a >> 1) & 0x77) | ((a ^ (a << 3)) & 0x80) | (((a << 2) ^ (a << 3)) & 0x08)
if a == c: break
def out(port, value):
print(f"Port: {hex(port)}xx Out: {hex(value)}")
unlock_asic()
</pre>
<br>
==Visual representation==
As one may see, the nybbles in the sequence are based on two 4bit shift registers.
[[File:AsicUnlockSequence.png]]
Visual by [[Hwikaa]]
<br>
==Patent==For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
The patent seems to focus on ''verifying'' (rather than on ''sending'') On the sequence[[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, so its legal it is precised at §2.11 "Locking of enhanced features":<code>it should be noted that unauthorised use is a bit unclearof this mechanism may infringe Amstrad's patent.</code>
According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
<br>
[[Category:Programming]]
[[Category:CPC Plus]]