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ASIC

312 bytes added, 12:53, 5 July 2024
/* DMA commands */
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.

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*  A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:* The channel enable bits in this register enable each "DMA" channel separately, and can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on reset.* The interrupt bits are set when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
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Phi2x
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