Each chip has its own challenges:
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*[[Z80]] is a bloated architecture, with lots of special cases and complex bus logic. The difference with the lean GBZ80 and [[MOS 6502|6502]] and GBZ80 is striking.
*[[CRTC]] has a character-based addressing logic, many incompatible chip implementations, and requires accurate VDU emulation too.
*[[Gate Array]] has a weird interrupt system and adds an unnecessary layer of complexity to sync signals.