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Changes - CPCWiki

Changes

Default I/O Port Summary

265 bytes added, 16:07, 10 January 2025
/* I/O Port Allocation Rules */
! b15 !! b14 !! b13 !! b12 !! b11 !! b10 !! b9 !! b8 !! b7 !! b6 !! b5 !! b4 !! b3 !! b2 !! b1 !! b0
|-
| [[Gate-Array ]] || Write only || 0 || 1 || - || - || - || - || - || - || - || - || - || - || - || - || - || -
|-
| [[PAL16L8|PAL]] (RAM Configuration configuration) || Write only || 0 || - * || - || - || - || - || - || - || - || - || - || - || - || - || - || -
|-
| [[CRTC ]] || Read/Write || - || 0 || - || - || - || - || r1 || r0 || - || - || - || - || - || - || - || -
|-
| [[Upper ROM Bank Number| ROM select ]] || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -
|-
| [[Printer port Port]] || Write only || - || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || -
|-
| [[8255| 8255 PPI ]] || Read/Write || - || - || - || - || 0 || - || r1 || r0 || - || - || - || - || - || - || - || -
|-
| Expansion Peripherals || Read/Write || - || - || - || - || - || 0 || x || x || x || x || x || x || x || x || x || x
*"1" means the bit must be set to "1" for the hardware device to respond.
*"r1" and "r0" mean a bit used to define a register
* "*" Bit14 of the PAL port must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
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