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Changes - CPCWiki

Changes

Gate Array

3 bytes added, 09:58, 31 August 2024
/* Bus arbitration */
In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

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Unlike the ZX Spectrum or the Amiga, this bus arbitration is not limited only to the "chip RAM". On the CPC, it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the memory type of memory it accesses.
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