For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included.
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The same logic applies to Gate Array will always perform a full VSYNC, with of 26 lines (including 4 lines instead of chars. The Gate Array C-VSYNC is considered complete when to the 26th line has been processed. Then monitor), even if the Gate Array stops outputting duration of the palette colour blackCRTC VSYNC is reduced to 2 µseconds.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 which counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2. It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.