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Changes - CPCWiki

Changes

Gate Array

1 byte added, 16:38, 1 July 2024
/* CSYNC signal */
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included.
The same logic applies to VSYNC , with lines instead of chars. The Gate Array VSYNC is considered complete when the 26th line has been processed. Then the Gate Array stops outputting the palette colour black.
The Gate Array uses 2 internal counters to create its CSYNC signal:
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