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* The eagle schematics indicate INT is triggered, but the PCB drawings indicate [[NMI]] is connected. * the static RAM is accessible between 0-1fff. It could be mirrored between 2000-3fff.* Has a write only I/O port &FBFB/&FAFB (partially decoded. where A10=0, and A2=0). A8 controls of the port address (when '1'?) is used to 'activate' the ROMDIS/RAMDIS signal(see IC1A) causing the CPC's ROM to be disabled. Cleared by RESETThe static ram is then readable in the address space from 0-fff.* Freeze button seems to trigger normal interrupt A9 of the port address (not NMIwhen '1'?)* Seems like there (see IC1B) is rom and ram used to 'activate' the RAMDIS signal causing the CPC's RAM to be disabled. This allows the static RAM to be read/written in the range 1000-1fff since accessdepends on A12 (see IC7A).It's not clear if both are visible.It's not clear how the entire space can be written to.