Notice: Trying to access array offset on value of type bool in /mnt/cpcwiki-httpdocs/includes/libs/IPSet.php on line 243

Notice: Trying to access array offset on value of type bool in /mnt/cpcwiki-httpdocs/includes/libs/IPSet.php on line 246

Notice: Trying to access array offset on value of type bool in /mnt/cpcwiki-httpdocs/includes/libs/IPSet.php on line 243

Notice: Trying to access array offset on value of type bool in /mnt/cpcwiki-httpdocs/includes/libs/IPSet.php on line 246
Changes - CPCWiki
Open main menu

Changes

VHDL

2 bytes removed, 13:45, 5 March 2017
Its syntaxe does look like ADA language. It differs from computer langage as its first instruction does generaly look like :
if rising_edge(clock) then
output_write output_wire <= input_write input_wire xor 1;
end if;
Freemac
1,218
edits