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Changes - CPCWiki

Changes

Z80-DART/Z80-SIO chip

2 bytes removed, 15:27, 5 January 2010

/* Control Registers */

0=No action

1=DART: Reserved, SIO: Reset Receive CRC Checker

2=DART: Reserved, SIO: Reset Transmit CRC Generator

3=DART: Reserved, SIO: Reset Tx Underrun/End of Message latch

2=SDLC Mode (0111 1110 Flag) (SIO only, not DART)

3=External SYNC Mode (SIO only, not DART)

6-7 Rx/Tx DART clock mode (0..3=X1, X16, X32, X64)

6,388

edits