Each chip has its own challenges:
*[[Z80]] is a bloated architecture, with lots of special cases and complex bus logic. The difference with the lean [[MOS 6502|6502]] is striking.
*[[CRTC]] has a character-based addressing scheme, many incompatible implementations, and requires an accurate VDU implementation too.
*[[Gate Array]] has a weird interrupt system and adds an unnecessary layer of complexity to sync signals.
*[[ASIC]] is buggy and lacks precise documentation.