Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.
Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]
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= Optimized version versions =
The unlocking sequence can be reconstituted from simple bit operations instead of being stored in memory.
== In Z80 Assembler [[Madram]] version == It still uses some magic numbers.
This allowed [[Madram]] to create this optimized lock-unlock routine:
<pre>
UnlockAsic
di
ld bc,#BCFF
ld hl,%1001000011101010
.loop:
out (c),c
ld a,h:rlca:ld h,l:ld l,a
ld c,a
cp #4D
jr nz,.loop
ld a,#CD ; a=#CD for unlock, another value for lock
out (c),a:out (c),a
ei
</pre>
Another optimized unlock routine by == [[Urusergi]]:version == No magic numbers here.
<pre>
di ; v3.1 -> 30 bytes!
ld bc,#BCFF
out (c),c
out (c),0 ; db #ED,#71
ld a,c
.loop:
out (c),a
ld dh,a ; D h = 7654 3210rlca:rlca add hl,hl ; h = 6543 210*rra ; a = 7765 4321add hl,hl ; A h = 5432 107610**xor dh:and #7FF7:xor d h ; A a = 7432 10767765 1321ld el,arlca ; A l = 4321 07677765 1321xor e ld a,h ; A a = 7432 1076 XOR 4321 07675432 10**rrc d rla ; D a = 0765 43210***xor d:and #88:xor d l ; A a = (7 xor 4)765 (1 xor 0)321
cp c
jr nz,.loop
ei
</pre>
== In Python [[Longshot]] version == Interleave keys here28 bytes - 349 nops
<pre>
def unlock_asicAsic_Unlock ld de,#533e ; interleave key 32 bits ld hl,#849 ; interleave key (#841 to lock): bld a, #ffld bc,#bcef ; crtc input io address and 1st nibblesout (c), ha ; RQ00 <>0out (c), l = 0xBC, 0xFF0 ; defb #ed, 0x90, 0xEA # Initialize registers71 ; Send 00 (out (c),0 port_outAsic_Unlock_Loop:out (bc), a ; Send 2 nibblesxor h ; Put bit 12 of the key in the bit 4 of A for high nibbleand c ; erase bit 4 to put key bit insteadxor hadc hl,hl ; Extract left incoming bit of high nibble of interleave keyret z ; exit when key is empty (extra value sent to io address) port_outex de,hl ; Switch the interleave key (badd hl, 0hl is good for you)rra ; Bit 7 high nibble=Cf and rotate the complete byteadd hl,hl ; Extract left incoming bit of low nibble of interleave key jr Asic_Unlock_Loop ; Send at last 18 values to crtc input io address</pre>
while c != 0x4D: port_out(b, c) h, l = l, ((h << 1) | (h >> 7)) & 0xFF # Rotate h and swap h, l c Algorithm == ((c >> 1) & ~(1 << 3)) | (l & 0x88) # Modify c
<pre>def unlock_asic(): b, c = 0xBC, 0xFF port_outout(b, 0xCDc) port_outout(b, 0xCD0) a = c while True: out(b, a) # a = (7 xor 4)765 (1 xor 0)321 a = ((a >> 1) & 0x77) | ((a ^ (a << 3)) & 0x80) | (((a << 2) ^ (a << 3)) & 0x08) if a == c: break
def port_outout(port, value): print(f"Port: {hex(port)}xx Out: {hex(value)}")
unlock_asic()
= Patent =
For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
On the [[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, it is precised at §2.11 "Locking of enhanced features":
</code>
According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
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[[Category:Programming]]
[[Category:CPC Plus]]