Z80 - Revision history

Phi2x at 18:37, 30 April 2025

2025-04-30T18:37:13Z

Phi2x at 18:36, 30 April 2025

2025-04-30T18:36:28Z

Phi2x at 18:35, 30 April 2025

2025-04-30T18:35:32Z

Phi2x at 18:27, 30 April 2025

2025-04-30T18:27:50Z

Phi2x at 18:23, 30 April 2025

2025-04-30T18:23:14Z

Phi2x at 18:22, 30 April 2025

2025-04-30T18:22:50Z

Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /mnt/cpcwiki-httpdocs/includes/diff/DairikiDiff.php on line 434

Phi2x: /* Interrupt Acknowledge */

2025-04-30T15:40:22Z

‎Interrupt Acknowledge

Phi2x: /* Description */

2025-04-30T13:27:22Z

‎Description

Phi2x: /* Description */

2025-04-30T09:21:37Z

‎Description

Phi2x: /* Description */

2025-04-30T07:20:50Z

‎Description

Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /mnt/cpcwiki-httpdocs/includes/diff/DairikiDiff.php on line 434

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 The Z80 was also used as a dual CPU in many computers in order to have [[CP/M]] compatibility:
-* the [[Commodore 64|Commodore C128]] had one
+* the [[Commodore 64|Commodore C128]] had one built-in
 * the Acorn Z80 Second Processor expansion for the [[BBC Micro]]
 * the popular Z-80 SoftCard expansion for the [[Apple II]]

@@ Line 9: / Line 9: @@
 * the popular Z-80 SoftCard expansion for the [[Apple II]]
 * the ATR8000 expansion for the [[Atari 8-bit]]
-* the [[C64]] had a Z80 CP/M expansion cartridge
+* the Z80 CP/M expansion cartridge for the [[C64]]
 The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].

@@ Line 8: / Line 8: @@
 * the Acorn Z80 Second Processor expansion for the [[BBC Micro]]
 * the popular Z-80 SoftCard expansion for the [[Apple II]]
-* the [[C64]] had a Z80 CP/M expansion cartridge, although it was not very usable due to its 40-column display
+* the ATR8000 expansion for the [[Atari 8-bit]]
 The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].

@@ Line 8: / Line 8: @@
 * the Acorn Z80 Second Processor expansion for the [[BBC Micro]]
 * the popular Z-80 SoftCard expansion for the [[Apple II]]
-* the C64 had a Z80 CP/M expansion cartridge, although it was not very usable due to its 40-column display
+* the [[C64]] had a Z80 CP/M expansion cartridge, although it was not very usable due to its 40-column display
 The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].

@@ Line 5: / Line 5: @@
 The Z80 was also used as a dual CPU in many computers in order to have [[CP/M]] compatibility:
-" the [[Commodore 64|Commodore C128]] had one
+* the [[Commodore 64|Commodore C128]] had one
 * the Acorn Z80 Second Processor expansion for the [[BBC Micro]]
 * the popular Z-80 SoftCard expansion for the [[Apple II]]

@@ Line 4: / Line 4: @@
 The Z80/Z80A was a very popular microprocessor, used in a wide range of applications, from gaming consoles like the [[ColecoVision]], the [[Sega Master System]] and [[Sega GameGear]] to personal computers like the [[ZX81]], [[ZX Spectrum]] and [[MSX]].
-It was used in the [[Commodore 64|Commodore C128]] as a secondary processor in order to achieve [[CP/M]] compatibility. Similarly, the Acorn Z80 Second Processor expansion for the [[BBC Micro]] enabled [[CP/M]] compatibility. And the popular Z-80 SoftCard expansion did the same for the [[Apple II]].
+The Z80 was also used as a dual CPU in many computers in order to have [[CP/M]] compatibility:
 The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].

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 | Non-Maskable Interrupt || 11 (5, 3, 3) || M1, Int(1), MW (Push PCH), MW (Push PCL) || iff2 := iff1, iff1 := 0, sp -= 2, (sp) := pc, pc := 0066h || Highest priority interrupt. Cannot be disabled by `DI`. Fixed vector address. Saves previous IFF1 state.
 |-
-| Interrupt Mode 0 || 13+ (Typically 13 for RST) || M1 (IntAck + 2wait), Int(1), plus cycles for fetched instruction (e.g., MW, MW for RST) || Fetches instruction from Data Bus during acknowledge cycle; Executes fetched instruction (usually `RST nn`) || 8080 compatible mode. Relies on interrupting peripheral to supply an instruction byte (typically `RST`). Cycle count depends on the instruction supplied (13T is for a 1-byte `RST`).
+| Interrupt in Mode 0 || 13+ (Typically 13 for RST) || M1 (IntAck + 2wait), Int(1), plus cycles for fetched instruction (e.g., MW, MW for RST) || Fetches instruction from Data Bus during acknowledge cycle; Executes fetched instruction (usually `RST nn`) || 8080 compatible mode. Relies on interrupting peripheral to supply an instruction byte (typically `RST`). Cycle count depends on the instruction supplied (13T is for a 1-byte `RST`).
 |-
-| Interrupt Mode 1 || 13 (7, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL) || iff1 := 0, sp -= 2, (sp) := pc, pc := 0038h || Simple mode, always jumps to fixed address `0038h`. No data needed from peripheral during acknowledge.
+| Interrupt in Mode 1 || 13 (7, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL) || iff1 := 0, sp -= 2, (sp) := pc, pc := 0038h || Simple mode, always jumps to fixed address `0038h`. No data needed from peripheral during acknowledge.
 |-
-| Interrupt Mode 2 || 19 (7, 3, 3, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL), MR (Read Vector Low), MR (Read Vector High) || iff1 := 0, sp -= 2, (sp) := pc, pc := '''('''(I << 8) + V''')''' || Most flexible mode. Forms pointer `(I * 256) + V` where `V` is vector byte from peripheral (LSB ignored). Reads 16-bit target address from pointer address. `I` register must be set up beforehand.
+| Interrupt in Mode 2 || 19 (7, 3, 3, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL), MR (Read Vector Low), MR (Read Vector High) || iff1 := 0, sp -= 2, (sp) := pc, pc := '''('''(I << 8) + V''')''' || Most flexible mode. Forms pointer `(I * 256) + V` where `V` is vector byte from peripheral (LSB ignored). Reads 16-bit target address from pointer address. `I` register must be set up beforehand.
 |}

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 The Z80 microprocessor is an 8-bit [[CPU]] with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.
-The Z80 instruction set is really 3 separate subsets each occupying 256 opcode ‘slots’. The main and CB subsets each occupy the full range of 256 instructions, while the ED subset is mostly empty and only implements 59 instructions. DD and FD instruction prefixes are not counted as they are just modifiers. This means there are 571 unique instructions in the Z80 instruction set.
+The Z80 instruction set is really 3 separate subsets each occupying 256 opcode ‘slots’. The main and CB subsets each occupy the full range of 256 instructions, while the ED subset is mostly empty and only implements 59 instructions. DD and FD instruction prefixes are not counted as they are just modifiers to use the index registers. This means there are 571 unique instructions in the Z80 instruction set.
 Although it lacks the raw processing power of processors like the Intel 80x86 or the [[Motorola 68000]] series, the Z80 is extremely useful for low cost control applications.

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 The Z80 microprocessor is an 8-bit [[CPU]] with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.
-It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, access to an additional 308 instructions. Although it lacks the raw processing power of processors like the Intel 80x86 or the [[Motorola 68000]] series, the Z80 is extremely useful for low cost control applications.
+The Z80 instruction set is really 3 separate subsets each occupying 256 opcode ‘slots’. The main and CB subsets each occupy the full range of 256 instructions, while the ED subset is mostly empty and only implements 59 instructions. DD and FD instruction prefixes are not counted as they are just modifiers. This means there are 571 unique instructions in the Z80 instruction set. [https://floooh.github.io/2021/12/06/z80-instruction-timing.html Source]
 The Z80 has about 8500 transistors. To put it into perspective, 64KB of DRAM contains 524288 transistors, as 1 bit of DRAM needs 1 transistor. Fun fact: an Amstrad CPC equipped with a 4MB RAM expansion has 32 million transistors dedicated to RAM while the Z80 CPU still has only 8500 transistors.