Talk:Z80 STI RS232 interface - Revision history

Octoate: moved Talk:Tim Riemann's RS232 interface to Talk:Z80 STI RS232 interface: The title shouldn't contain a real name

2011-04-29T20:44:17Z

moved Talk:Tim Riemann's RS232 interface to Talk:Z80 STI RS232 interface: The title shouldn't contain a real name

Nocash at 20:56, 10 May 2010

2010-05-10T20:56:50Z

Bryce at 20:37, 10 May 2010

2010-05-10T20:37:55Z

Nocash at 19:59, 10 May 2010

2010-05-10T19:59:17Z

Bryce at 19:38, 10 May 2010

2010-05-10T19:38:56Z

Nocash at 19:15, 10 May 2010

2010-05-10T19:15:11Z

Bryce at 17:00, 10 May 2010

2010-05-10T17:00:51Z

Bryce at 15:19, 10 May 2010

2010-05-10T15:19:56Z

Bryce: Created page with 'The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the…'

2010-05-10T15:19:09Z

Created page with 'The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the…'

New page

The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY of the four upper addresses decoded from the 3 Address pins at the input.

← Older revision		Revision as of 20:56, 10 May 2010
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	Bryce.		Bryce.
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		+	:Sounds like the Maplin rombox thing (it has "pre-decoded" signals for further expansions, too). Yup, that explains how the multiplexer crept into the schematic.

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	:Yes, fragments of it do have some purpose. It's just terribly overcomplicated. You've seen the original Schneider solution (the other schematic on the same page), don't you? They used only 2 chips, not 5 chips for port decoding. --[[User:Nocash\|Nocash]] 19:59, 10 May 2010 (UTC)		:Yes, fragments of it do have some purpose. It's just terribly overcomplicated. You've seen the original Schneider solution (the other schematic on the same page), don't you? They used only 2 chips, not 5 chips for port decoding. --[[User:Nocash\|Nocash]] 19:59, 10 May 2010 (UTC)
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		+	Ah, ok, now I understand why you think it's nonsense... But you're missing some background information about the schematic. The original circuit was a modular design, with one address decoder that was used on several projects and all projects were compatible with each other and could be expanded much further. As far as I can remember, there was a 24bit I/O Port, 8bit Printer Port and even an EPROM burner, which all used the same decoder and all of them could even be built in parallel together on one board, so the decoder has a lot of potential, that's not being utilised on this particular project. The other 4 outputs on the 74LS138 were used for the other expansions, but obviously they are overkill if all you wanted was the RS232 Port. Does it make more sense now?
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		+	Bryce.

← Older revision		Revision as of 19:59, 10 May 2010
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	Bryce.		Bryce.
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		+	:Yes, fragments of it do have some purpose. It's just terribly overcomplicated. You've seen the original Schneider solution (the other schematic on the same page), don't you? They used only 2 chips, not 5 chips for port decoding. --[[User:Nocash\|Nocash]] 19:59, 10 May 2010 (UTC)

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	:Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses.		:Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses.
	:Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --[[User:Nocash\|Nocash]] 19:15, 10 May 2010 (UTC)		:Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --[[User:Nocash\|Nocash]] 19:15, 10 May 2010 (UTC)
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		+	Yes, it maps all four addresses as you state correctly, just the bit about calling it non-sense is what I disagree with - If any of the four addresses are selected, the output of the 74LS20 activates the Chip Select on the STI and then in combination with the connections to pins 32-35 on the STI allows that each register can be individually addressed by the amstrad. How else would you achieve this without the configuration shown in the schematic? What signal should activate the STI CS pin, if not this one? How would you do it?
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		+	Bryce.

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	Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest.		Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest.
		+
		+	:Bryce, my interpretation in Note 2 is EXACTLY the same as what you are saying. It maps to ALL four addresses.
		+	:Thus, the decoding of the "lower" two addressbits (A2,A3) is total nonsense, really. --[[User:Nocash\|Nocash]] 19:15, 10 May 2010 (UTC)

← Older revision	Revision as of 20:44, 29 April 2011
(No difference)

← Older revision		Revision as of 17:00, 10 May 2010
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−	The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input.	+	The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate).
		+
		+	Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input. This is of course required for the circuit to function properly and definitely NOT nonsense to avoid legal issues as you suggest.

← Older revision		Revision as of 15:19, 10 May 2010
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−	The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY of the four ~~upper~~ addresses decoded from the 3 Address pins at the input.	+	The symbol in the Schematic for the 74LS20 is incorrect (Should be a 4 input NAND gate). Your interpretation of the schematic in Note 2 is also incorrect. The combination of the 74LS138 followed by the 74LS20 means that the STI is mapped to ANY/ALL of the four lower addresses decoded from the 3 Address pins at the input.