Programming:Unlocking ASIC - Revision history

Longshot at 21:10, 21 November 2025

2025-11-21T21:10:06Z

2025-11-21T19:19:29Z

Another algorithm

2025-04-09T08:59:55Z

‎Patent

2025-04-09T08:51:47Z

2025-04-07T19:10:45Z

‎Urusergi version

2025-04-07T17:52:26Z

‎Patent

2025-04-07T14:38:20Z

‎Urusergi version

2025-04-06T13:02:42Z

‎Urusergi version

2025-04-05T21:52:27Z

‎Algorithm

2025-04-05T17:22:26Z

‎Urusergi version

@@ Line 143: / Line 143: @@
 rra			; Bit 7 high nibble=Cf and rotate the complete byte
 add hl,hl		; Extract left incoming bit of low nibble of interleave key
-jr Asic_Unlock_Loop	; Send at last 20 values to crtc input io address
+jr Asic_Unlock_Loop	; Send at last 18 values to crtc input io address
 </pre>

@@ Line 118: / Line 118: @@
 ei
 ret
 </pre>

@@ Line 154: / Line 154: @@
 = Patent =
-For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]).
+For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
-−
 The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
 On the [[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, it is precised at §2.11 "Locking of enhanced features":

← Older revision		Revision as of 08:51, 9 April 2025
Line 8:		Line 8:

	Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.		Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.
		+
		+	Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]

	<br>		<br>

@@ Line 94: / Line 94: @@
 <pre>
-di			; v3.0 -> 30 bytes!
+di			; v3.1 -> 30 bytes!
 ld bc,#BCFF
 out (c),c

@@ Line 161: / Line 161: @@
 </code>
 <br>
 [[Category:Programming]]
 [[Category:CPC Plus]]

@@ Line 107: / Line 107: @@
 add hl,hl		; h = 5432 10**
 xor h:and #F7:xor h	; a = 7765 1321
 ld l,a			; l = 7765 1321
-ld a,h			; a = 4321 0***
+ld a,h			; a = 5432 10**
 and #88:xor l		; a = (7 xor 4)765 (1 xor 0)321
 cp c

@@ Line 97: / Line 97: @@
 ld bc,#BCFF
 out (c),c
-out (c),0
+out (c),0		; db #ED,#71
 ld a,c

@@ Line 134: / Line 134: @@
 def out(port, value):
-     print(f"Port: {hex(port)} Out: {hex(value)}")
+     print(f"Port: {hex(port)}xx  Out: {hex(value)}")
 unlock_asic()