Plus Vectored Interrupt Bug - Revision history

Phi2x: /* Weblinks */

2024-04-17T18:20:48Z

‎Weblinks

Phi2x: /* Weblinks */

2024-04-17T18:16:23Z

‎Weblinks

Phi2x: /* Weblink */

2024-04-17T17:44:25Z

‎Weblink

Phi2x: /* Weblink */

2024-04-17T17:43:47Z

‎Weblink

Phi2x at 17:42, 17 April 2024

2024-04-17T17:42:46Z

Arnoldemu at 10:44, 11 March 2018

2018-03-11T10:44:34Z

Arnoldemu at 13:47, 30 July 2017

2017-07-30T13:47:38Z

Arnoldemu at 11:51, 30 July 2017

2017-07-30T11:51:43Z

Arnoldemu: /* The Vectored Interrupt Bug */

2017-07-30T10:21:24Z

‎The Vectored Interrupt Bug

Arnoldemu: /* The Vectored Interrupt Bug */

2017-07-30T10:17:28Z

‎The Vectored Interrupt Bug

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 == Weblinks ==
-*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/amstrad-plus-and-im2-bug/ Amstrad Plus and IM2 bug] Related topic on CPCWiki forum
+*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/amstrad-plus-and-im2-bug/ Amstrad Plus and IM2 bug] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/asic-im-2-vector/ ASIC IM2 vector] Related topics on CPCWiki forum
 *[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]
 *[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Le bug DMA0 vs PRI (FR)]
 [[Category:Hardware]]

@@ Line 106: / Line 106: @@
 == Weblinks ==
 *[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]
 *[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Le bug DMA0 vs PRI (FR)]
 [[Category:Hardware]]

@@ Line 104: / Line 104: @@
 The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.
-== Weblink ==
+== Weblinks ==
 *[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]

@@ Line 107: / Line 107: @@
 *[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]
-*[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Bug DMA0 vs PRI (FR)]
+*[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Le bug DMA0 vs PRI (FR)]
 [[Category:Hardware]]

← Older revision		Revision as of 17:42, 17 April 2024
Line 103:		Line 103:

	The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.		The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.
		+
		+	== Weblink ==
		+
		+	*[https://asmtradcpc.zilog.fr/docs/Interruptions_-_modes_et_fonctionnement.php Le bug des interruptions cpc+ (FR)]
		+	*[http://quasar.cpcscene.net/doku.php?id=assem:asic#les_interruptions_de_l_asic Bug DMA0 vs PRI (FR)]

	[[Category:Hardware]]		[[Category:Hardware]]

← Older revision		Revision as of 10:44, 11 March 2018
Line 103:		Line 103:

	The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.		The logic around the Z80 shortens or lengthens the IORQ based on A13 and that is why the bug doesn't happen when A13=1.
		+
		+	[[Category:Hardware]]

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 Following discussions on cpcwiki involving roudoudou, Longshot, gerald, arnoldemu and dragon the cause of the bug has been identified, through testing and from analysis by gerald with his logic analyzer and a workaround has been identified.
-The bug relates to the raster interrupt. When a raster interrupt is acknowledged sometimes the vector will be 6 (for raster interrupt) or 4 (for dma channel 0 - the lowest priority interrupt).
+This bug has mostly been seen when using the raster interrupt.
 *  If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't occur with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.
 * If the instruction at the time of interrupt acknowledge is located in a memory region where A13=1 then the bug doesn't happen.
 There are workarounds:

@@ Line 9: / Line 9: @@
 The Z80 will then read a 2-byte address which is the location of the interrupt handler.
-Bit 0 of the vector will be 0. Bits 3..1 are generated by the ASIC based on the interrupt source (one of the DMA channels or raster interrupt). Bits 7..4 are defined by writing a value to the ASIC IVR register (at &6805 in the ASIC registers).
+Bit 0 of the vector will be 0. Bits 2..1 are generated by the ASIC based on the interrupt source (one of the DMA channels or raster interrupt). Bits 7..3 are defined by writing a value to the ASIC IVR register (at &6805 in the ASIC registers).
 The raster interrupt interrupt comes from the CPC compatible 52-line interrupt OR the Plus programmable line interrupt (PRI at &6800 in the ASIC registers).
@@ Line 74: / Line 74: @@
 The bug relates to the raster interrupt. When a raster interrupt is acknowledged sometimes the vector will be 6 (for raster interrupt) or 4 (for dma channel 0 - the lowest priority interrupt).
-*  If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.
+*  If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't occur with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.
 * If the instruction at the time of interrupt acknowledge is located in a memory region where A13=1 then the bug doesn't happen.

@@ Line 76: / Line 76: @@
 *  If the instruction at the time of interrupt acknowledge is located in a memory region where A13=0 then the bug happens. The bug is not dependent on RAM or ROM or I register value. The location of the interrupt handler code is also not important. The location of the instruction is important. The bug also doesn't with opcodes that don't use memory read/write or don't contain a memory read/write when fetching the opcode. Single byte instructions are fine including HALT. However, it is difficult to code in a way to workaround the issue in this way.
-* If the instruction at the time of interrupt acknowledge is located in a memory region where A13=1 then the bug doesn't happen. Therefore to workaround the issue put your code between &2000-&3fff, &6000-&7fff, &a000-&bfff, &e000-&ffff. You can place your I value anywhere and the code for your interrupt handlers can be anywhere.
+* If the instruction at the time of interrupt acknowledge is located in a memory region where A13=1 then the bug doesn't happen.
 == Technical ==