PAL16L8 - Revision history

Phi2x at 14:14, 13 May 2025

2025-05-13T14:14:21Z

2025-04-07T16:03:06Z

‎4MB RAM expansions

2025-04-07T11:07:08Z

‎4MB RAM expansions

2025-04-07T11:04:25Z

‎576KB vs 640KB total

2025-04-02T12:45:55Z

‎Page order

2025-04-02T12:45:28Z

‎Page order

2025-04-02T12:44:44Z

‎Page order

2025-04-02T12:08:27Z

‎RAM mode &C3

2025-04-02T11:39:10Z

‎PAL MMR register

2025-03-04T04:42:14Z

‎PAL and ASIC

@@ Line 4: / Line 4: @@
 On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.
 <br>
@@ Line 283: / Line 273: @@
 [[File:Amstrad.cpc6128.pal.ga.jpg]]
 <br>

← Older revision		Revision as of 16:03, 7 April 2025
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	Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB RAM expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.		Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB RAM expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.
		+
		+	See the [[Default I/O Port Summary\|I/O Port Allocation Rules]] to understand why.

	The practical safe maximum on Amstrad CPC with [[Standard Memory Expansions]] is 2MB.		The practical safe maximum on Amstrad CPC with [[Standard Memory Expansions]] is 2MB.

@@ Line 296: / Line 296: @@
 == 4MB RAM expansions ==
-Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.
+Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB RAM expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.
 The practical safe maximum on Amstrad CPC with [[Standard Memory Expansions]] is 2MB.

← Older revision		Revision as of 11:04, 7 April 2025
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	However, if the RAM expansion decodes the [[Standard_Memory_Expansions#Extended_1M-4M_Expansions_.28RAM7.2FYarek-style.29\|A8 address line]], you can access the internal second RAM bank of the 6128 from another range (&7Exx). The [[X-MEM]] and [[CPC_iRAM#CPC_iRAM.2F640\|iRAM/640]] expansions implement this and therefore can provide 640K of total RAM. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-to-640kb-for-cpc6128-on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 Source]		However, if the RAM expansion decodes the [[Standard_Memory_Expansions#Extended_1M-4M_Expansions_.28RAM7.2FYarek-style.29\|A8 address line]], you can access the internal second RAM bank of the 6128 from another range (&7Exx). The [[X-MEM]] and [[CPC_iRAM#CPC_iRAM.2F640\|iRAM/640]] expansions implement this and therefore can provide 640K of total RAM. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-to-640kb-for-cpc6128-on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 Source]
		+
		+	<br>
		+
		+	== 4MB RAM expansions ==
		+
		+	Beware about 4MB RAM expansions. The upper 2MB (Port 7Bxxh, 7Axxh, 79xxh, 78xxh) of a 4MB expansion can conflict with other hardware as setting A10 to 0 is also used for many hardware expansions.
		+
		+	The practical safe maximum on Amstrad CPC with [[Standard Memory Expansions]] is 2MB.

	<br>		<br>

@@ Line 120: / Line 120: @@
 RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx.
-Given this diversity of expansions, [[SymbOS]] does the right thing by testing each 64k page individually to detect the available RAM.
+Given this diversity of RAM expansions, [[SymbOS]] does the right thing by testing each 64k page individually to detect the available RAM.
 <br>

← Older revision		Revision as of 12:44, 2 April 2025
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	RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx.		RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx.
		+
		+	Given this diversity of expansions, [[SymbOS]] does the right thing by testing each 64KB page individually to detect the available RAM.

	<br>		<br>

@@ Line 126: / Line 126: @@
 The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does.
-So external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
+So external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion].
 <br>

@@ Line 33: / Line 33: @@
 == PAL MMR register ==
-This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the [[Gate Array]] can only access the Base 64k page of RAM.
+This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all (even in C3 mode). The [[Gate Array]] can only access the unmapped Base 64k page of RAM.
 {| class="wikitable"

@@ Line 156: / Line 156: @@
 The PAL component is integrated inside the ASIC chip. But it is disabled by default on the 464 Plus and GX4000. [https://www.cpcwiki.eu/forum/news-events/announcing-sonic-gx-a-new-episode-of-sonic-the-hedgehog-for-amstrad-gx-4000/msg248436/#msg248436 Source]
-Most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
+Besides, most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
 The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.