Gate Array - Revision history

Longshot: correction of an error relating to IC

2025-05-30T11:58:37Z

correction of an error relating to IC

Longshot: Interruption chapter

2025-05-30T11:18:20Z

Interruption chapter

Longshot at 12:17, 24 May 2025

2025-05-24T12:17:06Z

Phi2x: Removing the false allegations. It is all based on common knowledge.

2025-05-24T10:05:17Z

Removing the false allegations. It is all based on common knowledge.

Phi2x: Undo revision 126273 by Longshot (talk) Repairing the wiki

2025-05-24T10:01:56Z

Undo revision 126273 by Longshot (talk) Repairing the wiki

Longshot: Deleted for infringement of copyrighted material protected under the CC BY-NC-ND 4.0 license

2025-05-24T08:37:02Z

Deleted for infringement of copyrighted material protected under the CC BY-NC-ND 4.0 license

Phi2x at 20:38, 22 May 2025

2025-05-22T20:38:06Z

Longshot at 18:09, 21 May 2025

2025-05-21T18:09:13Z

Longshot: Added information on citation issues

2025-05-21T18:07:06Z

Added information on citation issues

Longshot: /* External links */

2025-05-18T22:07:15Z

‎External links

@@ Line 95: / Line 95: @@
 The interrupt is generated anyway, but:
 * If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).
-* Otherwise, IC = 0.
+* Otherwise bit 5 of IC is set to zero.
 == Controlling the Gate Array  ==

← Older revision		Revision as of 11:18, 30 May 2025
Line 58:		Line 58:

	<br>		<br>
		+
		+	== Interrupt generation ==
		+	[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
		+
		+	The CPU maskable interrupts are generated by the Gate Array.
		+	This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC.
		+
		+	On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
		+
		+	When the CPU acknowledge the interrupt (eg. it is going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 32 HSync.
		+
		+	When a VSync occurs, the Gate Array will wait for two HSync and:
		+
		+	* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.
		+	* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.
		+
		+	This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed.
		+
		+	So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.
		+
		+	The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…
		+
		+	Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
		+
		+	=== Timings ===
		+	[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
		+
		+	The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).
		+
		+	=== DI in peace ===
		+	[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]
		+
		+	The GA maintains its int request until it is accepted.
		+	RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.
		+	But after the EI, a test similar to the one seen for the VBL is performed:
		+	The interrupt is generated anyway, but:
		+	* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).
		+	* Otherwise, IC = 0.

	== Controlling the Gate Array ==		== Controlling the Gate Array ==

← Older revision		Revision as of 12:17, 24 May 2025
Line 56:		Line 56:

	Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]		Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
−
−	~~<br>~~
−
−	~~== Interrupt generation ==~~
−
−	Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
−
−	On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.
−
−	~~R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:~~
−	* When it exceeds 51
−	* By setting bit4 of the RMR register of the Gate Array to 1
−	* At the end of the 2nd HSYNC after the start of the VSYNC
−
−	~~When the Gate Array sends an interrupt request:~~
−	*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
−	*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
−
−	~~Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.~~
−
−	~~<br>~~
−
−	~~== CSYNC signal ==~~
−
−	The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.
−
−	~~When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.~~
−
−	~~If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.~~
−
−	~~C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).~~
−
−	~~For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.~~
−
−	On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.
−
−	~~The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:~~
−	* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
−	* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
−
−	~~If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.~~
−
−	~~The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.~~
−
−	~~C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.~~
−
−	On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

	<br>		<br>

@@ Line 60: / Line 60: @@
 == Interrupt generation ==
 Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
@@ Line 82: / Line 79: @@
 == CSYNC signal ==
 The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

← Older revision		Revision as of 10:01, 24 May 2025
Line 56:		Line 56:

	Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]		Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
		+
		+	<br>
		+
		+	== Interrupt generation ==
		+	* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
		+	** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
		+	** ''Author: Serge Querné ([[Longshot]])''
		+
		+	Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
		+
		+	On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.
		+
		+	R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
		+	* When it exceeds 51
		+	* By setting bit4 of the RMR register of the Gate Array to 1
		+	* At the end of the 2nd HSYNC after the start of the VSYNC
		+
		+	When the Gate Array sends an interrupt request:
		+	*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
		+	*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
		+
		+	Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
		+
		+	<br>
		+
		+	== CSYNC signal ==
		+	* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
		+	** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
		+	** ''Author: Serge Querné ([[Longshot]])''
		+
		+	The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.
		+
		+	When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.
		+
		+	If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.
		+
		+	C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).
		+
		+	For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.
		+
		+	On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.
		+
		+	The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
		+	* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
		+	* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
		+
		+	If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.
		+
		+	The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.
		+
		+	C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.
		+
		+	On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

	<br>		<br>

← Older revision		Revision as of 08:37, 24 May 2025
Line 56:		Line 56:

	Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]		Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
−
−	~~<br>~~
−
−	~~== Interrupt generation ==~~
−	* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
−	** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
−	** ''Author: Serge Querné ([[Longshot]])''
−
−	Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
−
−	On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.
−
−	~~R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:~~
−	* When it exceeds 51
−	* By setting bit4 of the RMR register of the Gate Array to 1
−	* At the end of the 2nd HSYNC after the start of the VSYNC
−
−	~~When the Gate Array sends an interrupt request:~~
−	*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
−	*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
−
−	~~Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.~~
−
−	~~<br>~~
−
−	~~== CSYNC signal ==~~
−	* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
−	** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
−	** ''Author: Serge Querné ([[Longshot]])''
−
−	The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.
−
−	~~When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.~~
−
−	~~If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.~~
−
−	~~C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).~~
−
−	~~For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.~~
−
−	On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.
−
−	~~The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:~~
−	* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
−	* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.
−
−	~~If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.~~
−
−	~~The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.~~
−
−	~~C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.~~
−
−	On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

	<br>		<br>

@@ Line 62: / Line 62: @@
 * '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
 ** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf  The Amstrad CPC CRTC Compendium]''
-** ''Author: Serge Querné (Longshot)''
+** ''Author: Serge Querné ([[Longshot]])''
 Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
@@ Line 84: / Line 84: @@
 * '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
 ** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf  The Amstrad CPC CRTC Compendium]''
-** ''Author: Serge Querné (Longshot)''
+** ''Author: Serge Querné ([[Longshot]])''
 The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

@@ Line 76: / Line 76: @@
 *If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
 *If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
 Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.
@@ Line 112: / Line 110: @@
 On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.
 <br>

@@ Line 790: / Line 790: @@
 == External links ==
 *[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
 * [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
 * [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]