FPGA - Revision history

Arnoldemu at 12:21, 11 March 2018

2018-03-11T12:21:54Z

Dingo: expanded a bit.

2017-03-09T04:25:47Z

expanded a bit.

Freemac: Created page with "FPGA (field-programmable gate array) This is a reprogrammable ASIC chip. You know what a "truth table" is ? Here a example :
'''XOR''' truth table : A B | C 0 0 | 0..."

2017-03-05T13:55:40Z

Created page with "FPGA (field-programmable gate array) This is a reprogrammable ASIC chip. You know what a "truth table" is ? Here a example :<br /> '''XOR''' truth table : A B | C 0 0 | 0..."

New page

FPGA (field-programmable gate array)

This is a reprogrammable ASIC chip.

You know what a "truth table" is ? Here a example :<br />
'''XOR''' truth table :
A B | C
0 0 | 0
0 1 | 1
1 0 | 1
1 1 | 0

In a truth table you have got 2 input wires, and 1 output wires.

In ASIC you have got 10000000000000000 input/output wires.

As it is complex to feed the table values, a special language was make to feel them : [[VHDL]] (and -blech!!!- verilog)

GA in Amstrad is an ASIC.

← Older revision		Revision as of 12:21, 11 March 2018
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	Common CPLDs are made by Atheros (now part of Intel) and Altera.		Common CPLDs are made by Atheros (now part of Intel) and Altera.
		+
		+	[[Category:Hardware]]

@@ Line 1: / Line 1: @@
 FPGA (field-programmable gate array)
-This is a reprogrammable ASIC chip.
+This is a reprogrammable [[COTS]] Instruction set Processor (IP). It consists of a re-programmable ("FP") Gate Array (GA), i.e. a [[FET]] (Field-Effect Transistor) array where the transistors can be set by the FET Gate to "conduct" or "resist". This can flexibly simulate many different logical ICs.
 You know what a "truth table" is ? Here a example :<br />
 '''XOR''' truth table :
@@ Line 11: / Line 12: @@
 1 | 0
-In a truth table you have got 2 input wires, and 1 output wires.
+In a truth table you have got eg. 2 input wires, and 1 output wires.
-In ASIC you have got 10000000000000000 input/output wires.
+A FPGA is programmed by a LUT (Look-Up Table) that has to be loaded into volatile memory at power-up. In a FPGA LUT you have got 10,000,000,000,000,000 input/output wires.
-As it is complex to feed the table values, a special language was make to feel them : [[VHDL]] (and -blech!!!- verilog)
+As it is complex to feed the table values, special languages (HDL - Hardware Description Language) are used to feed them : [[VHDL]] (and -blech!!!- verilog)
-GA in Amstrad is an ASIC.
+The Gate Array (GA) in Amstrad graphics is an [[ASIC]].

FPGA - Revision history

Arnoldemu at 12:21, 11 March 2018

Dingo: expanded a bit.

Freemac: Created page with "FPGA (field-programmable gate array) This is a reprogrammable ASIC chip. You know what a "truth table" is ? Here a example : '''XOR''' truth table : A B | C 0 0 | 0..."

Freemac: Created page with "FPGA (field-programmable gate array) This is a reprogrammable ASIC chip. You know what a "truth table" is ? Here a example :
'''XOR''' truth table : A B | C 0 0 | 0..."