Extra CPC Plus Hardware Information - Revision history

Phi2x at 07:25, 7 July 2024

2024-07-07T07:25:32Z

Phi2x at 07:24, 7 July 2024

2024-07-07T07:24:20Z

Phi2x at 07:22, 7 July 2024

2024-07-07T07:22:59Z

Phi2x: /* Equation Notes */

2024-07-07T07:21:50Z

‎Equation Notes

Phi2x: /* Equation Notes */

2024-07-07T07:21:27Z

‎Equation Notes

Phi2x: /* Analogue tests */

2024-07-07T07:18:15Z

‎Analogue tests

Phi2x: /* DMA channels and interrupt control */

2024-07-07T07:16:11Z

‎DMA channels and interrupt control

Phi2x: /* Analogue inputs */

2024-07-07T07:14:24Z

‎Analogue inputs

Phi2x: /* Misc registers */

2024-07-07T07:12:53Z

‎Misc registers

Phi2x: /* Misc registers */

2024-07-07T07:12:05Z

‎Misc registers

← Older revision		Revision as of 07:25, 7 July 2024
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	Microsoft sidewinder doesn't work!		Microsoft sidewinder doesn't work!

−	[[Category:Hardware]] [[Category:CPC Internal Components]]	+	[[Category:Hardware]] [[Category:CPC Plus]] [[Category:CPC Internal Components]]

← Older revision		Revision as of 07:24, 7 July 2024
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	Microsoft sidewinder doesn't work!		Microsoft sidewinder doesn't work!

−	[[Category:Hardware]]	+	[[Category:Hardware]] [[Category:CPC Internal Components]]

← Older revision		Revision as of 07:22, 7 July 2024
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	Microsoft sidewinder doesn't work!		Microsoft sidewinder doesn't work!
		+
		+	[[Category:Hardware]]

← Older revision		Revision as of 07:21, 7 July 2024
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	In if statements, the operations enclosed in { } brackets following the if are executed if the condition is true, otherwise the operations enclosed in the brackets following the "else" statement are executed.		In if statements, the operations enclosed in { } brackets following the if are executed if the condition is true, otherwise the operations enclosed in the brackets following the "else" statement are executed.
		+

	In the ASIC documentation it states that following the leading edge of the HSYNC, there is one dead cycle, followed by an instruction fetch for each channel. For each cycle 1 2 byte instruction is fetched.		In the ASIC documentation it states that following the leading edge of the HSYNC, there is one dead cycle, followed by an instruction fetch for each channel. For each cycle 1 2 byte instruction is fetched.

@@ Line 684: / Line 684: @@
 For those who do not know this language, here is a quick list of the operators and their functions:
-| - bitwise/logical OR
+* | - bitwise/logical OR
-& - bitwise/logical AND
+* & - bitwise/logical AND
-<< - shift left by number of bits specified
+* << - shift left by number of bits specified
->> - shift right by number of bits specified
+* >> - shift right by number of bits specified
-== - equals comparison
+* == - equals comparison
-= - assign value to variable
+* = - assign value to variable
-&& - and, as used in "if a==b and c==d ..."
+* && - and, as used in "if a==b and c==d ..."
 Hex numbers are represented with a prefix of 0x. e.g. 0x0abcd is the hex number abcd.

@@ Line 715: / Line 715: @@
 When competition pro attached only.
-= left/right
+* 6808 = left/right
-= up/down
+* 6809 = up/down
-a = Z button
+* 680a = Z button
-b = y button
+* 680b = y button
 pressing X button sets bit 4 of all keys on keyboard matrix, pressing A button sets bit 5 of all keys on keyboard matrix
@@ Line 724: / Line 724: @@
 pressing delete causes all lines to go to 0x080, except line 15. All keys except delete work as expected.
-keyboard normally all keys pressed gives 0-9 0x0ff
+* keyboard normally all keys pressed gives 0-9 0x0ff
-is joystick
+* 10 is joystick
-anything above 10 is zero.
+* anything above 10 is zero.
 === joypad and analogue joypad ===

@@ Line 588: / Line 588: @@
 The official documentation is not clear about the bits in the DCSR register (&6c0f), I found the following are correct:
-Bit 7	Raster Int
+{| class="wikitable"
-Bit 6	DMA Channel 0 Interrupt
+|-
-Bit 5	DMA Channel 1 Interrupt
+| Bit 7 || Raster Int
-Bit 4	DMA Channel 2 Interrupt
+|-
-Bit 3	not used
+| Bit 6 || DMA Channel 0 Interrupt
-Bit 2	DMA Channel 2 Enable
+|-
-Bit 1	DMA Channel 1 Enable
+| Bit 5 || DMA Channel 1 Interrupt
-Bit 0	DMA Channel 0 Enable
+|-
 Each DMA opcode is two bytes, and is always fetched from an even address. The top 4-bits of the opcode fetched in the DMA cycle are used to specify the function to perform by the DMA.
 I found the following rule:
-bit 3	not used
+{| class="wikitable"
-Bit 2	Nop/loop/Int/Stop instruction
+|-
-Bit 1	Repeat N instruction
+| Bit 3 || not used
-Bit 0	Pause instruction.
+|-
 If (opcode & 0x07 == 0) then write data to register else perform function defined by bits.

@@ Line 566: / Line 566: @@
 Without any peripherals attached, the following readings were observed:
-ADC0: 0x03f
+* ADC0: 0x03f
-ADC1: 0x03f
+* ADC1: 0x03f
-ADC2: 0x03f
+* ADC2: 0x03f
-ADC3: 0x03f
+* ADC3: 0x03f
-ADC4: 0x03f
+* ADC4: 0x03f
-ADC5: 0x000
+* ADC5: 0x000
-ADC6: 0x03f
+* ADC6: 0x03f
-ADC7: 0x000
+* ADC7: 0x000
 Writing to these appears to have no effect, with the readings not changing.

@@ Line 559: / Line 559: @@
 However, I found that with this bit set to 0, there is a bug.
-Example showing bug: [http://www.cpctech.org.uk/source/asicbug.html highlighted] | [http://www.cpctech.org.uk/source/asicbug.asm original] ]
+Example showing bug: [ [http://www.cpctech.org.uk/source/asicbug.html highlighted] | [http://www.cpctech.org.uk/source/asicbug.asm original] ]
 A demo program used a single DMA channel to issue an interrupt, a few lines later a raster interrupt would issue an interrupt. The first interrupt executed the correct interrupt handler routine (0,2 or 4), the second executed the interrupt handler for vector of 0 (the raster interrupt is vector 6). This was clearly wrong! My advice is that you should not use the automatic interrupt clear feature.

@@ Line 545: / Line 545: @@
 Reading from 0x06800-0x06807 will read the same values as for invalid data.
-Writing to &6800 will set the interrupt raster line,
+* Writing to &6800 will set the interrupt raster line,
-Writing to &6801 will set the screen split line,
+* Writing to &6801 will set the screen split line,
-Writing to &6802 and &6803 will set the screen split address,
+* Writing to &6802 and &6803 will set the screen split address,
-Writing to &6804 will set the soft scroll,
+* Writing to &6804 will set the soft scroll,
-Writing to &6805 will set the interrupt vector (Arnold V specification 1.4).
+* Writing to &6805 will set the interrupt vector (Arnold V specification 1.4).
-Writing to &6806 has no effect.
+* Writing to &6806 has no effect.
-Writing to &6807 has no effect.
+* Writing to &6807 has no effect.
 For the interrupt raster line, soft scroll and split line please see furthur in this document for details of how the ASIC generates the comparison value to compare against each of these programmed values.
@@ Line 559: / Line 559: @@
 However, I found that with this bit set to 0, there is a bug.
-Example showing bug: [ highlighted | original ]
+Example showing bug: [http://www.cpctech.org.uk/source/asicbug.html highlighted] | [http://www.cpctech.org.uk/source/asicbug.asm original] ]
 A demo program used a single DMA channel to issue an interrupt, a few lines later a raster interrupt would issue an interrupt. The first interrupt executed the correct interrupt handler routine (0,2 or 4), the second executed the interrupt handler for vector of 0 (the raster interrupt is vector 6). This was clearly wrong! My advice is that you should not use the automatic interrupt clear feature.