Default I/O Port Summary - Revision history

Phi2x: /* Memory Mapped I/O */

2025-03-18T15:51:07Z

‎Memory Mapped I/O

Phi2x: /* I/O Port Allocation Rules */

2025-02-16T11:23:52Z

‎I/O Port Allocation Rules

Phi2x: /* Related pages */

2025-01-12T07:54:01Z

‎Related pages

Phi2x: /* I/O Port Allocation Rules */

2025-01-10T16:07:28Z

‎I/O Port Allocation Rules

Phi2x: /* Official I/O Ports */

2025-01-10T16:01:51Z

‎Official I/O Ports

Phi2x: /* Memory Mapped I/O Ports */

2025-01-10T15:59:35Z

‎Memory Mapped I/O Ports

Phi2x: /* Official I/O Ports */

2025-01-10T13:58:23Z

‎Official I/O Ports

Phi2x: /* I/O Port Allocation Rules */

2025-01-10T13:34:06Z

‎I/O Port Allocation Rules

Phi2x: /* Official I/O Ports */

2025-01-10T13:33:06Z

‎Official I/O Ports

Phi2x: /* I/O Port Allocation Rules */

2025-01-10T13:28:19Z

‎I/O Port Allocation Rules

@@ Line 115: / Line 115: @@
 |-
 |}
 See the [[ASIC]] page for details.

@@ Line 18: / Line 18: @@
 | [[CRTC]] || Read/Write || - || 0 || - || - || - || - || r1 || r0 || - || - || - || - || - || - || - || -
 |-
-| [[Upper ROM Bank Number|ROM select]] || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -
+| [[Upper ROM Bank Number|Upper ROM select]] || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -
 |-
 | [[Printer Port]] || Write only || - || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || -

← Older revision		Revision as of 07:54, 12 January 2025
Line 119:		Line 119:

	<br>		<br>
−
−	~~==Related pages==~~
−
−	*[[Arnold V specs]]
−	*[[Arnold V Specs Revised]]

	[[Category:Programming]] [[Category:CPC Internal Components]]		[[Category:Programming]] [[Category:CPC Internal Components]]

@@ Line 12: / Line 12: @@
 ! b15 !! b14 !! b13 !! b12 !! b11 !! b10 !! b9 !! b8 !! b7 !! b6 !! b5 !! b4 !! b3 !! b2 !! b1 !! b0
 |-
-| Gate-Array || Write only || 0 || 1 || - || - || - || - || - || - || - || - || - || - || - || - || - || -
+| [[Gate Array]] || Write only || 0 || 1 || - || - || - || - || - || - || - || - || - || - || - || - || - || -
 |-
-| RAM Configuration || Write only || 0 || - || - || - || - || - || - || - || - || - || - || - || - || - || - || -
+| [[PAL16L8|PAL]] (RAM configuration) || Write only || 0 || * || - || - || - || - || - || - || - || - || - || - || - || - || - || -
 |-
-| CRTC || Read/Write || - || 0 || - || - || - || - || r1 || r0 || - || - || - || - || - || - || - || -
+| [[CRTC]] || Read/Write || - || 0 || - || - || - || - || r1 || r0 || - || - || - || - || - || - || - || -
 |-
-| ROM select || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -
+| [[Upper ROM Bank Number|ROM select]] || Write only || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || - || -
 |-
-| Printer port || Write only || - || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || -
+| [[Printer Port]] || Write only || - || - || - || 0 || - || - || - || - || - || - || - || - || - || - || - || -
 |-
-| 8255 PPI || Read/Write || - || - || - || - || 0 || - || r1 || r0 || - || - || - || - || - || - || - || -
+| [[8255|8255 PPI]] || Read/Write || - || - || - || - || 0 || - || r1 || r0 || - || - || - || - || - || - || - || -
 |-
 | Expansion Peripherals || Read/Write || - || - || - || - || - || 0 || x || x || x || x || x || x || x || x || x || x
@@ Line 32: / Line 32: @@
 *"1" means the bit must be set to "1" for the hardware device to respond.
 *"r1" and "r0" mean a bit used to define a register
 <br>

← Older revision		Revision as of 16:01, 10 January 2025
Line 99:		Line 99:

	* The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.		* The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
−
−	* Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.

	<br>		<br>

@@ Line 104: / Line 104: @@
 <br>
-== Memory Mapped I/O Ports ==
+== Memory Mapped I/O ==
 {| class="wikitable"

@@ Line 96: / Line 96: @@
 |}
-* The three [[765 FDC]] floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.
+* The FDC is considered as an expansion peripheral. The three [[765 FDC]] floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.
 * The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.

← Older revision		Revision as of 13:34, 10 January 2025
Line 4:		Line 4:

	== I/O Port Allocation Rules ==		== I/O Port Allocation Rules ==
		+
		+	Components use partial address decoding. It is therefore possible to send the same value to different components '''simultaneously''' by carefully using custom I/O ports.

	{\| class="wikitable"		{\| class="wikitable"

← Older revision		Revision as of 13:33, 10 January 2025
Line 99:		Line 99:

	* Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.		* Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
−
−	* As components use partial address decoding, it is therefore possible to send the same value to different components '''simultaneously''' by carefully using custom I/O ports.

	<br>		<br>