AMSSIO - Revision history

Zigzac: Just a change of my website url

2016-04-11T20:46:42Z

Just a change of my website url

MacDeath at 18:04, 19 December 2010

2010-12-19T18:04:20Z

Nocash: /* AMSSIO-II (v4) */

2010-05-12T16:22:04Z

‎AMSSIO-II (v4)

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2010-05-12T16:16:07Z

‎AMSSIO-II (v4)

Nocash: /* AMSSIO-II (v4) */

2010-05-12T15:22:46Z

‎AMSSIO-II (v4)

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2010-05-12T15:21:08Z

‎Technical

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2010-05-12T15:20:03Z

‎Technical

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2010-05-12T14:59:29Z

‎Technical

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2010-05-12T14:59:06Z

‎Technical

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Nocash at 14:00, 12 May 2010

2010-05-12T14:00:45Z

@@ Line 72: / Line 72: @@
 == Weblinks ==
-[http://www.citystromer.dk/CPC/ AMSSIO project <s>lives</s> sleeps here!]
+[http://www.zacho.org/CPC/ AMSSIO project <s>lives</s> sleeps here!]
 [[Category:Peripherals]] [[Category:Serial interfaces]] [[Category:DIY]]

← Older revision		Revision as of 18:04, 19 December 2010
Line 74:		Line 74:
	[http://www.citystromer.dk/CPC/ AMSSIO project <s>lives</s> sleeps here!]		[http://www.citystromer.dk/CPC/ AMSSIO project <s>lives</s> sleeps here!]

−	~~[[Category:Hardware]]~~ [[Category:Peripherals]] [[Category:Serial interfaces]] [[Category:DIY]]	+	[[Category:Peripherals]] [[Category:Serial interfaces]] [[Category:DIY]]

@@ Line 35: / Line 35: @@
 AMSSIO-II is a newer version, using a 44pin 16C850CJ instead of the 24pin MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable). Unlike the previous versions, this version also connects to the Z80's interrupt input.
-The "PC" attached to the "16C850CJ" part number (labeled as "16C850CJPC" in schematic) is meant to say that the chip is wired to "PC Mode" (SEL, Pin 34 = GND). In the PC Mode, the chip tries to decode PC ISA bus addresses (COM1-4 = 3F8h,2F8h,3E8h,2E8h), some address lines are swapped, so the AMSSIO maps to FBE0h or FBF0h (selected by S1 input) whilst the chip "thinks" it is mapped to COM3/COM4 ISA bus addresses (3E8h/2E8h).
+The "PC" attached to the "16C850CJ" part number (labeled as "16C850CJPC" in schematic) is meant to say that the chip is wired to "PC Mode" (SEL, Pin 34 = GND). In the PC Mode, the chip tries to decode PC ISA bus addresses (COM1-4 = 3F8h,2F8h,3E8h,2E8h), some address lines are swapped, so the AMSSIO maps to FBE0h or FBF0h (selected by S1 input) whilst the chip "thinks" it is mapped to COM3/COM4 ISA bus addresses (3E8h/2E8h). ''Unclear: the jumper on S1 should change "A8" - but the schematic is wired as if "A4" changes - which would require a jumper on S2, not on S1 (?)''
 * [[Media:XR16C850.pdf]] - 16C850 Datasheet

@@ Line 33: / Line 33: @@
 === AMSSIO-II (v4) ===
-AMSSIO-II is a newer version, using a 16C850 instead of the MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable). Unlike the previous versions, this version also connects to the Z80's interrupt input.
+AMSSIO-II is a newer version, using a 44pin 16C850CJ instead of the 24pin MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable). Unlike the previous versions, this version also connects to the Z80's interrupt input.
 * [[Media:XR16C850.pdf]] - 16C850 Datasheet

@@ Line 33: / Line 33: @@
 === AMSSIO-II (v4) ===
-AMSSIO-II is a newer version, using a 16C850 instead of the MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable).
+AMSSIO-II is a newer version, using a 16C850 instead of the MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable). Unlike the previous versions, this version also connects to the Z80's interrupt input.
 * [[Media:XR16C850.pdf]] - 16C850 Datasheet

@@ Line 21: / Line 21: @@
 == Technical ==
 Connects between Z80 CPU and mainboard. I/O Ports for AMSSIO v1,v2,v3 are:
@@ Line 30: / Line 31: @@
 Observe that the baudrate CLK sources differ for v1,v2,v3. In v3 the CLK is fixed, v1/v2 have different jumper-selectable CLKs. And, the photo shows a different CLK crystal than the schematic. So, don't expect different AMSSIOs to be compatible with each other.
-----
+=== AMSSIO-II (v4) ===
-−
-'''AMSSIO-II (v4)'''
 AMSSIO-II is a newer version, using a 16C850 instead of the MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable).
-* Media:XR16C850.pdf - 16C850 Datasheet
+* [[Media:XR16C850.pdf]] - 16C850 Datasheet
 == Software ==

← Older revision		Revision as of 15:20, 12 May 2010
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	'''AMSSIO-II (v4)'''		'''AMSSIO-II (v4)'''
		+
		+	AMSSIO-II is a newer version, using a 16C850 instead of the MC6850. Aside from the schematic (see below), there is no documentation or source code for AMSSIO-II. I/O base address can be FBE0h or FBF0h (jumper-selectable).
		+	* Media:XR16C850.pdf - 16C850 Datasheet

	== Software ==		== Software ==

@@ Line 23: / Line 23: @@
 Connects between Z80 CPU and mainboard. I/O Ports for AMSSIO v1,v2,v3 are:
-  FBF0h AMSSIO Serial Interface [[MC6850|6850 ACIA chip]] Control/Status Register (R/W)
+  FBF0h AMSSIO Serial Interface [[6850 ACIA chip|MC6850]] Control/Status Register (R/W)
-  FBF1h AMSSIO Serial Interface [[MC6850|6850 ACIA chip]] Data Register (R/W)
+  FBF1h AMSSIO Serial Interface [[6850 ACIA chip|MC6850]] Data Register (R/W)
 For details on the MC6850 chip, see [[6850 ACIA chip]].

← Older revision		Revision as of 14:00, 12 May 2010
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	A new and improved version is the AMSSIO II.		A new and improved version is the AMSSIO II.
		+
		+	== Description ==
		+
		+	AMSSIO is a RS-232 serial interface for the CPC464 (and 664/6128) and it exists in three different versions which all uses the MC6850 asyncronous communication interface adapter (ACIA) from Motorola.
		+
		+	* The first version was based on components from the scrap yard. But the MC14411 is a bit bulky and by now rather old and somewhat hard to find. The second and third version was an attempt to work around the MC14411.
		+	* Version 2 uses a 4060 ripple counter as clock generator. But it can be tricky to make it operate at 2.5 MHz. This was the reason for version 3...
		+	* The version 3 uses a 74LS393 to divide the 4 MHz CPU clock by 26 to obtain the 153 kHz for the serial clock (9600 * 16).
		+
		+	"I couldn't get the software to receive faster than 9600 :-( But it was at least 4 times faster than the tape transfer rate :-)."
		+	All three versions are supposed to use the CPU socket in the CPC. The CPU socket on AMSSIO is meant to be a wire wrap socket. The CPU is removed from the CPC main board. AMSSIO is mounted in the empty socket and the CPU is placed in the 40 pin socket on the AMSSIO.

	== Technical ==		== Technical ==