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Format:DSK disk image file format

2017-10-08T00:08:56Z

Thomasharte: /* Disc Information block */Fixed typo

[[Category:Cpctech.org]]
<div style="border: 1px solid rgb(228, 222, 222); margin: 0px 0px 5px; padding: 0.5em 1em; background-color: rgb(249, 249, 249);">
<center>

'''''This article originally came from Kevin Thackers' archive at [http://www.cpctech.org.uk http://www.cpctech.org.uk].''''' </center></div>

= Disk image file format =

This document describes the standard disk image format. It has the file extension ".DSK".

== Disc Information block ==

The "Disc Information block" is always at offset 0 in the disk image file. If track data exists, then this will immediately follow the Disc Information Block and will start at offset &100 in the disc image file.

The "Disc Information block" has the following structure:

{| border="1"
|-
! offset
! description
! bytes
|-
| 00-21
| "MV - CPCEMU Disk-File\r\nDisk-Info\r\n"
| 34
|-
| 22-2f
| name of creator
| 14
|-
| 30
| number of tracks
| 1
|-
| 31
| number of sides
| 1
|-
| 32-33
| size of a track (little endian; low byte followed by high byte)
| 2
|-
| 34-ff
| not used (0)
| 204
|}

Notes:

*Track 0 (or Track 0 side 0 for double sided disks) immediatly follows the Disk Information Block, and is at offset &100 in the disk image.
*"MV - CPC" must be present, because it is used to identify the file as a disk image. It is sufficient to check this to identify the file as being a disk image.
*"\r" is the C programming language equivalent of ASCII character 13.
*"\n" is the C programming language equivalent of ASCII character 10.
*'''All''' tracks must be the same size.
*"size of track" is used to calculate the location of the data for a chosen track.
*"size of track" includes the &100 byte Track Information Block.
*'''All''' tracks must have a "Track Information Block"
*track lengths are stored in the same order as the tracks in the image e.g. In the case of a double sided disk: Track 0 side 0, Track 0 side 1, Track 1 side 0 etc...
*The track blocks are stored in increasing order 0..number of tracks, with alternating sides interleaved if the disc image describes a double sided disk. e.g. if the disk image represents a double sided disk, the order of tracks is: track 0 side 0, track 0 side 1, track 1 side 0, track 1 side 1.... track (number of tracks-1) side 0, track (number of tracks-1) side 1 The tracks are '''always''' ordered in this way regardless of the disc-format described by the disc image.
*A standard disk image can be used to describe a copy-protected disk, but will often result in a file which is larger than the same disk described by a extended disk image. For a standard disk image to represent a copy-protected disk:
**All track sizes in the standard disk image must be the same. This value therefore would be the size of the largest track, and other tracks would have unused space in them.
**All sector sizes within each track must be the same size, but not necessarily the same size as the sectors for another track. If a track contained different sized sectors, the size of the largest sector should be used. This would result in some wasted space.

== Track Information Block ==

Each Track Block comprises a Track Information Block and sector data. The sector data is always at an offset of &100 bytes from the start of the track block. The data for the next track in the disc image immediatly follows the data for the current track.

The first Track Block is located at offset &100 in the disk image file. The track block starts with the Track Information Block and has this form.

{| border="1"
|-
! offset
! description
! bytes
|-
| 00 - 0b
| "Track-Info\r\n"
| 12
|-
| 0c - 0f
| unused
| 4
|-
| 10
| track number
| 1
|-
| 11
| side number
| 1
|-
| 12 - 13
| unused
| 2
|-
| 14
| sector size
| 1
|-
| 15
| number of sectors
| 1
|-
| 16
| GAP#3 length
| 1
|-
| 17
| filler byte
| 1
|-
| 18 - xx
| Sector Information List
| xx
|}

Notes:

*"number of sectors" is used to identify the number of valid entries in the sector information list.
*"sector size" parameter is used to calculate the location of each sector's data. Therefore, The data allocated for each sector must be the same. If the track contains different sized sectors, then the data allocated must be the size of the biggest sector. The "sector size" parameter is used to calculate the location of the sector data.
*Sector data always follows Track Information Block at offset &100 from the start of the track information block.
*Sector data is stored in the same order as the sectors in the sector info block.

=== Sector info ===

{| border="1"
|-
! offset
! description
! bytes
|-
| 00
| track (equivalent to C parameter in NEC765 commands)
| 1
|-
| 01
| side (equivalent to H parameter in NEC765 commands)
| 1
|-
| 02
| sector ID (equivalent to R parameter in NEC765 commands)
| 1
|-
| 03
| sector size (equivalent to N parameter in NEC765 commands)
| 1
|-
| 04
| FDC status register 1 (equivalent to NEC765 ST1 status register)
| 1
|-
| 05
| FDC status register 2 (equivalent to NEC765 ST2 status register)
| 1
|-
| 06 - 07
| notused (0)
| 2
|}

Notes:

*The following bits are used from NEC765 status register 1:
**b7 EN (End of Cylinder)
**b5 DE (Data Error)
**b2 ND (No Data)
**b0 MA (Missing Address Mark)
*The following bits are used from NEC765 status register 2:
**b5 CM (Control Mark)
**b5 DD (Data Error in Data field)
**b0 MD (Missing address Mark in Data field)
*For 8k Sectors (N="6"), only 1800h bytes is stored.

== General format ==

=== Single sided DSK images ===

*Disc Information Block
*Track 0 data
**Track Information Block
**Sector data
*Track 1 data
**Track Information Block
**Sector data . . . .
*Track (number_of_tracks-1) data
**Track Information Block
**Sector data

=== Double sided DSK images ===

*Disc Information Block
*Track 0 side 0 data
**Track Information Block
**Sector data
*Track 0 side 1 data
**Track Information Block
**Sector data . . . .
*Track (number_of_tracks-1) side 1 data
**Track Information Block
**Sector data

<br>

= Extended DSK image definition =

The extended DSK image is a file designed to describe copy-protected floppy disk software. It's definition was defined by Marco Vieth, Ulrich Doewich and Kevin Thacker.

This format has been widely adopted and is one of the major file formats used (the other major format is the standard disk image with the "MV - CPC" identifier).

The extended disk image format should be used for copy-protected disc software, or in place of a standard disk image if the resulting image is smaller than in the standard disk image form.

== Extended DiSK Format (Rev.5) ==

The disc image has the following format:

{| border="1"
|-
| DISK INFORMATION BLOCK (256 bytes)
|-
| TRACK INFORMATION BLOCK * number of tracks * number of sides
|}

The track blocks are stored in increasing order 0..number of tracks, with alternating sides interleaved if the disc image describes a double sided disk. e.g. if the disk image represents a double sided disk, the order of tracks is: track 0 side 0, track 0 side 1, track 1 side 0, track 1 side 1.... track (number of tracks-1) side 0, track (number of tracks-1) side 1

The tracks are '''always''' ordered in this way regardless of the disc-format described by the disc image.

The location of the track information block is found by using the track size table.

== DISK INFORMATION BLOCK ==

The "DISK INFORMATION BLOCK" is always located at offset 0 in the disk image file, and has the following structure:

{| border="1"
|-
! offset
! description
! bytes
|-
| 00 - 21
| "EXTENDED CPC DSK File\r\nDisk-Info\r\n"
| 34
|-
| 22 - 2f
| name of creator (utility/emulator)
| 14
|-
| 30
| number of tracks
| 1
|-
| 31
| number of sides
| 1
|-
| 32 - 33
| unused
| 2
|-
| 34 - xx
| track size table
| number of tracks*number of sides
|}

NOTES:

*An extended DSK image is identified by the "EXTENDED" tag. The track size at offset 32h and 33h, used by the STANDARD disk image is ignored for extended format DSK images.
*If track data exists, then it starts at offset 100h.
*The "EXTENDED" tag is present to prevent existing emulators which support the standard DSK image from interpreting the data wrong and possibly crashing.
*"\r" is the C programming language equivalent of ASCII character 13.
*"\n" is the C programming language equivalent of ASCII character 10.

== TRACK OFFSET TABLE ==

{| border="1"
|-
! offset
! description
! bytes
|-
| 01
| high byte of track 0 length (equivalent to track length/256)
| 1
|-
| ...
| ...
| ...
|}

NOTES:

*Depending on the information in the disk information block, the table contains
**track lengths for a single sided floppy disc
**track lengths for a double sided floppy disc
*track lengths are stored in the same order as the tracks in the image e.g. In the case of a double sided disk: Track 0 side 0, Track 0 side 1, Track 1 side 0 etc...
*A size of "0" indicates an unformatted track. In this case there is no data, and no track information block for this track in the image file!
*Actual length of track data = (high byte of track length) * 256
*Track length includes the size of the TRACK INFORMATION BLOCK (256 bytes)
*The location of a Track Information Block for a chosen track is found by summing the sizes of all tracks up to the chosen track plus the size of the Disc Information Block (&100 bytes). The first track is at offset &100 in the disc image.

== TRACK INFORMATION BLOCK ==

{| border="1"
|-
! offset
! description
! bytes
|-
| 00 - 0b
| "Track-Info\r\n"
| 12
|-
| 0c - 0f
| unused
| 4
|-
| 10
| track number
| 1
|-
| 11
| side number
| 1
|-
| 12 - 13
| unused
| 2
|-
| 14
| sector size
| 1
|-
| 15
| number of sectors
| 1
|-
| 16
| GAP#3 length
| 1
|-
| 17
| filler byte
| 1
|-
| 18 - xx
| Sector Information List
| xx
|}

NOTES:

*Identical to the original DSK format definition.

== SECTOR INFORMATION LIST ==

{| border="1"
|-
! offset
! description
! bytes
|-
| 00
| track (equivalent to C parameter in NEC765 commands)
| 1
|-
| 01
| side (equivalent to H parameter in NEC765 commands)
| 1
|-
| 02
| sector ID (equivalent to R parameter in NEC765 commands)
| 1
|-
| 03
| sector size (equivalent to N parameter in NEC765 commands)
| 1
|-
| 04
| FDC status register 1 (equivalent to NEC765 ST1 status register)
| 1
|-
| 05
| FDC status register 2 (equivalent to NEC765 ST2 status register)
| 1
|-
| 06 - 07
| actual data length in bytes
| 2
|}

NOTES:

*Identical to the original definition except for the addition of the sector data length. This value is in bytes and stored in little endian notation. (low byte followed by high byte)
*The location of each sectors data is found by adding the size of the previous sectors, plus the size of the 256 byte header.
*For 8k Sectors (N="6"), only 1800h bytes is stored. Please see extensions below!!!

== Extensions to the above specification ==

1. This extension was proposed by John Elliott. Extension to TRACK INFORMATION BLOCK:

{| border="1"
|-
! offset
! description
! bytes
|-
| 12
| Data rate. (See note 1 and note 3)
| 1
|-
| 13
| Recording mode. (See note 2 and note 3)
| 1
|}

:Notes:

:1. Data rate defines the rate at which data was written to the track. This value applies to the entire track.

{| border="1"
|-
! Date rate
! description
|-
| 0
| Unknown.
|-
| 1
| Single or double density
|-
| 2
| High Density
|-
| 3
| Extended density
|}

Existing files should have zeroes in these bytes; hence the use of 0 for unknown.

:2. Recording mode is used to define how the data was written. It defines the encoding used to write the data to the disc and the structure of the data on the disc including the layout of the sectors. This value applies to the entire track.

{| border="1"
|-
! Date rate
! description
|-
| 0
| Unknown.
|-
| 1
| FM
|-
| 2
| MFM
|}

Existing files should have zeroes in these bytes; hence the use of 0 for unknown.

:3. How to determine the actual rate. The NEC765 floppy disc controller is supplied with a single clock. When reading from and writing to a disc using the NEC765 you can choose FM or MFM recording modes. Use of these modes and the clock into the NEC765 define the final rate at which the data is written to the disc.
:When FM recording mode is used, data is read from or written to at a rate which is double that of when MFM is used. The time for each bit will be twice the time for MFM.
:Examples:

{| border="1"
|-
! NEC765 Clock
! FM/MFM
! Actual rate
|-
| 4Mhz
| FM
| 4us per bit
|-
| 4Mhz
| MFM
| 2us per bit
|}

2. This extension was proposed by Simon Owen.

:1. It has been found that many protections using 8K Sectors (N="6") do store more than &1800 bytes of useable data. It was thought that &1800 was the maximum useable limit, but this has proved wrong. So you should support 8K of data to ensure this data is read correctly. The size of the sector will be reported in the SECTOR INFORMATION LIST as described above.
:For sector size N="7" the full 16K will be stored. It is assumed that sector sizes are defined as 3 bits only, so that a sector size of N="8" is equivalent to N="0".
:2. Storing Multiple Versions of Weak/Random Sectors.
:Some copy protections have what is described as 'weak/random' data. Each time the sector is read one or more bytes will change, the value may be random between consecutive reads of the same sector.
:To support these formats the following extension has been proposed.
:Where a sector has weak/random data, there are multiple copies stored. The actual sector size field in the SECTOR INFORMATION LIST describes the size of all the copies. To determine if a sector has multiple copies then compare the actual sector size field to the size defined by the N parameter. For multiple copies the actual sector size field will have a value which is a multiple of the size defined by the N parameter. The emulator should then choose which copy of the sector it should return on each read.

CRTC

2017-08-10T16:24:05Z

Thomasharte: Minor adjustments; some incorrect apostrophes, and minor other things.

* ''This is an article about the "Cathode Ray Tube Controller" hardware unit of the Amstrad CPC. For the cpc scene member see [[ChaRleyTroniC]]''

The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

== Timings and relating with Z80 instructions count ==

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O port address''||''Function''||''Read/Write''
|-
|&BCxx||Select 6845 register||Write only
|-
|&BDxx||Write 6845 register data||Write only
|-
|&BExx||(note 1)||Read only
|-
|&BFxx||(note 1)||Read only
|-
|}

'''NOTE'''

1. The function of these I/O ports is dependant on the CRTC type

2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.

==Addressing==

The following table defines the generated memory address from the CRTC and Gate-Array signals.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||RA2
|-
|A12||6845||RA1
|-
|A11||6845||RA0
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.

== DISPTMG ==

DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

== HSYNC and VSYNC ==

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

== The 6845 Registers ==

The Internal registers of the 6845 are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||32
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (Low)||00000000||||Read Only
|-
|}

registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

Details about Reg. 12 and Reg. 13 specifically:

.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'

So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12).

== CRTC Differences ==

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 1

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|}

Type 2

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 3 and 4

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1||2||3||4
|-
|0||Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}

'''Notes'''

1. On type 0 and 1, if a Write Only register is read from, "0" is returned.

2. See the document "Extra CPC Plus Hardware Information" for more details.

3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.

== Horizontal and Vertical Sync (R3) ==

UM6845:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

UM6845R:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

MC6845:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Pre-ASIC/ASIC:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

== UM6845R and R31 ==

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3.

== UM6845R and R12/R13 ==

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

== UM6845R status register ==

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

== Datasheets ==

* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umc.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]]

* [[VHDL implementation of the 6845]]

== Clones ==
* [CM607P a Bulgarian clone made in Pravetz factory]
* [EF6845P by Thomson Semiconductors]

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects - by [[Elmar Krieger]] ] (DSK for Emulators)

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTCs on grimware]

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

8255

2017-08-07T23:40:10Z

Thomasharte: There's no apostrophe for ownership on 'its' (or the other personal pronouns — hers, yours, etc — other than one's)

== 8255 Part numbers used in the CPC during its lifetime ==

* NEC D8255AC-2
* NEC D8255AC-5
* Toshiba TMP8255AP-5

All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.

== The 8255 in the CPC ==

The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.

The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O address''||''A9''||''A8''||''Description''||''Read/Write status''||''Used Direction''||''Used for''
|-
|&F4xx||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick)
|-
|&F5xx||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
|-
|&F6xx||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
|-
|&F7xx||1||1||Control||Write Only||Out||Control
|-
|}

In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the "Extra CPC+ documentation" for more information.

* Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used.

== Port Usage ==

* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.

== PPI Port A ==

Operating system settings:
* I/O Mode 0,
* For writing data to PSG all bits must be set to output,
* for reading data from PSG all bits must be set to input (thereafter, output direction should be restored, for compatibility with the BIOS).

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)
|-
|}

== PPI Port B ==

Operating system settings:

* I/O Mode 0,
* Input

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage in CPC''||''Usage in KC Compact''
|-
|7||CAS.IN||Cassette data input||Same as on CPC
|-
|6||PRN.BUSY||Parallel/Printer port ready signal, "1" = not ready, "0" = Ready||Same as on CPC
|-
|5||/EXP||Expansion Port /EXP pin||Same as on CPC
|-
|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
|-
|2||LK2||Purpose unknown (set to "0")
|-
|1||LK1||Expansion Port /TEST pin
|-
|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
|-
|}

* LK1-4 are links on the mainboard ("0" bits are wired to GND). On CPC464,CPC664,CPC6128 and GX4000 they are labeled LK1-LK4, on the CPC464+ and CPC6128+ they are labeled LK101-LK103 (and LK104, presumably?).

* Bit5 (/EXP) can be used by a expansion device to report its presence. "1" = device connected, "0" = device not connected. This is not always used by all expansion devices. ''is it used by any expansions?'' [in the DDI-1 disc interface, /EXP connects to the ROM bank selection, bank 0 or bank 7]

* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.

* For more info on LK1-LK4 (and further LKs) see [[LK Links]]

== PPI Port C ==

Operating system settings:

* upper: I/O Mode 0, lower: I/O mode 0,
* upper: output, lower: output

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7||PSG BDIR||PSG function selection
|-
|6||PSG BC1||
|-
|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
|-
|4||Cassette Motor Control||set bit to "1" for motor on, or "0" for motor off
|-
|3||rowspan=4|Keyboard line||rowspan=4|Select keyboard line to be scanned (0-15)
|-
|2
|-
|1
|-
|0
|-
|}

PSG function selection:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit 7''||''Bit 6''||''Function''
|-
|0||0||Inactive
|-
|0||1||Read from selected PSG register
|-
|1||0||Write to selected PSG register
|-
|1||1||Select PSG register
|-
|}

== PPI Control ==

This register has two different functions depending on bit7 of the data written to this register.

=== PPI Control with Bit7=1 ===
If Bit 7 is "1" then the other bits will initialize Port A-B as Input or Output:

Bit 0 IO-Cl Direction for Port C, lower bits (always 0=Output in CPC)
Bit 1 IO-B Direction for Port B (always 1=Input in CPC)
Bit 2 MS0 Mode for Port B and Port Cl (always zero in CPC)
Bit 3 IO-Ch Direction for Port C, upper bits (always 0=Output in CPC)
Bit 4 IO-A Direction for Port A (0=Output, 1=Input)
Bit 5,6 MS0,MS1 Mode for Port A and Port Ch (always zero in CPC)
Bit 7 SF Must be "1" to setup the above bits

* CAUTION: Writing to PIO Control Register (with Bit7 set), automatically resets PIO Ports A,B,C to 00h each!
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.

=== PPI Control with Bit7=0 ===
Otherwise, if Bit 7 is "0" then the register is used to set or clear a single bit in Port C:

Bit 0 B New value for the specified bit (0=Clear, 1=Set)
Bit 1-3 N0,N1,N2 Specifies the number of a bit (0-7) in Port C
Bit 4-6 - Not Used
Bit 7 SF Must be "0" in this case

== Programming Examples ==

1. Using the control byte

* Setting bit 7 of port C to 1,

<pre>
LD B,&F7 ;8255 Control port
LD A,%00001111 ;Bit Set/reset function
OUT (C),A ;Send it to 8255
RET
</pre>

* Set port A to input, operating in mode 0, port B to output, operating in mode 0 and port C to input, operating in mode 0.

<pre>
LD B,&F7 ;8255 Control port
LD A,%10011001 ;Configuration function
OUT (C),A ;Send it to 8255
RET
</pre>

2. Using port A/B/C,

In this example, port A is set to output, port B is set to input, and port C is set to output, and they are all operating in mode 0.

We will only be using port A for these examples.
* Reading from port A,

<pre>
;Set port A to input

LD B,&F7 ;8255 Control port
LD A,%10010010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;Port A port address
IN E,(C) ;Get byte from port

;Register E holds value from port

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255
RET
</pre>

* Writing to port A,

<pre>
;Set port A to output

;(Note the next few lines are not necessary
;as port A is already acting as output, however
;it is given here just to make the example
;more understandable)

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;port A port address

;Register E holds value to put into port

LD E,&FF ;Data to put into port
OUT (C),A ;Send to port A

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A
RET
</pre>

= Diagrams =

[[Image:8255 ppi 1.jpg]]

[[Image:8255 ppi 2.jpg]]

= Resources =

* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL implementation of the 8255 PIO]]

= Links =

[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]

[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]

CPC old generation

2017-08-04T20:01:59Z

Thomasharte: /* The 3" floppy disk drives */ the +3 wasn't produced by Sinclair. It was launched in 1987, a year after Amstrad's acquisition of the Spectrum

[[Category:Hardware|*]][[Category:CPC Internal Components| ]][[Category:CPC History|*]][[Category:Amstrad Products| ]]

[[Image:464.png|thumb|CPC 464 with Colour monitor]]
[[Image:Schneider 664 en.jpg|thumb|German CPC 664]]

''The following text was copied in part from the [http://en.wikipedia.org/wiki/Amstrad_CPC English Wikipedia article].''

==Hardware description==
All CPC models were based on a Zilog Z80 processor clocked at 4 MHz. Because a common pool of RAM is shared with the video circuits, the Z80 may only make a memory access once every four cycles, which has the effect of rounding all instruction cycle lengths up to the next multiple of four. For details, see [http://www.grimware.org/doku.php/documentations/devices/z80 a nearly complete list of instructions with timings (number of cycles) for each.]

The system came with 64 KB or 128 KB of RAM depending on the model (capable of being expanded to more). The machines also featured a standard 9-pin Atari-style joystick socket which was able to take two joysticks via a splitter.

The machines' dimensions are:
*'''CPC464''' : 17 x 57.5 x 7.5
*'''CPC6128''' : 17.5 x 51.1 x 5

===Video (graphics): modes, outputs===
Underlying the CPC's video output was the [[CRTC|Motorola 6845]] address generator. This chip was connected to a pixel generator that supported 4 bpp, 2 bpp and 1 bpp output (bits per pixel). The address generator was clocked at a constant rate so the 4 bpp display generated half as many pixels as the 2 bpp and a quarter as many as the 1 bpp.

The ROM featured three built-in display resolutions but many others could be achieved by reprogramming the 6845.

The standard [[video modes]] were:
*'''Mode 0''': '''160×200''' pixels with 16 colours (4 bpp)
*'''Mode 1''': '''320×200''' pixels with 4 colours (2 bpp)
*'''Mode 2''': '''640×200''' pixels with 2 colours (1 bpp)
*'''Mode 3''': '''160×200''' pixels with 4 colours (2 bpp) (this is not an official mode, but rather a side-effect of the hardware)

A colour palette of 27 colours was supported, derived from RGB colour space with each component assigned as either off, half on or on. The later '''Plus''' models extended this to 4096 colours and added support for hardware sprites.

This hardware compares well with the other 8-bit computers. In particular the CPC lacks the colour clash of the ZX Spectrum, and clever programming of the 6845 could produce overscan, different resolutions (although with the same pixel density) and smooth pixel scrolling.

The machine lacked either a RF TV or composite video output and instead shipped with a proprietary 5-pin DIN connector intended for use solely with the supplied Amstrad monitor. An external adapter for RF TV was available to be bought separately.

The five-pin DIN connector is capable of driving a television with a correctly wired SCART lead.

===Audio (sound)===
The CPC used the General Instrument AY-3-8912 sound chip, providing three channels, each configurable to generate square waves, white noise or both. A small array of hardware volume envelopes are available.

Output was provided in mono by a small (4 cm) built-in loudspeaker with volume control, driven by an unusually powerful amplifier. Stereo output was provided through a 3.5mm headphone jack, not present on some early CPC464 models. In those models, what looked like a standard 3.5" headphone jack was actually used for connecting an external tape recorder, although later models used a five-pin DIN connector for the same purpose.

Playback of digital sound samples at a resolution of a little better than 5-bit, as heard on the title screen of the game ''RoboCop'', was possible through clever programming of the sound chip. This trick was very processor intensive and hard to combine with any other processing.

===The 3" floppy disk drives===
Amstrad's idiosyncratic choice of Hitachi's 3" floppy disk drive, when the rest of the PC industry was moving to Sony's 3.5" format, is often claimed to be due to Amstrad bulk-buying a large consignment of 3" drive units in Asia. The cheapest drive (built-in in later models) was a single-sided 40-track unit that required the user to physically remove and flip the disk to access both sides. Each side had its own independent write-protect switch. The sides were termed "A" and "B", with each one holding 180KB (178KB in AMSDOS format) for a total of 360KB per disc.

The disk drive interface was a NEC 765 FDC, used for the same purpose in the IBM PC/XT, PC/AT and PS/2 machines. Many of its features were unused in order to cut costs, namely DMA transfers and support for single density disks. Disks were formatted as double density using Modified Frequency Modulation.

Disks were shipped in a paper sleeve or a hard plastic case resembling a compact disc "jewel" case. The casing is thicker and more rigid than that of 3.5" diskettes and the sliding metal cover to protect the media surface is internal to the casing and latched, unlike the simple external sliding cover of Sony's version (some reviews at the time reported driving over them with no problems). Because of this they were significantly more expensive than both the 5.25" and 3.5" alternatives. This, combined with their low nominal capacities and their essentially proprietary nature, lead to the format being discontinued when the CPC itself was discontinued.

Apart from Amstrad's other 3" machines, the PCW and the ZX Spectrum +3 (produced by Amstrad after their acquisition of the Spectrum from Sinclair), the only other computer systems to use them were the Sega SF-7000 and mostly obscure and exotic CP/M systems such as the Tatung Einstein and Osborne machines. It should be noted that some of these machines used drives with different pinouts and care should be taken when replacing drives.

The data formatting of 3" disks was very similar to that of 5¼" disks, and the Amstrad CPC machines were able to use 5¼" drives through their "external drive" port - either one specially designed for use by the CPC or an adapted IBM-PC drive.

A more popular alternative was to attach an adapted IBM-PC 3½" drive for operation in either single-sided 180 KB or double-sided 360 KB mode, although with the later availability of the PARADOS Disc Operating System, 720k per disc became available. (It was possible to patch CP/M Plus so that it recognised 80 track double sided disk formats, too.)

===Serial port adaptor===
An official RS-232-C D25 serial port adaptor was produced that attached to the expansion connector at the rear of the machine, and had a through-connector for the CPC464 disk drive or other peripherals. The adaptor came with a "''Book of Spells''" for facilitating data transfer between other systems using a proprietary protocol in the device's own ROM, as well as terminal software to connect to British Telecom's Prestel service. A separate version of the ROM was created for the U.S. market due to the use of the commands "SUCK" and "BLOW", which were considered unacceptable there.

===Similarities to the BBC Micro===
The CPC has been termed an "improved Z80 implementation of the (earlier) BBC Micro" due to similarities in firmware and hardware. Both used the Motorola 6845 video address generator and the two have very similar sound output chips - the General Instrument AY-3-8912 in the CPC provided three tone channels each optionally with added noise and the Texas Instruments SN76489 in the BBC offered three tone channels and one exclusive noise channel.

The BBC Micro used an Intel 8271 floppy disc controller. The CPC used the Intel 8272, which is similar to the 8271 but contains the addition of a double density (MFM) mode.

The "two cursor" BASIC editing system seen on the Amstrad CPC (whereby holding Shift and using the cursor keys moves a shadow text cursor allowing text to be copied from another area of the screen to the normal cursor) was a lift from BBC BASIC, albeit substantially improved by allowing free movement of the normal cursor.

Both systems provided similar systems of full hardware abstraction through Operating System calls. This saves programs which don't require time critical hardware access from having to touch the underlying machine and provides a level of machine portability for those programs.

As the CPC had its own dialect of [[BASIC]], namely [[Locomotive BASIC]], so the BBC Micro has its own version named [[BBC BASIC]]. BBC BASIC evolved with subsequent models of BBC computers and with Acorn's next system, the Archimedes. Both had their own sets of advantages: Locomotive BASIC was faster in many contexts, had native support for text windows, had more comprehensive commands for manipulating sound, ''etc.''; BBC BASIC had support for procedures (rather than just arithmetic functions), an inline assembler, and others. Of note is the fact that among the numerous [http://www.bbcbasic.co.uk/bbcbasic.html ports of BBC Basic] produced by the company [http://www.rtrussell.co.uk/ R.T. Russell] is a version especially adapted for the Amstrad CPC, including support for its specific graphics and sound capabilities; there is also a generic version for [[CP/M]].

==Software==
===Built-in BASIC and operating system===
Like most home computers at the time, the CPC had its OS and a BASIC interpreter built in as ROM. It used Locomotive BASIC - a variant specifically written for the CPC hardware which as a result was faster, more comfortable and more powerful than the generic but common Microsoft BASIC used by the Commodore 64 and MSX amongst others. It was particularly notable for providing easy access to the machine's video and audio resources in contrast to the arcane POKE commands required on some Microsoft implementations (the MSX implementation of Microsoft Basic being an exception, which even allowed for hardware sprite manipulation and collision detection).

===Other languages===
Although it was possible to obtain compilers for Locomotive BASIC, BCPL, C, Forth, and Turbo Pascal the majority of the CPC's software was written in native Z80 assembly language.

An interpreter for the educational language LOGO was also supplied with the 664 and 6128 (and available for the 464 with purchase of an external disc drive).

==What was in the box?==

=== CPC464 ===

* The computer itself, including built-in [[Datacorder]]
* [[Demostration tape or disc|Demonstration tape]] in local language (UK, Germany, France, Spain)
* [[User Manual]]
* Either an [[Amstrad GT64/GT65 Green Monitor|Amstrad GT64 (Later: GT65) green monitor]] or an [[Amstrad CTM640/CTM644 Color Monitor|Amstrad CTM640 (Later: CTM644) Colour Monitor]]
* Optional: [[Amstrad MP1/MP2 modulator|Amstrad MP-1 (Later: MP-2) TV modulator and power supply]]
* A Gamepack consisting of 12 Amsoft Titles on Tape.

<gallery>
Image:CPC464_pcb_r1.jpg|CPC464 PCB revision 0 (original)
Image:CPC464_pcb_r3.jpg|CPC464 PCB revision 3 (costdown)
Image:CPC464_new_amstrad_logo.jpg|CPC464 (new Amstrad logo - photo from costdown model)
</gallery>

=== CPC472 ===
The CPC 472 was a spanish version of the CPC 464 with additional (nonfunctional) 8 KB RAM. The reason for this was that Amstrad wanted to circumvent a Spanish law that levied an extra tax for machines with 64KB or less of memory; thus, they upped the spec to 72KB by including an additional 8KB though this extra memory was not functional.

* Amstrad CPC [[472]]
<gallery>
Image:CPC_472_es.jpg|The CPC472
</gallery>
=== CPC664 ===

* The computer itself, including built-in 3" disk drive
* [[System Disk]]: CP/M 2.2 disk with demo in local language (UK, Germany, France, Spain)
* [[User Manual]]
* Either an [[Amstrad GT64/GT65 Green Monitor|Amstrad GT65 green monitor]] or an [[Amstrad CTM640/CTM644 Color Monitor|Amstrad CTM644 Colour Monitor]]
* Optional: [[Amstrad MP1/MP2 modulator|Amstrad MP-2 TV modulator and power supply]]

<gallery>
Image:664.jpg|The 664 in high-res
Image:CPC664_Top.jpg|CPC 664 Top
Image:CPC664_PCB_Top.jpg|CPC 664 Motherboard Top
Image:CPC664_PCB_Bottom.jpg|CPC 664 Motherboard Bottom
</gallery>

==== Links ====

* http://www.sellmyretro.com/ - Buy new keyboard membranes for CPC664 from RWAP software
* http://www.rwapsoftware.co.uk/ - RWAP Software, makers of membranes for Sinclair, Enterprise and CPC664

=== CPC6128 ===

* The computer itself, including built-in 3" disk drive
* [[System Disk]]s with CP/M Plus, CP/M 2.2 and a demo in local language (UK, Germany, France, Spain)
* [[User Manual]]
* Either an [[Amstrad GT64/GT65 Green Monitor|Amstrad GT65 green monitor]] or an [[Amstrad CTM640/CTM644 Color Monitor|Amstrad CTM644 Colour Monitor]]
* Optional: [[Amstrad MP1/MP2 modulator|Amstrad MP-2 TV modulator and power supply]]
* Later models came with the [[Amstrad PP8 Promotional Pack]]

<gallery>
Image:CPC6128_Top.jpg|CPC 6128 Top
Image:CPC6128_PCB_Top_(Z70290_MC0020B).jpg|CPC 6128 Motherboard Top
Image:CPC6128_PCB_Bottom_(Z70290_MC0020B).jpg|CPC 6128 Motherboard Bottom
</gallery>

=== DDI-1 ===

* Controller DDI-1
* 3" disk drive FD-1
* [[System Disk]]: CP/M 2.2 disk with demo
* [[User Manual]]

==Others==

* [[Keyboard Versions]]
* [[Mainboard Versions]]
* [[CPC6128_Keyboard_Disassembled]]
*[[CPC464 & CPC664_logos | CPC Case logos]]

==Clones==

See [[Clones]] for a list of classic and modern clones.

Other Computers:Other Amstrad products

2017-08-02T20:11:21Z

Thomasharte: Minor copy edits: a spelling correction, extra space removed, etc.

Thanks to the success of the CPC464 Amstrad was able to be a major part of the computer market in the '80s.

*[[PCW]]: a revolutionary and fully equipped 8-bit word processor.
*[[Amstrad PC]]: the first "cheap" IBM PC compatible range.
*[[NC Series]]: a range of portable computers.
*[[ZX Spectrum]]: Amstrad bought Sinclair's computer brand and produced its own ZX Spectrum range from 1986.

[[Category:Non CPC Computers]][[Category:Amstrad Products]][[Category:CPC History]]

CRTC

2017-08-01T15:37:10Z

Thomasharte: /* Addressing */ the top two bits of MA are retained, not the almost-top-two.

* ''This is an article about the "Cathode Ray Tube Controller" hardware unit of the Amstrad CPC. For the cpc scene member see [[ChaRleyTroniC]]''

The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with it's separate CRTC and Gate-Array.
The Plus has both integrated into the same IC, but could be considered to have 2 functional blocks, one for CRTC and one for Gate-Array. In this document Gate-Array is used, but this also applies to the ASIC.

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

== Timings and relating with Z80 instructions count ==

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O port address''||''Function''||''Read/Write''
|-
|&BCxx||Select 6845 register||Write only
|-
|&BDxx||Write 6845 register data||Write only
|-
|&BExx||(note 1)||Read only
|-
|&BFxx||(note 1)||Read only
|-
|}

'''NOTE'''

1. The function of these I/O ports is dependant on the CRTC type

2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.

==Addressing==

The following table defines the generated memory address from the CRTC and Gate-Array signals.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||RA2
|-
|A12||6845||RA1
|-
|A11||6845||RA0
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.

== DISPTMG ==

DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

== HSYNC and VSYNC ==

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

== The 6845 Registers ==

The Internal registers of the 6845 are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||32
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (Low)||00000000||||Read Only
|-
|}

registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

Details about Reg. 12 and Reg. 13 specifically:

.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'

So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12).

== CRTC Differences ==

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 1

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|}

Type 2

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 3 and 4

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1||2||3||4
|-
|0||Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}

'''Notes'''

1. On type 0 and 1, if a Write Only register is read from, "0" is returned.

2. See the document "Extra CPC Plus Hardware Information" for more details.

3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.

== UM6845R and R31 ==

R31 is described in the UM6845R documentation as "Dummy Register".

It's use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3.

== UM6845R and R12/R13 ==

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

== UM6845R status register ==

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

== Datasheets ==

* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umc.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]]

* [[VHDL implementation of the 6845]]

== Clones ==
* [CM607P a Bulgarian clone made in Pravetz factory]
* [EF6845P by Thomson Semiconductors]

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects - by [[Elmar Krieger]] ] (DSK for Emulators)

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTCs on grimware]

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

765 FDC

2017-07-28T13:38:13Z

Thomasharte: /* Notes */ Minor copy edits. Hopefully improvements.

µPD765 - Floppy Disc Controller (used in [[DDI-1]] and CPC 664/6128).

* Port FA7Eh - Floppy Motor On/Off Flipflop
* Port FB7Eh - FDC 765 Main Status Register (read only)
* Port FB7Fh - FDC 765 Data Register (read/write)

== IC Models used in CPC ==

More than one manufacturer made 765 compatible ICs. These are the ones known to be used in the CPC by looking at pictures of CPC mainboards.
All should operate almost identically.

* [[Zilog]] Z0765A08PSC
* NEC D765AC-2
* NEC D765AC
* UMC UM8272A

The following data seperators are used:

* FDC9216

== Accessing the FDC 765 ==
The Data Register (Port FB7Fh) is used to write Commands and Parameters, to read/write data bytes, and to receive result bytes. These three operations are called Command-, Execution-, and Result-Phase. The Main Status Register signalizes when the FDC is ready to send/receive the next byte through the Data Register.

Command Phase
A command consists of a command byte (eventually including the MF, MK, SK bits), and up to eight parameter bytes.

Execution Phase
During this phase, the actual data is transferred (if any). Usually that are the data bytes for the read/written sector(s), except for the Format Track Command, in that case four bytes for each sector are transferred.

Result Phase
Returns up to seven result bytes (depending on the command) that are containing status information. The Recalibrate and Seek Track commands do not return result bytes directly, instead the program must wait until the Main Status Register signalizes that the command has been completed, and then it must (!) send a Sense Interrupt State command to 'terminate' the Seek/Recalibrate command.

== FDC Command Table ==

Command Parameters Exm Result Description
02+MF+SK HU TR HD ?? SZ NM GP SL <R> S0 S1 S2 TR HD NM SZ read track
03 XX YY - specify spd/dma
04 HU - S3 sense drive state
05+MT+MF HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ write sector(s)
06+MT+MF+SK HU TR HD SC SZ LS GP SL <R> S0 S1 S2 TR HD LS SZ read sector(s)
07 HU - recalib.seek TP=0
08 - - S0 TP sense int.state
09+MT+MF HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ wr deleted sec(s)
0A+MF HU - S0 S1 S2 TR HD LS SZ read ID
0C+MT+MF+SK HU TR HD SC SZ LS GP SL <R> S0 S1 S2 TR HD LS SZ rd deleted sec(s)
0D+MF HU SZ NM GP FB <W> S0 S1 S2 TR HD LS SZ format track
0F HU TP - seek track n
11+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan equal
19+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan low or equal
1D+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan high or eq.

Parameter bits that can be specified in some Command Bytes are:

MT Bit7 Multi Track (continue multi-sector-function on other head)
MF Bit6 MFM-Mode-Bit (Default 1=Double Density)
SK Bit5 Skip-Bit (set if secs with deleted DAM shall be skipped)

Parameter/Result bytes are:

HU b0,1=Unit/Drive Number, b2=Physical Head Number, other bits zero
TP Physical Track Number
TR Track-ID (usually same value as TP)
HD Head-ID
SC First Sector-ID (sector you want to read)
SZ Sector Size (80h shl n) (default=02h for 200h bytes)
LS Last Sector-ID (should be same as SC when reading a single sector)
GP Gap (default=2Ah except command 0D: default=52h)
SL Sectorlen if SZ=0 (default=FFh)
Sn Status Register 0..3
FB Fillbyte (for the sector data areas) (default=E5h)
NM Number of Sectors (default=09h)
XX b0..3=headunload n*32ms (8" only), b4..7=steprate (16-n)*2ms
YY b0=DMA_disable, b1-7=headload n*4ms (8" only)

Format Track: output TR,HD,SC,SZ for each sector during execution phase
Read Track: reads NM sectors (starting with first sec past index hole)
Read ID: read ID bytes for current sec, repeated/undelayed read lists all IDs
Recalib: walks up to 77 tracks, 80tr-drives may need second recalib if failed
Seek/Recalib: All read/write commands will be disabled until succesful senseint
Senseint: Set's IC if unsuccesful (no int has occured) (until IC=0)

== FDC Status Registers ==

The Main Status register can be always read through Port FB7E. The other four Status Registers cannot be read directly, instead they are returned through the data register as result bytes in response to specific commands.

Main Status Register (Port FB7E)

b0..3 DB FDD0..3 Busy (seek/recalib active, until succesful sense intstat)
b4 CB FDC Busy (still in command-, execution- or result-phase)
b5 EXM Execution Mode (still in execution-phase, non_DMA_only)
b6 DIO Data Input/Output (0=CPU->FDC, 1=FDC->CPU) (see b7)
b7 RQM Request For Master (1=ready for next byte) (see b6 for direction)

Status Register 0

b0,1 US Unit Select (driveno during interrupt)
b2 HD Head Address (head during interrupt)
b3 NR Not Ready (drive not ready or non-existing 2nd head selected)
b4 EC Equipment Check (drive failure or recalibrate failed (retry))
b5 SE Seek End (Set if seek-command completed)
b6,7 IC Interrupt Code (0=OK, 1=aborted:readfail/OK if EN, 2=unknown cmd
or senseint with no int occured, 3=aborted:disc removed etc.)

Status Register 1

b0 MA Missing Address Mark (Sector_ID or DAM not found)
b1 NW Not Writeable (tried to write/format disc with wprot_tab=on)
b2 ND No Data (Sector_ID not found, CRC fail in ID_field)
b3,6 0 Not used
b4 OR Over Run (CPU too slow in execution-phase (ca. 26us/Byte))
b5 DE Data Error (CRC-fail in ID- or Data-Field)
b7 EN End of Track (set past most read/write commands) (see IC)

Status Register 2

b0 MD Missing Address Mark in Data Field (DAM not found)
b1 BC Bad Cylinder (read/programmed track-ID different and read-ID = FF)
b2 SN Scan Not Satisfied (no fitting sector found)
b3 SH Scan Equal Hit (equal)
b4 WC Wrong Cylinder (read/programmed track-ID different) (see b1)
b5 DD Data Error in Data Field (CRC-fail in data-field)
b6 CM Control Mark (read/scan command found sector with deleted DAM)
b7 0 Not Used

Status Register 3

b0,1 US Unit Select (pin 28,29 of FDC)
b2 HD Head Address (pin 27 of FDC)
b3 TS Two Side (0=yes, 1=no (!))
b4 T0 Track 0 (on track 0 we are)
b5 RY Ready (drive ready signal)
b6 WP Write Protected (write protected)
b7 FT Fault (if supported: 1=Drive failure)

== Motor On/Off Flipflop ==
Writing 00h to Port FA7Eh turns all disk drive motors off, writing 01h turns all motors on. It is not possible to turn on/off the motor of a specific drive separately.
An exception are the Vortex F1-S, F1-D, M1-S and M1-D drives.

== Notes ==

Before accessing a disk you should issue a ''recalibrate'' command to the drive to move the head backwards until the ''track zero'' signal from the drive is sensed by the FDC. The FDC will also set its track counter for that drive to zero.

On an 80-track drive you may need to repeat that twice because some models of the FDC stop after 77 steps so if recalibrating from track 78 or above the controller might not reach track zero.

In order to format, read or write a sector on a specific track you must first ''seek'' that track using command 0Fh. That'll move the read/write head to the physical track number. If you don't do that then the FDC will attempt to read/write data from/to the current physical track, irrespective of the specified logical ''track ID''.

The ''track'', ''sector'', and ''head'' IDs are logical IDs only. These logical IDs are defined when formatting the disk and aren't required to reflect the physical track, sector, or head numbers. However, when reading or writing a sector you must specify the same IDs that have been used during formatting.

Despite the name, a sector with a ''Deleted data Address Mark'' (DAM) is not deleted; the DAM-flag is just another ID bit. 'Deleted' sectors can be read/written just like normal data sectors and if that ID bit is specified correctly in the command.

At the end of a successful read or write command, the program should send a ''Terminal Count'' (TC) signal to the FDC. However, in the CPC the TC pin isn't connected to the I/O bus, making it impossible for the program to confirm a correct operation. For that reason, the FDC will assume that the command has failed, and it'll return both Bit 6 in Status Register 0 and Bit 7 in Status Register 1 set. The program should ignore this error message.

The CPC doesn't support floppy DMA transfers, and the FDCs Interrupt signal isn't used in the CPC.

Usually single sided 40-track 3" disk drives are used in CPCs. For practical purposes, 42 tracks could be used — the limit is specific to the drive and some support more tracks but 42 is a good maximum. The FDC controller can be used to control 80-tracks and/or double sided drives, though AMSDOS doesn't support such formats. AMSDOS supports a maximum of two disk drives only.

== Datasheets ==

* [[Media:UPD765 Datasheet OCRed.pdf]] - uPD765 disc controller
* [[Media:FDC9229BT Datasheet.pdf]] - FDC9229BT data separator (that usually assists the uPD765 chip)
* [[Media:DDI Schematic.png]] - DDI-1 Schematic (disc interface for CPC464)

[[Category:CPC Internal Components]][[Category:Programming]][[Category:DATA Storage]][[Category:Electronic Component]]

765 FDC

2017-07-28T13:04:56Z

Thomasharte: Removed incorrect apostrophe.

µPD765 - Floppy Disc Controller (used in [[DDI-1]] and CPC 664/6128).

* Port FA7Eh - Floppy Motor On/Off Flipflop
* Port FB7Eh - FDC 765 Main Status Register (read only)
* Port FB7Fh - FDC 765 Data Register (read/write)

== IC Models used in CPC ==

More than one manufacturer made 765 compatible ICs. These are the ones known to be used in the CPC by looking at pictures of CPC mainboards.
All should operate almost identically.

* [[Zilog]] Z0765A08PSC
* NEC D765AC-2
* NEC D765AC
* UMC UM8272A

The following data seperators are used:

* FDC9216

== Accessing the FDC 765 ==
The Data Register (Port FB7Fh) is used to write Commands and Parameters, to read/write data bytes, and to receive result bytes. These three operations are called Command-, Execution-, and Result-Phase. The Main Status Register signalizes when the FDC is ready to send/receive the next byte through the Data Register.

Command Phase
A command consists of a command byte (eventually including the MF, MK, SK bits), and up to eight parameter bytes.

Execution Phase
During this phase, the actual data is transferred (if any). Usually that are the data bytes for the read/written sector(s), except for the Format Track Command, in that case four bytes for each sector are transferred.

Result Phase
Returns up to seven result bytes (depending on the command) that are containing status information. The Recalibrate and Seek Track commands do not return result bytes directly, instead the program must wait until the Main Status Register signalizes that the command has been completed, and then it must (!) send a Sense Interrupt State command to 'terminate' the Seek/Recalibrate command.

== FDC Command Table ==

Command Parameters Exm Result Description
02+MF+SK HU TR HD ?? SZ NM GP SL <R> S0 S1 S2 TR HD NM SZ read track
03 XX YY - specify spd/dma
04 HU - S3 sense drive state
05+MT+MF HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ write sector(s)
06+MT+MF+SK HU TR HD SC SZ LS GP SL <R> S0 S1 S2 TR HD LS SZ read sector(s)
07 HU - recalib.seek TP=0
08 - - S0 TP sense int.state
09+MT+MF HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ wr deleted sec(s)
0A+MF HU - S0 S1 S2 TR HD LS SZ read ID
0C+MT+MF+SK HU TR HD SC SZ LS GP SL <R> S0 S1 S2 TR HD LS SZ rd deleted sec(s)
0D+MF HU SZ NM GP FB <W> S0 S1 S2 TR HD LS SZ format track
0F HU TP - seek track n
11+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan equal
19+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan low or equal
1D+MT+MF+SK HU TR HD SC SZ LS GP SL <W> S0 S1 S2 TR HD LS SZ scan high or eq.

Parameter bits that can be specified in some Command Bytes are:

MT Bit7 Multi Track (continue multi-sector-function on other head)
MF Bit6 MFM-Mode-Bit (Default 1=Double Density)
SK Bit5 Skip-Bit (set if secs with deleted DAM shall be skipped)

Parameter/Result bytes are:

HU b0,1=Unit/Drive Number, b2=Physical Head Number, other bits zero
TP Physical Track Number
TR Track-ID (usually same value as TP)
HD Head-ID
SC First Sector-ID (sector you want to read)
SZ Sector Size (80h shl n) (default=02h for 200h bytes)
LS Last Sector-ID (should be same as SC when reading a single sector)
GP Gap (default=2Ah except command 0D: default=52h)
SL Sectorlen if SZ=0 (default=FFh)
Sn Status Register 0..3
FB Fillbyte (for the sector data areas) (default=E5h)
NM Number of Sectors (default=09h)
XX b0..3=headunload n*32ms (8" only), b4..7=steprate (16-n)*2ms
YY b0=DMA_disable, b1-7=headload n*4ms (8" only)

Format Track: output TR,HD,SC,SZ for each sector during execution phase
Read Track: reads NM sectors (starting with first sec past index hole)
Read ID: read ID bytes for current sec, repeated/undelayed read lists all IDs
Recalib: walks up to 77 tracks, 80tr-drives may need second recalib if failed
Seek/Recalib: All read/write commands will be disabled until succesful senseint
Senseint: Set's IC if unsuccesful (no int has occured) (until IC=0)

== FDC Status Registers ==

The Main Status register can be always read through Port FB7E. The other four Status Registers cannot be read directly, instead they are returned through the data register as result bytes in response to specific commands.

Main Status Register (Port FB7E)

b0..3 DB FDD0..3 Busy (seek/recalib active, until succesful sense intstat)
b4 CB FDC Busy (still in command-, execution- or result-phase)
b5 EXM Execution Mode (still in execution-phase, non_DMA_only)
b6 DIO Data Input/Output (0=CPU->FDC, 1=FDC->CPU) (see b7)
b7 RQM Request For Master (1=ready for next byte) (see b6 for direction)

Status Register 0

b0,1 US Unit Select (driveno during interrupt)
b2 HD Head Address (head during interrupt)
b3 NR Not Ready (drive not ready or non-existing 2nd head selected)
b4 EC Equipment Check (drive failure or recalibrate failed (retry))
b5 SE Seek End (Set if seek-command completed)
b6,7 IC Interrupt Code (0=OK, 1=aborted:readfail/OK if EN, 2=unknown cmd
or senseint with no int occured, 3=aborted:disc removed etc.)

Status Register 1

b0 MA Missing Address Mark (Sector_ID or DAM not found)
b1 NW Not Writeable (tried to write/format disc with wprot_tab=on)
b2 ND No Data (Sector_ID not found, CRC fail in ID_field)
b3,6 0 Not used
b4 OR Over Run (CPU too slow in execution-phase (ca. 26us/Byte))
b5 DE Data Error (CRC-fail in ID- or Data-Field)
b7 EN End of Track (set past most read/write commands) (see IC)

Status Register 2

b0 MD Missing Address Mark in Data Field (DAM not found)
b1 BC Bad Cylinder (read/programmed track-ID different and read-ID = FF)
b2 SN Scan Not Satisfied (no fitting sector found)
b3 SH Scan Equal Hit (equal)
b4 WC Wrong Cylinder (read/programmed track-ID different) (see b1)
b5 DD Data Error in Data Field (CRC-fail in data-field)
b6 CM Control Mark (read/scan command found sector with deleted DAM)
b7 0 Not Used

Status Register 3

b0,1 US Unit Select (pin 28,29 of FDC)
b2 HD Head Address (pin 27 of FDC)
b3 TS Two Side (0=yes, 1=no (!))
b4 T0 Track 0 (on track 0 we are)
b5 RY Ready (drive ready signal)
b6 WP Write Protected (write protected)
b7 FT Fault (if supported: 1=Drive failure)

== Motor On/Off Flipflop ==
Writing 00h to Port FA7Eh turns all disk drive motors off, writing 01h turns all motors on. It is not possible to turn on/off the motor of a specific drive separately.
An exception are the Vortex F1-S, F1-D, M1-S and M1-D drives.

== Notes ==

Before accessing a disk you should first "Recalibrate" the drive, that moves the head backwards until it reaches Track 0. (The Track 0 signal from the drive is sensed by the FDC and it initializes its internal track counter for that drive to 0).

On a 80 track drive you may need to repeat that twice because some models of the FDC stop after 77 steps and if your recalibrating from track 80 it will not recalibrate fully.

Now if you want to format, read or write a sector on a specific track you must first Seek that track (command 0Fh). That'll move the read/write head to the physical track number. If you don't do that, then the FDC will attempt to read/write data to/from the current physical track, independenly of the specified logical Track-ID.

The Track-, Sector-, and Head-IDs are logical IDs only. These logical IDs are defined when formatting the disk, and aren't required to be identical to the physical Track, Sector, or Head numbers. However, when reading or writing a sector you must specify the same IDs that have been used during formatting.

Despite the confusing name, a sector with a "Deleted Data Address Mark" (DAM) is not deleted. The DAM-flag is just another ID-bit, and (if that ID-bit is specified correctly in the command) it can be read/written like normal data sectors.

At the end of a successful read/write command, the program should send a Terminal Count (TC) signal to the FDC. However, in the CPC the TC pin isn't connected to the I/O bus, making it impossible for the program to confirm a correct operation. For that reason, the FDC will assume that the command has failed, and it'll return both Bit 6 in Status Register 0 and Bit 7 in Status Register 1 set. The program should ignore this error message.

The CPC doesn't support floppy DMA transfers, and the FDCs Interrupt signal isn't used in the CPC also.

Usually single sided 40 Track 3" disk drives are used in CPCs, whereas 40 tracks is the official specification, practically 42 tracks could be used (the limit is specific to the FDD, some support more tracks. 42 is a good maximum). The FDC controller can be used to control 80 tracks, and/or double sided drives also, even though AMSDOS isn't supporting such formats. AMSDOS is supporting a maximum of two disk drives only.

== Datasheets ==

* [[Media:UPD765 Datasheet OCRed.pdf]] - uPD765 disc controller
* [[Media:FDC9229BT Datasheet.pdf]] - FDC9229BT data separator (that usually assists the uPD765 chip)
* [[Media:DDI Schematic.png]] - DDI-1 Schematic (disc interface for CPC464)

[[Category:CPC Internal Components]][[Category:Programming]][[Category:DATA Storage]][[Category:Electronic Component]]