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Format:DSK disk image file format

2024-10-14T15:37:48Z

Lordheavy: /* Extensions to the above specification */

8255

2023-08-15T11:56:12Z

Lordheavy: /* Programming Examples */

== 8255 Part numbers used in the CPC during its lifetime ==

* NEC D8255AC-2
* NEC D8255AC-5
* Toshiba TMP8255AP-5

All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.

== The 8255 in the CPC ==

The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.

The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O address''||''A9''||''A8''||''Description''||''Read/Write status''||''Used Direction''||''Used for''
|-
|&F4xx||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick)
|-
|&F5xx||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
|-
|&F6xx||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
|-
|&F7xx||1||1||Control||Write Only||Out||Control
|-
|}

In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.

* Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used.

== Port Usage ==

* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.

== PPI Port A ==

Operating system settings:
* I/O Mode 0,
* For writing data to PSG all bits must be set to output,
* for reading data from PSG all bits must be set to input (thereafter, output direction should be restored, for compatibility with the BIOS).

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)
|-
|}

== PPI Port B ==

Operating system settings:

* I/O Mode 0,
* Input

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage in CPC''||''Usage in KC Compact''
|-
|7||CAS.IN||Cassette data input||Same as on CPC
|-
|6||PRN.BUSY||Parallel/Printer port ready signal, "1" = not ready, "0" = Ready||Same as on CPC
|-
|5||/EXP||Expansion Port /EXP pin||Same as on CPC
|-
|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
|-
|2||LK2||Purpose unknown (set to "0")
|-
|1||LK1||Expansion Port /TEST pin
|-
|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
|-
|}

* LK1-4 are links on the mainboard ("0" bits are wired to GND). On CPC464,CPC664,CPC6128 and GX4000 they are labeled LK1-LK4, on the CPC464+ and CPC6128+ they are labeled LK101-LK103 (and LK104, presumably?).

* Bit5 (/EXP) can be used by a expansion device to report its presence. "1" = device connected, "0" = device not connected. This is not always used by all expansion devices. ''is it used by any expansions?'' [in the DDI-1 disc interface, /EXP connects to the ROM bank selection, bank 0 or bank 7]

* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.

* For more info on LK1-LK4 (and further LKs) see [[LK Links]]

== PPI Port C ==

Operating system settings:

* upper: I/O Mode 0, lower: I/O mode 0,
* upper: output, lower: output

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7||PSG BDIR||PSG function selection
|-
|6||PSG BC1||
|-
|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
|-
|4||Cassette Motor Control||set bit to "1" for motor on, or "0" for motor off
|-
|3||rowspan=4|Keyboard line||rowspan=4|Select keyboard line to be scanned (0-15)
|-
|2
|-
|1
|-
|0
|-
|}

PSG function selection:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit 7''||''Bit 6''||''Function''
|-
|0||0||Inactive
|-
|0||1||Read from selected PSG register
|-
|1||0||Write to selected PSG register
|-
|1||1||Select PSG register
|-
|}

== PPI Control ==

This register has two different functions depending on bit7 of the data written to this register.

=== PPI Control with Bit7=1 ===
If Bit 7 is "1" then the other bits will initialize Port A-B as Input or Output:

Bit 0 IO-Cl Direction for Port C, lower bits (always 0=Output in CPC)
Bit 1 IO-B Direction for Port B (always 1=Input in CPC)
Bit 2 MS0 Mode for Port B and Port Cl (always zero in CPC)
Bit 3 IO-Ch Direction for Port C, upper bits (always 0=Output in CPC)
Bit 4 IO-A Direction for Port A (0=Output, 1=Input)
Bit 5,6 MS0,MS1 Mode for Port A and Port Ch (always zero in CPC)
Bit 7 SF Must be "1" to setup the above bits

* CAUTION: Writing to PIO Control Register (with Bit7 set), automatically resets PIO Ports A,B,C to 00h each!
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.

=== PPI Control with Bit7=0 ===
Otherwise, if Bit 7 is "0" then the register is used to set or clear a single bit in Port C:

Bit 0 B New value for the specified bit (0=Clear, 1=Set)
Bit 1-3 N0,N1,N2 Specifies the number of a bit (0-7) in Port C
Bit 4-6 - Not Used
Bit 7 SF Must be "0" in this case

== Programming Examples ==

1. Using the control byte

* Setting bit 7 of port C to 1,

<pre>
LD B,&F7 ;8255 Control port
LD A,%00001111 ;Bit Set/reset function
OUT (C),A ;Send it to 8255
RET
</pre>

* Set port A to input, operating in mode 0, port B to output, operating in mode 0 and port C to input, operating in mode 0.

<pre>
LD B,&F7 ;8255 Control port
LD A,%10011001 ;Configuration function
OUT (C),A ;Send it to 8255
RET
</pre>

2. Using port A/B/C,

In this example, port A is set to output, port B is set to input, and port C is set to output, and they are all operating in mode 0.

We will only be using port A for these examples.
* Reading from port A,

<pre>
;Set port A to input

LD B,&F7 ;8255 Control port
LD A,%10010010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;Port A port address
IN E,(C) ;Get byte from port

;Register E holds value from port

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255
RET
</pre>

* Writing to port A,

<pre>
;Set port A to output

;(Note the next few lines are not necessary
;as port A is already acting as output, however
;it is given here just to make the example
;more understandable)

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;port A port address

;Register E holds value to put into port

LD E,&FF ;Data to put into port
OUT (C),E ;Send to port A

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A
RET
</pre>

= Diagrams =

[[Image:8255 ppi 1.jpg]]

[[Image:8255 ppi 2.jpg]]

= Resources =

* [[Media:Intel_8255A_Datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL implementation of the 8255 PIO]]

= Links =

*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]
*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]

[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]

8255

2023-08-15T11:55:15Z

Lordheavy: Value assigned in the wrong register

== 8255 Part numbers used in the CPC during its lifetime ==

* NEC D8255AC-2
* NEC D8255AC-5
* Toshiba TMP8255AP-5

All of these are almost identical in their operation. It is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back.

== The 8255 in the CPC ==

The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.

In these systems it is connected to the AY-3-8912 Programmable Sound Generator (PSG), keyboard, cassette recorder, the VSYNC of the 6845 CRTC and the "busy" signal from the parallel port.

The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O address''||''A9''||''A8''||''Description''||''Read/Write status''||''Used Direction''||''Used for''
|-
|&F4xx||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick)
|-
|&F5xx||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
|-
|&F6xx||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
|-
|&F7xx||1||1||Control||Write Only||Out||Control
|-
|}

In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.

* Mode 1 (Strobed Input/Output) and Mode 2 (Bi-Directional Bus), as far as I know, are not used by any program, Mode 0 (Basic Input/Output) is always used.

== Port Usage ==

* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.

== PPI Port A ==

Operating system settings:
* I/O Mode 0,
* For writing data to PSG all bits must be set to output,
* for reading data from PSG all bits must be set to input (thereafter, output direction should be restored, for compatibility with the BIOS).

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)
|-
|}

== PPI Port B ==

Operating system settings:

* I/O Mode 0,
* Input

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage in CPC''||''Usage in KC Compact''
|-
|7||CAS.IN||Cassette data input||Same as on CPC
|-
|6||PRN.BUSY||Parallel/Printer port ready signal, "1" = not ready, "0" = Ready||Same as on CPC
|-
|5||/EXP||Expansion Port /EXP pin||Same as on CPC
|-
|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
|-
|2||LK2||Purpose unknown (set to "0")
|-
|1||LK1||Expansion Port /TEST pin
|-
|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
|-
|}

* LK1-4 are links on the mainboard ("0" bits are wired to GND). On CPC464,CPC664,CPC6128 and GX4000 they are labeled LK1-LK4, on the CPC464+ and CPC6128+ they are labeled LK101-LK103 (and LK104, presumably?).

* Bit5 (/EXP) can be used by a expansion device to report its presence. "1" = device connected, "0" = device not connected. This is not always used by all expansion devices. ''is it used by any expansions?'' [in the DDI-1 disc interface, /EXP connects to the ROM bank selection, bank 0 or bank 7]

* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.

* For more info on LK1-LK4 (and further LKs) see [[LK Links]]

== PPI Port C ==

Operating system settings:

* upper: I/O Mode 0, lower: I/O mode 0,
* upper: output, lower: output

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit''||''Description''||''Usage''
|-
|7||PSG BDIR||PSG function selection
|-
|6||PSG BC1||
|-
|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
|-
|4||Cassette Motor Control||set bit to "1" for motor on, or "0" for motor off
|-
|3||rowspan=4|Keyboard line||rowspan=4|Select keyboard line to be scanned (0-15)
|-
|2
|-
|1
|-
|0
|-
|}

PSG function selection:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Bit 7''||''Bit 6''||''Function''
|-
|0||0||Inactive
|-
|0||1||Read from selected PSG register
|-
|1||0||Write to selected PSG register
|-
|1||1||Select PSG register
|-
|}

== PPI Control ==

This register has two different functions depending on bit7 of the data written to this register.

=== PPI Control with Bit7=1 ===
If Bit 7 is "1" then the other bits will initialize Port A-B as Input or Output:

Bit 0 IO-Cl Direction for Port C, lower bits (always 0=Output in CPC)
Bit 1 IO-B Direction for Port B (always 1=Input in CPC)
Bit 2 MS0 Mode for Port B and Port Cl (always zero in CPC)
Bit 3 IO-Ch Direction for Port C, upper bits (always 0=Output in CPC)
Bit 4 IO-A Direction for Port A (0=Output, 1=Input)
Bit 5,6 MS0,MS1 Mode for Port A and Port Ch (always zero in CPC)
Bit 7 SF Must be "1" to setup the above bits

* CAUTION: Writing to PIO Control Register (with Bit7 set), automatically resets PIO Ports A,B,C to 00h each!
* In the CPC only Bit 4 is of interest, all other bits are always having the same value. In order to write to the PSG sound registers, a value of 82h must be written to this register. In order to read from the keyboard (through PSG register 0Eh), a value of 92h must be written to this register.

=== PPI Control with Bit7=0 ===
Otherwise, if Bit 7 is "0" then the register is used to set or clear a single bit in Port C:

Bit 0 B New value for the specified bit (0=Clear, 1=Set)
Bit 1-3 N0,N1,N2 Specifies the number of a bit (0-7) in Port C
Bit 4-6 - Not Used
Bit 7 SF Must be "0" in this case

== Programming Examples ==

1. Using the control byte

* Setting bit 7 of port C to 1,

<pre>
LD B,&F7 ;8255 Control port
LD A,%00001111 ;Bit Set/reset function
OUT (C),A ;Send it to 8255
RET
</pre>

* Set port A to input, operating in mode 0, port B to output, operating in mode 0 and port C to input, operating in mode 0.

<pre>
LD B,&F7 ;8255 Control port
LD A,%10011001 ;Configuration function
OUT (C),A ;Send it to 8255
RET
</pre>

2. Using port A/B/C,

In this example, port A is set to output, port B is set to input, and port C is set to output, and they are all operating in mode 0.

We will only be using port A for these examples.
* Reading from port A,

<pre>
;Set port A to input

LD B,&F7 ;8255 Control port
LD A,%10010010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;Port A port address
IN E,(C) ;Get byte from port

;Register E holds value from port

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255
RET
</pre>

* Writing to port A,

<pre>
;Set port A to output

;(Note the next few lines are not necessary
;as port A is already acting as output, however
;it is given here just to make the example
;more understandable)

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A ;Send to 8255

LD B,&F4 ;port A port address

;Register E holds value to put into port

LD A,&FF ;Data to put into port
OUT (C),A ;Send to port A

;Return port I/O status and operating modes
;to previous settings.

LD B,&F7 ;8255 Control port
LD A,%10000010 ;Configuration function
OUT (C),A
RET
</pre>

= Diagrams =

[[Image:8255 ppi 1.jpg]]

[[Image:8255 ppi 2.jpg]]

= Resources =

* [[Media:Intel_8255A_Datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[VHDL implementation of the 8255 PIO]]

= Links =

*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]
*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]

[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]

CRTC

2023-08-05T07:12:08Z

Lordheavy: New crtc compendium version

* ''This is an article about the "Cathode Ray Tube Controller" hardware unit of the Amstrad CPC. For the cpc scene member see [[ChaRleyTroniC]]''

The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

== Timings and relating with Z80 instructions count ==

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O port address''||''Function''||''Read/Write''
|-
|&BCxx||Select 6845 register||Write only
|-
|&BDxx||Write 6845 register data||Write only
|-
|&BExx||(note 1)||Read only
|-
|&BFxx||(note 1)||Read only
|-
|}

'''NOTE'''

1. The function of these I/O ports is dependant on the CRTC type

2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.

==Addressing==

The following table defines the generated memory address from the CRTC and Gate-Array signals.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||RA2
|-
|A12||6845||RA1
|-
|A11||6845||RA0
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.

== DISPTMG ==

DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

== HSYNC and VSYNC ==

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

== The 6845 Registers ==

The Internal registers of the 6845 are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (Low)||00000000||||Read Only
|-
|}

registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

Details about Reg. 12 and Reg. 13 specifically:

.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'

So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

== CRTC Differences ==

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 1

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|}

Type 2

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 3 and 4

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1||2||3||4
|-
|0||Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}

'''Notes'''

1. On type 0 and 1, if a Write Only register is read from, "0" is returned.

2. See the document "Extra CPC Plus Hardware Information" for more details.

3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.

== Horizontal and Vertical Sync (R3) ==

UM6845:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

UM6845R:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

MC6845:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Pre-ASIC/ASIC:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

== UM6845R and R31 ==

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3.

== UM6845R and R12/R13 ==

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

== UM6845R status register ==

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

== Datasheets ==

* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umc.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]]

* [[VHDL implementation of the 6845]]

== Clones ==
* [CM607P a Bulgarian clone made in Pravetz factory]
* [EF6845P by Thomson Semiconductors]

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects - by [[Elmar Krieger]] ] (DSK for Emulators)

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTCs on grimware]
* [http://logon.system.free.fr/down/ACCC1.6-EN.pdf Amstrad Cpc Crtc Compendium] Latest (2023!!) document containing in-depth info about CRTC programming on CPC.

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

Format:SNA snapshot file format

2022-08-07T10:00:30Z

Lordheavy: cleanup example of RLE compression

[[Category:Cpctech.org]]
<div style="border: 1px solid rgb(228, 222, 222); margin: 0px 0px 5px; padding: 0.5em 1em; background-color: rgb(249, 249, 249);">
<center>

'''''This article originally came from Kevin Thackers' archive at [http://www.cpctech.org.uk http://www.cpctech.org.uk].''''' </center></div>

= Snapshot (.SNA) file format =

The format was first defined for the CPCEMU emulator but is now widely supported. The format was originally defined by Marco Vieth. Version 3 was defined by Ulrich Doewich, Martin Korth, Richard Wilson and Kevin Thacker.

There are 3 versions defined in this document. Version 3 is the most recent and is currently supported by a few of the most recent emulators.

Abbreviations:

*GA = "Gate Array"
*CRTC = "6845 Cathode Ray Tube Controller"
*PPI = "Intel 8255 Programmable Peripheral Interface"
*PSG = "AY-3-8912 Programmable Sound Generator"

== Version 1 ==

{| border="1"
|-
! Offset (Hex)
! Count
! Description
|-
| 00-07
| 8
| The identification string "MV - SNA". This must exist for the snapshot to be valid.
|-
| 08-0f
| 8
| (not used; set to 0)
|-
| 10
| 1
| snapshot version (1)
|-
| 11
| 1
| Z80 register F
|-
| 12
| 1
| Z80 register A
|-
| 13
| 1
| Z80 register C
|-
| 14
| 1
| Z80 register B
|-
| 15
| 1
| Z80 register E
|-
| 16
| 1
| Z80 register D
|-
| 17
| 1
| Z80 register L
|-
| 18
| 1
| Z80 register H
|-
| 19
| 1
| Z80 register R
|-
| 1a
| 1
| Z80 register I
|-
| 1b
| 1
| Z80 interrupt flip-flop IFF0 (note 2)
|-
| 1c
| 1
| Z80 interrupt flip-flop IFF1 (note 2)
|-
| 1d
| 1
| Z80 register IX (low) (note 5)
|-
| 1e
| 1
| Z80 register IX (high) (note 5)
|-
| 1f
| 1
| Z80 register IY (low) (note 5)
|-
| 20
| 1
| Z80 register IY (high) (note 5)
|-
| 21
| 1
| Z80 register SP (low) (note 5)
|-
| 22
| 1
| Z80 register SP (high) (note 5)
|-
| 23
| 1
| Z80 register PC (low) (note 5)
|-
| 24
| 1
| Z80 register PC (high) (note 5)
|-
| 25
| 1
| Z80 interrupt mode (0,1,2) (note 3)
|-
| 26
| 1
| Z80 register F' (note 4)
|-
| 27
| 1
| Z80 register A' (note 4)
|-
| 28
| 1
| Z80 register C' (note 4)
|-
| 29
| 1
| Z80 register B' (note 4)
|-
| 2a
| 1
| Z80 register E' (note 4)
|-
| 2b
| 1
| Z80 register D' (note 4)
|-
| 2c
| 1
| Z80 register L' (note 4)
|-
| 2d
| 1
| Z80 register H' (note 4)
|-
| 2e
| 1
| GA: index of selected pen (note 10)
|-
| 2f-3f
| 17
| GA: current palette (note 11)
|-
| 40
| 1
| GA: multi configuration (note 12)
|-
| 41
| 1
| current RAM configuration (note 13)
|-
| 42
| 1
| CRTC: index of selected register (note 14)
|-
| 43-54
| 18
| CRTC: register data (0..17) (note 15)
|-
| 55
| 1
| current ROM selection (note 16)
|-
| 56
| 1
| PPI: port A (note 6)
|-
| 57
| 1
| PPI: port B (note 7)
|-
| 58
| 1
| PPI: port C (note 8)
|-
| 59
| 1
| PPI: control port (note 9)
|-
| 5a
| 1
| PSG: index of selected register (note 17)
|-
| 5b-6a
| 16
| PSG: register data (0,1,....15)
|-
| 6b-6c
| 1
| memory dump size in Kilobytes (e.g. 64 for 64K, 128 for 128k) (note 18)
|-
| 6d-ff
| 93
| not used set to 0
|-
| 100-...
| (defined by memory dump size)
| memory dump
|}

Notes:

#All multi-byte values are stored in little-endian format (low byte followed by higher bytes).
#"IFF0" reflects the state of the maskable interrupt (INT). "IFF1" is used to store the state of IFF0 when a non-maskable interrupt (NMI) is executed. Bit 0 of these bytes is significant. For CPCEMU compatibility, these bytes should be set to "1" when the IFF flip-flop is "1" and "0" when the flip-flop is "0". For compatibility with other emulators, bits 7-1 should be set to "0". When bit 0 of "IFF0" is "0" maskable interrupts will be ignored. When bit 0 of "IFF1" is "1" maskable interrupts will be acknowledged and executed. See the document about the Z80 for more information.
#This byte will be 0, 1 or 2 for the interrupt modes 0, 1 or 2. The interrupt mode is set using the "IM x" instructions. See the document about the Z80 for more information.
#These registers are from the alternate register set of the Z80.
#These registers are 16-bit. "low" indicates bits 7..0, "high"indicates bits 15..8.
#This byte represents the inputs to PPI port A regardless of the input/output setting of this port.
#This byte represents the inputs to PPI port B regardless of the input/output setting of this port.
#This byte represents the outputs from port C regardless of the input/output setting of this port.
#This byte represents the PPI control byte which defines the input/output and mode of each port and not the last value written to this port. For CPCEMU compatibility bit 7 of this byte must be set to "1".
#This byte in the snapshot represents the selected pen register of the Gate-Array. This byte is the last value written to this port. Bit 7,6,5 should be set to "0".
#This byte in the snapshot represents the multi-configuration register of the Gate-Array. This byte is the last byte written to this register. For CPCEMU compatibility, bit 7 should be set to "1" and bit 6 and bit 5 set to "0".
#These bytes are the current palette. For CPCEMU compatibility, these bytes should have bit 7=bit 6=bit 5="0". Bits 4..0 define the colour using the hardware colour code. The colours are stored in the order pen 0, pen1, pen 2,...,pen 15 followed by border colour.
#This byte represents a ram configuration for a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion, or the built in RAM expansion of the CPC6128 and CPC6128+. Bits 5..0 define the ram expansion code. For CPCEMU compatibility, bit 7 and bit 6 of this byte should be set to "0".
#This byte in the snapshot represents the index of the currently selected CRTC register. For compatibility with CPCEMU this value should be in the range 0-31.
#These bytes represent the data of the CRTC's registers.
#This byte in the snapshot represents the last byte written to the "ROM select" I/O port.
#This byte in the snapshot represents the index of the currently selected PSG register. For CPCEMU compatibility, this byte should be in the range 0-15.
#the first 64k is always the base 64k of ram. The second 64k (if present) is the additional ram in a Dk'Tronics/Dobbertin/Amstrad compatible RAM expansion or the internal ram of the CPC6128/CPC6128+. The memory dump is not dependant on the current RAM configuration. Note that CPCEMU can only write a 64K or 128K snapshot.

== Changes and additions in Version 2 from Version 1 ==

{| border="1"
|-
! Offset (Hex)
! Count
! Description
|-
| 10
| 1
| snapshot version (2)
|-
| 6d
| 1
|
CPC type:

*0 = CPC464
*1 = CPC664
*2 = CPC6128
*3 = unknown

|-
| 6e
| 1
| interrupt number (0..5) (note 1a)
|-
| 6f-74
| 6
| 6 multimode bytes (note 1b)
|-
| 75-ff
| x
| (not used)
|}

Notes:

#If standard CPC raster interrupts are used, interrupts are acknowledged and "executed" at the time they are requested, then there will be 6 interrupts executed per screen update cycle.
#*CPCEMU uses a simple system to emulate the interrupts. It is assumed there are exactly 6 interrupts per screen update cycle (the interrupts are assumed to occur at a frequency of 300Hz). This byte records the interrupt number in the current screen update cycle. More accurate emulators use the correct interrupt generation method and may ignore this byte. For CPCEMU compatibility, these emulators should set this byte to "0".
#*CPCEMU uses a simple system to emulate the screen display. It allows the mode to be changed in each of the 6 interrupts that occur during a single 50Hz/60Hz period. These bytes represent the mode in each of these sections, i.e. the screen modes (0,1 or 2) for the interrupts 0..5. More accurate emulators support changing of the screen mode at any point supported by the Amstrad hardware, these emulators should write "0" for all these bytes.

== Changes and additions in Version 3 from Version 2 ==

{| border="1"
|-
! Offset (Hex)
! Count
! Description
|-
| 10
| 1
| snapshot version (3)
|-
| 6d
| 1
|
CPC type:

*0 = CPC464
*1 = CPC664
*2 = CPC6128
*3 = unknown
*4 = 6128 Plus
*5 = 464 Plus
*6 = GX4000

|-
| 9C
| 1
| FDD motor drive state (0=off, 1=on)
|-
| 9D-A0
| 1
| FDD current physical track (note 15)
|-
| A1
| 1
| Printer Data/Strobe Register (note 1)
|-
| A4
| 1
|
CRTC type:

*0 = HD6845S/UM6845
*1 = UM6845R
*2 = MC6845
*3 = 6845 in CPC+ ASIC
*4 = 6845 in Pre-ASIC

|-
| A9
| 1
| CRTC horizontal character counter register (note 11)
|-
| AA
| 1
| unused (0)
|-
| AB
| 1
| CRTC character-line counter register (note 2)
|-
| AC
| 1
| CRTC raster-line counter register (note 3)
|-
| AD
| 1
| CRTC vertical total adjust counter register (note 4)
|-
| AE
| 1
| CRTC horizontal sync width counter (note 5)
|-
| AF
| 1
| CRTC vertical sync width counter (note 6)
|-
| B0-B1
| 2
|
CRTC state flags. (note 7) 

{| border="1"
|-
! Bit
! Function
|-
| 0
| if "1" VSYNC is active, if "0" VSYNC is inactive (note 8)
|-
| 1
| if "1" HSYNC is active, if "0" HSYNC is inactive (note 9)
|-
| 2-7
| reserved
|-
| 7
| if "1" Vertical Total Adjust is active, if "0" Vertical Total Adjust is inactive (note 10)
|-
| 8-15
| Reserved (0)
|}

|-
| B2
| 1
| GA vsync delay counter (note 14)
|-
| B3
| 1
| GA interrupt scanline counter (note 12)
|-
| B4
| 1
| interrupt request flag (0=no interrupt requested, 1=interrupt requested) (note 13)
|-
| B5-FF
| 75
| unused (0)
|}

Notes:

#This byte in the snapshot represents the last byte written to the printer I/O port (this byte does not include the automatic inversion of the strobe caused by the Amstrad hardware).
#This register is internal to the CRTC and counts the number of character-lines. The counter counts up. This value is in the range 0-127. (This counter is compared against CRTC register 4).
#This register is internal to the CRTC and counts the number of raster-lines. The counter counts up. This value is in the range 0-31. (This counter is compared against CRTC register 9).
#This register is internal to the CRTC and counts the number of raster-lines during vertical adjust. The counter counts up. This value is in the range 0-31. This should be ignored if the CRTC is not "executing" vertical. adjust.(This counter is compared against CRTC register 5).
#This register is internal to the CRTC and counts the number of characters during horizontal sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" horizontal sync. (This counter is compared against CRTC register 3).
#This register is internal to the CRTC and counts the number of scan-lines during vertical sync. This counter counts up. This value is in the range 0-16. This should be ignored if the CRTC is not "executing" vertical sync. (This counter is compared against CRTC register 3).
#These bytes define the internal state of the CRTC. Each bit in these bytes represents a state.
#When VSYNC is active, the CRTC is "executing" vertical sync, and the vertical sync width counter in the snapshot is used.
#When HSYNC is active, the CRTC is "executing" horizontal sync width counter in the snapshot is used.
#When Vertical total adjust is active, the CRTC is "executing" vertical total adjust and the vertical total adjust counter in the snapshot is used.
#This register is internal to the CRTC and counts the number of characters. This counter counts up. This value is in the range 0-255. (This counter is compared against CRTC register 0).
#This counter is internal to the GA and counts the number of HSYNCs. This counter is used to generate CPC raster interrupts. This counter counts up. This value is in the range 0-51.
#This flag is "1" if a interrupt request has been sent to the Z80 and it has not yet been acknowledged by the Z80. (A interrupt request is sent by the GA for standard CPC raster interrupts or by the ASIC for raster or dma interrupts).
#This is a counter internal to the GA and counts the number of HSYNCs since the start of the VSYNC and it is used to reset the interrupt counter to synchronise interrupts with the VSYNC. This counter counts up. This value is between 0 and 2. If this value is 0, the counter is inactive. If this counter is 1 or 2 the counter is active.

Immediatly following the memory dump there is optional data which is seperated into chunks.

Each chunk of data has a header and this is followed by the data in the chunk. The header has the following format:

{| border="1"
|-
! Offset (Hex)
! Count
! Description
|-
| 0
| 4
| Chunk name (note 1)
|-
| 4
| 4
| Chunk data length (note 2)
|}

Notes:

#The chunks are defined with 4-byte character codes. (e.g. "CPC+"). In this example, the 4-byte character code would be stored in the file as 'C' then 'P' then 'C' then '+'.
#The "Chunk data length" defines the length of data following the header and does not include the size of the header. This number is stored in little endian format.
#If a emulator finds a chunk which it does not support then it should skip the chunk and continue with the next chunk in the file. Therefore an emulator author may add emulator specific chunks to the file and it will not prevent the snapshot from being used with other emulators that do not recognise the added chunks.
#There is not a terminator chunk. The snapshot reader should determine if there are more chunks based on the size of data remaining to be read from the file.

The following chunks are currently defined:

== V3 Chunks ==

=== CPC+ Chunk (Plus only) ===

Chunk name: "CPC+"

If this chunk exists assume that you should use a 464Plus/6128Plus configuration to run the snapshot.

Chunk data:

{| border="1"
|-
! Offset (Hex)
! Length
! Addr in ASIC register-ram
! Description
|-
| 000-7FF
| 800h
| 4000-4FFF
| Sprite Bitmaps (note 1)
|-
| 800-87F
| 8*16
| 6000-607F
| Sprite Attributes (see below) (note 2)
|-
| 880-8BF
| 32*2
| 6400-643F
| Palettes (note 3)
|-
| 8C0
| 1
| 6800
| Programmable Raster Interrupt (note 4)
|-
| 8C1
| 1
| 6801
| Screen split scan-line (note 4)
|-
| 8C2
| 2
| 6802-6803
| Screen split secondary screen-address (note 4)
|-
| 8C4
| 1
| 6804
| Soft scroll control register (note 4)
|-
| 8C5
| 1
| 6805
| Interrupt vector (note 4)
|-
| 8C6-8C7
| 2
| -
| unused (0)
|-
| 8C8-8CF
| 8
| 6808-680f
| Analogue input channels 0-7 (note 5)
|-
| 8D0-8DB
| 3*4
| 6C00-6C0B
| Sound DMA channel attributes 0-2 (see below) (note 6)
|-
| 8DC-8DE
| 3
| -
| unused (0)
|-
| 8DF
| 1
| 6C0F
| DMA Control/Status (note 4)
|-
| 8E0-8F4
| 3*7
| internal
| DMA channel 0-2 internal registers (see below) (note 7)
|-
| 8F5
| 1
| internal
| gate array A0 register value (note 8)
|-
| 8F6
| 1
| internal
| gate array A0 lock: 0=locked, 1=unlocked (note 9)
|-
| 8F7
| 1
| internal
| ASIC unlock sequence state (note 10)
|}

Notes:

1. The sprite data is packed, with two sprite pixels per byte. Bits 7..4 define the first pixel and bits 3..0 define the second pixel. 2. The attributes for each sprite take 8 bytes. Each attribute block has the following format:

{| border="1"
|-
! Offset 
! Length 
! Description
|-
| 0
| 2
| Sprite X (see note)
|-
| 2
| 2
| Sprite Y (see note)
|-
| 4
| 1
| Sprite Magnification (see note)
|-
| 5-7
| 3
| unused (0)
|}

Note: the Sprite X, Y and magnification are in the same order as the ASIC registers

3. This is a direct copy of the palette in CPC+ ASIC Ram. There are 32 colours each with 2-bytes per colour. 4. These bytes in the snapshot represent the last value written to these ASIC registers. 5. These bytes represent the inputs to the analogue channels. 6. The attributes for each DMA channel take 4 bytes. Each attribute block has the following format:

{| border="1"
|-
! Offset 
! Length 
! Description
|-
| 0
| 2
| DMA Channel address (see note)
|-
| 2
| 1
| DMA Channel prescalar (see note)
|-
| 3
| 1
| unused (0)
|}

Note: the DMA address and prescalar are in the same order as the ASIC registers.

7. These registers are internal to the CPC+ and define the current DMA operation:

{| border="1"
|-
! Offset 
! Length 
! Description
|-
| 0
| 2
| loop counter (note a)
|-
| 2
| 2
| loop address (note b)
|-
| 4
| 2
| pause count (note c)
|-
| 6
| 1
| pause prescalar count (note d)
|}

a.) This value represents the number of loops remaining. 0 = none. This count is between 0..0FFF. This counter counts down. b.) This is the Amstrad memory address to loop back to. It is a pointer to the DMA instruction after the last REPEAT instruction. c.) This value represents the pause count and the count is between 0...0FFF. (TO BE CHECKED: down counter? what exactly does it represent) d.) This value represents the pause prescalar count and the count is between 0..FF. (TO BE CHECKED: down counter? what exactly does it represent) 

8. This value represents the last value written to this I/O port. 9. This value represents the lock status of the ASIC. If the ASIC is un-locked then the advanced features and ASIC registers are accessible. 10. This value represents the current unlock sequence state.

{| border="1"
|-
! State ID 
! Synchronised State 
! Note
|-
| 0
| not synchronised
| ASIC is waiting for first non-zero byte to be written, this is the first synchronisation byte required
|-
| 1
| not synchronised
| ASIC is waiting for zero byte to be written, this is the second synchronisation byte required
|-
| 2..10h
| synchronised
| ASIC is waiting for byte from unlock sequence. e.g. if "2", ASIC is waiting for &FF, the first byte of the unlock sequence. if "3" ASIC is waiting for &77, the second byte of the unlock sequence.
|}

=== Memory block chunks (CPC/Plus/KC Compact/Aleste) ===

There may be 1 or more of these memory blocks.

Chunk name: MEM0..MEM8.

Each block represents 64K.

MEM0 describes the standard on-board 64k.
MEM1...MEM8 for memory expansion bank.
The MEM1..MEM8 memory blocks map to RAM expansions:
* MEM1 = extra 64KB ram in CPC6128 or 6128Plus
* MEM1-4 = 256KB dk'tronics compatible ram expansion
* MEM5-8 = 256KB dk'tronics silicon disk compatible

Other RAM expansions have the full 512KB such as the X-MEM. These map to MEM1-MEM8.

If a chunk exists in the snapshot that means that memory is stored compressed.

It is possible to have a snapshot with 64KB base ram uncompressed and additional banks compressed but it's advised to either use MEM chunks or store the memory uncompressed in the V2 style.

The memory size in the snapshot refers to the amount of uncompressed V2 style memory that is in the snapshot. If the memory is described only by chunks it is 0.
If there is both uncompressed and compressed data then the compressed data takes priority over the uncompressed data. I.e. handle the uncompressed data first then the compressed data.

A RLE compression is used with 0x0e5 as the control byte.

i.e. <control byte>, <count>, <byte>

Examples (Uncompressed = Compressed):
* 11 22 33 = 11 22 33
* E5 03 11 = 11 11 11
* E5 00 = E5

=== Breakpoint chunk (Winape emulator specific) ===

Breakpoint chunk has the name "BRKS".

The chunk contains 1 or more breakpoints.

Each breakpoint has the form:

2 byte address
1 byte code (0=base 64K RAM, 1 = extended RAM)
2 bytes condition

=== Inserted disc images (Winape emulator specific) ===

There are two chunks. 'DSCA' and 'DSCB'.
DSCA is for drive A and DSCB is for drive B.

The chunk contains a string which is the path to the disk image inserted into that drive.

== Memory ==

Uncompressed memory described by the snapshot allows sizes of:
* 64K (base 64K only),
* 128K (base 64K + 64K dk'tronics compatible RAM expansion using ram selections C4-C7),
* 312K (base 64K+256K dk'tronics compatible RAM expansion using ram selections C4-CC),
* 576K (base 64K+512K RAM composed of dk'tronics compatible 256K RAM AND dk'tronics compatible 256K silicon disk). Ram selections c4-ff.

The MEM chunks do allow to describe RAM expansions where the configurations are not continuous. (e.g. 64K base + 256K silicon disk).

== Limitations of this snapshot format==
* The snapshot format doesn't support more than 512K RAM and only supports dk'tronics compatible RAM expansions.
* The snapshot format doesn't support additional hardware. A basic CPC464, CPC664, CPC6128 system is assumed.
* The snapshot format doesn't support KC Compact or Aleste hardware.
* The snapshot doesn't have knowledge of which ROMs are in use. This means it doesn't know which OS, BASIC or AMSDOS ROM, and nothing about expansion roms.

The format generally assumes a base CPC6128/6128Plus system with no attached hardware except for up to 512K of dk'tronics compatible RAM.