CPCWiki - THE Amstrad CPC encyclopedia! - User contributions [en]

Programming:Unlocking ASIC

2025-11-21T21:10:06Z

Longshot:

To unlock the [[ASIC]], a 17-byte "unlock" sequence must be sent to the [[CRTC]]'s selection port (&BC00) :
RQ00, 0, 255, 119, 179, 81, 168, 212, 98, 57, 156, 70, 43, 21, 138, STATE, <ACQ>
* RQ00 must be different from the value 0.
* STATE=205 for UNLOCK otherwise another value for LOCK.
* ACQ represents sending any value if STATE=205 (not needed otherwise).

Note: the ASIC is already unlocked after the STATE phase, before ACQ. So ACQ is actually never needed.

Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.

Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]

 

= BASIC version =
<pre>
10 RESTORE
20 FOR x=0 TO 16:READ a:OUT &BC00,a:NEXT
30 DATA 255,0,255,119,179,81,168,212,98,57,156,70,43,21,138,205,238
40 PRINT"ASIC unlocked!"
</pre>

 

= Z80 Assembler version =
<pre>
;; This example shows how to unlock the ASIC
;;
;; This example is designed for CPC+ only and will
;; not work on CPC or KC Compact.
;;
;; This example will compile with the MAXAM assembler
;; or the built-in assembler of WinAPE32.

org &8000

;;--------------------------------------------------
;; Unlock CPC+ additional features

di
ld b,&bc
ld hl,sequence
ld e,17

.seq
ld a,(hl)
out (c),a
inc hl
dec e
jr nz,seq

ei
ret

;;----------------------------------------------------------
;; this is the sequence to unlock the ASIC extra features
.sequence
defb &ff,&00,&ff,&77,&b3,&51,&a8,&d4,&62,&39,&9c,&46,&2b,&15,&8a,&cd,&ee
</pre>

 

= Optimized versions =

The unlocking sequence can be reconstituted from simple bit operations instead of being stored in memory.

== [[Madram]] version ==

It still uses some magic numbers.

<pre>
di
ld bc,#BCFF
out (c),c
out (c),0
ld hl,%1001000011101010

loop:
out (c),c
ld a,h:rlca:ld h,l:ld l,a
srl c
xor c:and #88:xor c
ld c,a
cp #4D
jr nz,loop

ld a,#CD ; a = #CD for unlock, another value for lock
out (c),a:out (c),a
ei
ret
</pre>

== [[Urusergi]] version ==

No magic numbers here.

<pre>
di ; v3.1 -> 30 bytes!
ld bc,#BCFF
out (c),c
out (c),0 ; db #ED,#71
ld a,c

loop:
out (c),a
ld h,a ; h = 7654 3210
add hl,hl ; h = 6543 210*
rra ; a = 7765 4321
add hl,hl ; h = 5432 10**
xor h:and #F7:xor h ; a = 7765 1321
ld l,a ; l = 7765 1321
ld a,h ; a = 5432 10**
rla ; a = 4321 0***
and #88:xor l ; a = (7 xor 4)765 (1 xor 0)321
cp c
jr nz,loop

ei
ret
</pre>

== [[Longshot]] version ==

Interleave keys here
28 bytes - 349 nops

<pre>
Asic_Unlock
ld de,#533e ; interleave key 32 bits
ld hl,#849 ; interleave key (#841 to lock)
ld a,#ff
ld bc,#bcef ; crtc input io address and 1st nibbles
out (c),a ; RQ00 <>0
out (c),0 ; defb #ed,#71 ; Send 00 (out (c),0
Asic_Unlock_Loop:
out (c),a ; Send 2 nibbles
xor h ; Put bit 12 of the key in the bit 4 of A for high nibble
and c ; erase bit 4 to put key bit instead
xor h
adc hl,hl ; Extract left incoming bit of high nibble of interleave key
ret z ; exit when key is empty (extra value sent to io address)
ex de,hl ; Switch the interleave key (add hl,hl is good for you)
rra ; Bit 7 high nibble=Cf and rotate the complete byte
add hl,hl ; Extract left incoming bit of low nibble of interleave key
jr Asic_Unlock_Loop ; Send at last 18 values to crtc input io address
</pre>

== Algorithm ==

<pre>
def unlock_asic():
b, c = 0xBC, 0xFF
out(b, c)
out(b, 0)
a = c

while True:
out(b, a)
# a = (7 xor 4)765 (1 xor 0)321
a = ((a >> 1) & 0x77) | ((a ^ (a << 3)) & 0x80) | (((a << 2) ^ (a << 3)) & 0x08)
if a == c: break

def out(port, value):
print(f"Port: {hex(port)}xx Out: {hex(value)}")

unlock_asic()
</pre>

 

= Visual representation =

As one may see, the nybbles in the sequence are based on two 4bit shift registers.

[[File:AsicUnlockSequence.png]]

Visual by [[Hwikaa]]

 

= Patent =
For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.

On the [[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, it is precised at §2.11 "Locking of enhanced features":
<code>
it should be noted that unauthorised use of this mechanism may infringe Amstrad's patent.
</code>

According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
 

[[Category:Programming]]
[[Category:CPC Plus]]

Programming:Unlocking ASIC

2025-11-21T19:19:29Z

Longshot: Another algorithm

To unlock the [[ASIC]], a 17-byte "unlock" sequence must be sent to the [[CRTC]]'s selection port (&BC00) :
RQ00, 0, 255, 119, 179, 81, 168, 212, 98, 57, 156, 70, 43, 21, 138, STATE, <ACQ>
* RQ00 must be different from the value 0.
* STATE=205 for UNLOCK otherwise another value for LOCK.
* ACQ represents sending any value if STATE=205 (not needed otherwise).

Note: the ASIC is already unlocked after the STATE phase, before ACQ. So ACQ is actually never needed.

Once the ASIC is unlocked, we get access to a new [[Gate Array]] register called RMR2. It is accessible in the same way as other Gate Array registers.

Locking the ASIC again doesn't disable any of its functionality, it just prevents you changing it. [https://www.cpcwiki.eu/forum/programming/asm-source-code/msg249856/#msg249856 Source]

 

= BASIC version =
<pre>
10 RESTORE
20 FOR x=0 TO 16:READ a:OUT &BC00,a:NEXT
30 DATA 255,0,255,119,179,81,168,212,98,57,156,70,43,21,138,205,238
40 PRINT"ASIC unlocked!"
</pre>

 

= Z80 Assembler version =
<pre>
;; This example shows how to unlock the ASIC
;;
;; This example is designed for CPC+ only and will
;; not work on CPC or KC Compact.
;;
;; This example will compile with the MAXAM assembler
;; or the built-in assembler of WinAPE32.

org &8000

;;--------------------------------------------------
;; Unlock CPC+ additional features

di
ld b,&bc
ld hl,sequence
ld e,17

.seq
ld a,(hl)
out (c),a
inc hl
dec e
jr nz,seq

ei
ret

;;----------------------------------------------------------
;; this is the sequence to unlock the ASIC extra features
.sequence
defb &ff,&00,&ff,&77,&b3,&51,&a8,&d4,&62,&39,&9c,&46,&2b,&15,&8a,&cd,&ee
</pre>

 

= Optimized versions =

The unlocking sequence can be reconstituted from simple bit operations instead of being stored in memory.

== [[Madram]] version ==

It still uses some magic numbers.

<pre>
di
ld bc,#BCFF
out (c),c
out (c),0
ld hl,%1001000011101010

loop:
out (c),c
ld a,h:rlca:ld h,l:ld l,a
srl c
xor c:and #88:xor c
ld c,a
cp #4D
jr nz,loop

ld a,#CD ; a = #CD for unlock, another value for lock
out (c),a:out (c),a
ei
ret
</pre>

== [[Urusergi]] version ==

No magic numbers here.

<pre>
di ; v3.1 -> 30 bytes!
ld bc,#BCFF
out (c),c
out (c),0 ; db #ED,#71
ld a,c

loop:
out (c),a
ld h,a ; h = 7654 3210
add hl,hl ; h = 6543 210*
rra ; a = 7765 4321
add hl,hl ; h = 5432 10**
xor h:and #F7:xor h ; a = 7765 1321
ld l,a ; l = 7765 1321
ld a,h ; a = 5432 10**
rla ; a = 4321 0***
and #88:xor l ; a = (7 xor 4)765 (1 xor 0)321
cp c
jr nz,loop

ei
ret
</pre>

== [[Longshot]] version ==

Interleave keys here
28 bytes - 349 nops

<pre>
Asic_Unlock
ld de,#533e ; interleave key 32 bits
ld hl,#849 ; interleave key (#841 to lock)
ld a,#ff
ld bc,#bcef ; crtc input io address and 1st nibbles
out (c),a ; RQ00 <>0
out (c),0 ; defb #ed,#71 ; Send 00 (out (c),0
Asic_Unlock_Loop:
out (c),a ; Send 2 nibbles
xor h ; Put bit 12 of the key in the bit 4 of A for high nibble
and c ; erase bit 4 to put key bit instead
xor h
adc hl,hl ; Extract left incoming bit of high nibble of interleave key
ret z ; exit when key is empty (extra value sent to io address)
ex de,hl ; Switch the interleave key (add hl,hl is good for you)
rra ; Bit 7 high nibble=Cf and rotate the complete byte
add hl,hl ; Extract left incoming bit of low nibble of interleave key
jr Asic_Unlock_Loop ; Send at last 20 values to crtc input io address
</pre>

== Algorithm ==

<pre>
def unlock_asic():
b, c = 0xBC, 0xFF
out(b, c)
out(b, 0)
a = c

while True:
out(b, a)
# a = (7 xor 4)765 (1 xor 0)321
a = ((a >> 1) & 0x77) | ((a ^ (a << 3)) & 0x80) | (((a << 2) ^ (a << 3)) & 0x08)
if a == c: break

def out(port, value):
print(f"Port: {hex(port)}xx Out: {hex(value)}")

unlock_asic()
</pre>

 

= Visual representation =

As one may see, the nybbles in the sequence are based on two 4bit shift registers.

[[File:AsicUnlockSequence.png]]

Visual by [[Hwikaa]]

 

= Patent =
For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.

On the [[Original Arnold V Specs]] - Issue 1.5 - 10th April 1990, it is precised at §2.11 "Locking of enhanced features":
<code>
it should be noted that unauthorised use of this mechanism may infringe Amstrad's patent.
</code>

According to [https://patents.google.com/patent/GB2243701A/en Google patents for GB2243701A] the patent was withdrawn on 1994-12-21. This means that this particular patent cannot be enforced.
 

[[Category:Programming]]
[[Category:CPC Plus]]

Amspirit

2025-07-10T20:32:12Z

Longshot:

Amspirit is a highly precise emulator of the Amstrad CPC range (CPC464, CPC664, CPC6128, CPC464+, CPC6128+) and GX4000 console. The project has been started in 2017 and is still in progress. It relies on a lone developer, [[DManu78]].
The main point of the emulator is it's emulating the CPC at the frequency of 16 MHZ, thus being able to emulate the Gate Array to the cycle level (To the opposite of all other Amstrad CPC emulators, which are more coarse and emulate at a frequency of only 1 MHz). The aim of [[Dmanu78]] is to emulate every little bug or side effect of the real hardware.

Some portions of Amspirit have been developed in conjunction with [[Longshot]] while he was writing his [[Compendium]]. Modified versions of Amspirit have been used to test some theories when writing the document. Even if Longshot didn't took part in Amspirit's development, the emulator benefited from the research for the Compendium, as well as the Compendium from Amspirit.

In 2025 Amspirit is the most accurate Amstrad CPC emulator on the [[Z80]], [[CRTC]] (types 0,1,2,3,4) and [[Gate Array]] or [[Asic]]. [[FDC]], [[AY]] and [[8255 PPI chip|PPI]] were less worked on, by lack of testing tools and documentation. It passes almost every [[The Logon Shaker|Shaker]] tests. This makes it the best choice when one needs a robust test platform when developing Amstrad CPC programs on a PC.

== Links ==
* [https://www.amspirit.fr/ The Website of Amspirit]
* [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535 A thread on System-cfg where DManu78 tells about the development process]
* [https://thecheshirec.at/2023/11/26/fatmag-2-confirme-que-lemulation-crtc-de-amspirit-est-au-top/ A program tries to make people believe Amspirit CRTC Emulation is buggy]

Amspirit

2025-07-10T20:30:22Z

Longshot: Crtc 3 emulation available

Amspirit is a highly precise emulator of the Amstrad CPC range (CPC464, CPC664 and CPC6128). The project has been started in 2017 and is still in progress. It relies on a lone developer, [[DManu78]].
The main point of the emulator is it's emulating the CPC at the frequency of 16 MHZ, thus being able to emulate the Gate Array to the cycle level (To the opposite of all other Amstrad CPC emulators, which are more coarse and emulate at a frequency of only 1 MHz). The aim of [[Dmanu78]] is to emulate every little bug or side effect of the real hardware.

Some portions of Amspirit have been developed in conjunction with [[Longshot]] while he was writing his [[Compendium]]. Modified versions of Amspirit have been used to test some theories when writing the document. Even if Longshot didn't took part in Amspirit's development, the emulator benefited from the research for the Compendium, as well as the Compendium from Amspirit.

In 2025 Amspirit is the most accurate Amstrad CPC emulator on the [[Z80]], [[CRTC]] (types 0,1,2,3,4) and [[Gate Array]] or [[Asic]]. [[FDC]], [[AY]] and [[8255 PPI chip|PPI]] were less worked on, by lack of testing tools and documentation. It passes almost every [[The Logon Shaker|Shaker]] tests. This makes it the best choice when one needs a robust test platform when developing Amstrad CPC programs on a PC.

== Links ==
* [https://www.amspirit.fr/ The Website of Amspirit]
* [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535 A thread on System-cfg where DManu78 tells about the development process]
* [https://thecheshirec.at/2023/11/26/fatmag-2-confirme-que-lemulation-crtc-de-amspirit-est-au-top/ A program tries to make people believe Amspirit CRTC Emulation is buggy]

Emulators

2025-07-05T17:07:15Z

Longshot: Amspirit new major version

[https://www.cpcwiki.eu/forum/emulators/which-emulator-s-do-you-use/ Vote for your favorite emulator] Poll on CPCWiki forum

[[Emulator evaluation tools]] Software list for evaluating CPC emulator accuracy

[[Emulator tooling]] UI screenshots of tooling in CPC emulators

 

= Software Platforms (Full OS independance) =

=== Java Platform ===

{| class="wikitable sortable"
! Emulator name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[Arnold Jnr|Arnold Jnr]]
| [https://web.archive.org/web/20160727011826/http://www.arnoldemu.freeserve.co.uk/]
|
| Aug 27, 2001
| ❌
| ❌
| -
| Open source
|-
| [[JavaCPC|JavaCPC Desktop]]
| [https://sourceforge.net/projects/javacpc/] [http://sourceforge.net/projects/javagx4000/ JavaGX4000] [http://sourceforge.net/projects/cpcinajar/ CPCInAJar]
| 3.0.2
| Apr 8, 2022
| ✅
| ✅
| [[KC Compact]]
| Donationware & Open source
|-
| [[JEMU|JEMU]]
| [http://jemu.winape.net/]
|
| Feb 19, 2007
| ❌
| ❌
| [[ZX Spectrum]], [[ZX80/81]], [[BBC Micro]], [[VZ-300]]
| Open source
|-
| [[WebCPC|WebCPC]]
| [http://sourceforge.net/projects/webcpc/] [https://web.archive.org/web/20110903132520/http://java.cpc-live.com/ JavaCPC Applet]
| r15
| Dec 31, 2010
| ❌
| ❌
| -
| Open source
|}

Note: Java applets have been discontinued and removed in all major web browsers. So JEMU and WebCPC could belong to the "Discontinued OS" part of this article. But with [https://libgdx.com/ libGDX] and a bit of work, they could make their Java emulators work on browsers again.

=== JS / Wasm / Web Platform ===

{| class="wikitable sortable"
|-
! Emulator name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[CPCBox|CPCBox]]
| [https://www.retroshowcase.gr/cpcbox-master/] [https://web.archive.org/web/20190702084943/http://www.cpcbox.com/] [https://bzhgames.xyz/index.php BZH Games]
| beta
| Dec 28, 2013
| ❌
| ❌
| -
| Freeware
|-
| [[CrocoDS|CrocoDS]]
| [https://crocods.org/web/] [https://github.com/redbug26/crocods Repo]
|
| Jun 9, 2020
| ⚠️
| ❌
| -
| Open source
|-
| [[MAME|Emularity (MAME)]]
| [https://github.com/db48x/emularity] [http://jsmess.textfiles.com/ JSMESS] [https://classicreload.com/platform/amstrad%20cpc Classic Reload]
[https://archive.org/details/softwarelibrary_cpc Internet Archive CPC Software Library]
|
| Jan 27, 2024
| ❌
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|-
| [[Roland javascript emulator|Roland]]
| [https://web.archive.org/web/20190308142014/http://roland.retrolandia.net/] [https://www.juegotk.com/emulador-online/2/amstrad-cpc464.html JuegoTk]
|
| Sep 24, 2011
| ❌
| ❌
| -
| Open source
|-
| [[Ronald|Ronald]]
| [https://ronald.int82.dev] [https://github.com/mdm/ronald Repo]
|
| Apr 1, 2024
| ⚠️
| ❌
| -
| Open source
|-
| [[RVMplayer|RVMplayer]]
| [https://www.retrovirtualmachine.org/rvmplayer/] [https://www.amstradcpc.es/doku.php?id=emus Amstrad ESP] [https://amstradpower.es/juega-online/ Juega Online]
| 0.1.1
| May 6, 2023
| ❌
| ❌
| [[ZX Spectrum]]
| Freeware
|-
| [[Tiny Emus]]
| [https://floooh.github.io/tiny8bit/] [https://floooh.github.io/tiny8bit/cpc-ui.html CPC UI] [http://floooh.github.io/virtualkc/ yakc] [http://cpc.novidee.com/ zpz] [https://devilmarkus.de/ WebGL 3d 8-bit] [https://youfiles.herokuapp.com/pcemulator/ PC Classic Games]
[https://www.sean.co.uk/books/amstrad/index.shtm Sean's CPC Games] [https://online.oldgames.sk/play/cpc Online OldGames] [https://bzhgames.xyz/amstrad.php BZH Games]

[https://acpc.me/index.php?language=eng Arcade Room acpc.me] [https://www.amstradcpcgames.eu/ Amstrad CPC Games]
|
| Jan 6, 2025
| ✅
| ❌
| [[KC Compact]], [[ZX Spectrum]], [[VIC-20]], [[Commodore 64]], [[Acorn Atom]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]], [[LC80]]
| Open source
|-
| [[Griffin CPC emulator|Xiragon]]
| [https://web.archive.org/web/20191027200008/http://xiragon.com/]
|
| Nov 28, 2012
| ❌
| ❌
| -
| Open source
|}

=== [https://docs.libretro.com/start/understanding/ Libretro] (API for emulators) ===

{| class="wikitable sortable"
! Core name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[CaPriCe|libretro-cap32]]
| [https://github.com/libretro/libretro-cap32]
| 4.5.4
| Dec 18, 2023
| -
| ✅
| -
| Open source
|-
| [[CrocoDS|libretro-crocods]]
| [https://github.com/libretro/libretro-crocods]
|
| Oct 16, 2024
| -
| ❌
| -
| Open source
|-
| [[MAME|LRMAME]]
| [https://github.com/libretro/mame]
| 0.277
| Apr 30, 2025
| -
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|-
| [[SugarBox|SugarLibRetro]]
| [https://github.com/Tom1975/SugarLibRetro] (wraps independent lib [https://github.com/Tom1975/CPCCore CPCCore])
| git
| Jan 10, 2020
| -
| ✅
| -
| Open source
|}

Several frontends exist for Libretro: [https://www.emuvr.net/ EmuVR], [https://github.com/leiradel/hackable-console Hackable Console], [https://ludo.libretro.com/ Ludo], [https://github.com/shauninman/MinUI MinUI], [https://www.retroarch.com/ RetroArch], etc...

And several distributions exist based on RetroArch: [https://www.retrobat.org/ RetroBat], [https://www.lakka.tv/ Lakka], [https://retropie.org.uk/ RetroPie], [https://batocera.org/ Batocera], [https://www.recalbox.com/ Recalbox], etc...

 

= Operating Systems =

=== Desktop ===

{| class="wikitable sortable"
! Emulator name
! External link
! Windows
! macOS
! Linux
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[ACE_(Emulator)|ACE]]
| [http://ace.cpcscene.net MorphOS and Haiku] [https://web.libera.chat/#cpc-fr IRC chan] [https://framagit.org/search?search=acepansion Repo]
| ❌
| ❌
| ❌
| 1.26
| Jan 1, 2024
| ✅
| ✅
| Dozens of CPC hardware expansions thru plugins
| Freeware (plugins are Open Source)
|-
| [[ACE-DL]]
| [http://www.roudoudou.com/ACE-DL] [https://discord.gg/rKxFPndHPw Discord] [http://ace.cpcscene.net Based on ACE]
| ✅
| ✅
| ❗
| MayLeven
| May 11, 2025
| ✅
| ✅
| -
| Freeware
|-
| [[Amspirit|AMSpiriT]]
| [https://www.amspirit.fr/] [https://discord.com/invite/g37me8WMW6 Discord] [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535 Forum]
| ✅
| ❌
| ❌
| v2 rc1
| Jul 3, 2025
| ❌
| ✅
| -
| Freeware
|-
| [[Arnimedes|Arnimedes]]
| [http://www.arnimedes.de/]
| ✅
| ❌
| ❌
| 1.02
| Jul 7, 2012
| ❌
| ❌
| -
| Freeware
|-
| [[Arnold_(Emulator)|Arnold]]
| [https://cpcrulez.fr/emulateurs_download-WIN-arnold.htm] [https://www.cpcwiki.eu/forum/emulators/another-version-of-arnold-emulator/ Aeliss fork] [http://www.yasara.org/cpc/ Arnold TNG]
[https://web.archive.org/web/20191023094109/https://www.bannister.org/software/arnold.htm macOS] [http://hirudov.com/amiga/Arnold.php AmigaOS PPC]
| ✅
| ✅
| 🛠️
|
| May 13, 2017
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]]
| Open source
|-
| [[Caprice Forever]]
| [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
| ✅
| ❌
| ❌
| 25.5
| May 4, 2025
| ✅
| ✅
| -
| Open source
|-
| [[CaPriCe|Caprice32]]
| [https://github.com/ColinPitrat/caprice32/releases] [http://sourceforge.net/projects/caprice32/ Old repo] [https://snapcraft.io/caprice32 Linux] [https://code.google.com/archive/p/cpcsdk/ Reloaded]
[https://github.com/kletellier/cpc4rpi Cpc4Rpi] [https://github.com/KaosOverride/CapriceRPI CapriceRPI] [https://www.arananet.net/cpc-pi/ CPC-PI]
| ✅
| ✅
| ✅
| 4.6.0
| Feb 14, 2025
| ⚠️
| ✅
| [http://aleste520.narod.ru/caprice.html Aleste 520EX]
| Donationware & Open source
|-
| [[Clock Signal|Clock Signal]]
| [https://github.com/TomHarte/CLK/releases] [https://snapcraft.io/clock-signal Linux] [https://snapcraft.io/install/clock-signal/raspbian Raspberry Pi]
| ❌
| ✅
| ✅
|
| Mar 20, 2025
| ❌
| ❌
| [[ZX Spectrum]], [[ZX80/81]], [[Enterprise]], [[MSX|MSX 1&2]], [[Oric 1/Atmos|Oric]], [[ColecoVision]], [[Apple II]], [[VIC-20]], [[Atari 2600]], [[Atari ST]], [[Acorn Electron|Electron]], [[Archimedes]], [[Macintosh]], [[Master System]]
| Donationware & Open source
|-
| [[CoPaCabana|CoPaCabana]]
| [http://copacabana.emuunlim.com/]
| ✅
| ❌
| ❌
| 0.74
| Apr 12, 2006
| ⚠️
| ❌
| -
| Donationware
|-
| [[CPC++|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| ✅
| ✅
| ❗
| b700
| May 31, 2015
| ❌
| ❌
| -
| Freeware
|-
| [[cpc4x|cpc4x]]
| [http://www.ulrich-cordes.de/cpc/english/cpcemu.htm]
| ❌
| ❌
| 🛠️
| 0.26
| Dec 11, 2004
| ❌
| ❌
| -
| Open source
|-
| [[CPCEC|CPCEC]]
| [http://cngsoft.no-ip.org/cpcec.htm] [https://github.com/cpcitor/cpcec Repo] [http://cngsoft.no-ip.org/ CPCE] [https://github.com/AmatCoder/CPCEG CPCEG]
| ✅
| 🛠️
| 🛠️
|
| Apr 27, 2025
| ⚠️
| ✅
| [[ZX Spectrum]], [[Commodore 64]], [[MSX|MSX 1&2]]
| Open source
|-
| [[CPCEC|cpcec-gtk]]
| [https://bitbucket.org/norecess464/cpcec-gtk/]
| ❌
| ❌
| 🛠️
|
| Feb 4, 2023
| ✅
| ✅
| -
| Open source
|-
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| ✅
| ✅
| ✅
| 3.0.2
| Apr 24, 2025
| ✅
| ❌
| -
| Freeware
|-
| [[CPCEPower|CPCEPower]]
| [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
| ✅
| ✅
| ✅
| 2105
| Jun 4, 2021
| ❌
| ✅
| -
| Donationware
|-
| [[CPCSharp|CPCSharp]]
| [https://github.com/dolbz/CPCSharp/releases/]
| ✅
| ✅
| ❌
| 1.0.0-beta1
| Apr 7, 2021
| ⚠️
| ❌
| -
| Open source
|-
| [[CPvC|CPvC]]
| [https://github.com/alybaek2/cpvc]
| ✅
| ❌
| ❌
|
| Sep 30, 2022
| ❌
| ❌
| -
| Open source
|-
| [[CrocoDS|CrocoDS]]
| [https://crazypiri.eu/crocods/] [https://github.com/redbug26/crocods Repo]
| ✅
| ✅
| ❌
| 4.0 beta3
| Dec 10, 2023
| ⚠️
| ❌
| -
| Open source
|-
| [[DSP|DSP]]
| [https://github.com/leniad/dsp-emulator/]
| ✅
| ✅
| 🛠️
| 0.24wip1
| Apr 30, 2025
| ❌
| ❌
| [[ZX Spectrum]], [[Commodore 64]], [[Oric 1/Atmos|Oric]], [[ColecoVision]], [[Game Boy]], [[NES]], [[SG-1000]], [[Master System]], [[Game Gear]], [[Super Cassette Vision]], [[PV-1000]], [[PV-2000]], [[Arcade]]
| Open source
|-
| [[ep128emu|ep128emu]]
| [https://github.com/istvan-v/ep128emu]
| ✅
| 🛠️
| 🛠️
| 2.0.11.2
| Apr 19, 2019
| ⚠️
| ❌
| [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
|-
| [[Gemux|Gemux]]
| [https://www.cpcwiki.eu/forum/emulators/gemux-cpc/]
| ✅
| ❌
| ❗
|
| Nov 5, 2024
| ❌
| ❌
| -
| Freeware
|-
| [[MESS|MAME]]
| [http://mamedev.org] [http://se.os4depot.net/index.php?function=showfile&file=emulation/computer/sdl_mess.lha AmigaOS PPC] [http://fabportnawak.free.fr/mame/ MorphOS] [https://depot.haiku-os.org/#!/pkg/mame Haiku]
[https://github.com/AntoPISA/MAME_SupportFiles Support Files] [https://auamstrad.es/software/mame-emulador-de-amstrad-cpc/ Tutorial (ES)]
| ✅
| ✅
| ✅
| 0.277
| Apr 30, 2025
| ⚠️
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|-
| [[NO$CPC|NO$CPC]]
| [http://problemkaputt.de/cpc.htm]
| ✅
| ❌
| ❌
| 1.8
| Nov 2, 2000
| ⚠️
| ✅
| -
| Donationware
|-
| [[PC-CPC|PC-CPC]]
| [http://cpcrulez.fr/emulateurs_download-WIN-PC-CPC.htm] [https://github.com/DemoniakLudo/PC-CPC Repo]
| ✅
| ❌
| ❌
| 0.1at b29
| Nov 17, 2011
| ⚠️
| ❌
| -
| Open source
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| [https://www.retrovirtualmachine.org]
| ✅
| ✅
| ✅
| 2.1.19
| Dec 9, 2024
| ❌ Removed
| ✅
| [[ZX Spectrum]], [[MSX|MSX 1]], [[ColecoVision]], [[SG-1000]], [[Master System]]
| Donationware
|-
| [[Roland Emulator|Roland]]
| [https://www.rolandemu.de/en/downloads.html] [https://github.com/raldus/roland Repo]
| ✅
| ❌
| 🛠️
| 0.70
| Apr 20, 2017
| ❌
| ❌
| -
| Open source
|-
| [[Ronald|Ronald]]
| [https://github.com/mdm/ronald]
| ❌
| ❌
| 🛠️
|
| Apr 1, 2024
| ⚠️
| ❌
| -
| Open source
|-
| [[SugarBox|SugarBox]]
| [https://github.com/Tom1975/SugarboxV2] [http://sugarbox.free.fr/ Old site] [https://github.com/Tom1975/SugarPi SugarPi]
| ✅
| ✅
| ✅
| 2.0.4
| Nov 24, 2024
| ⚠️
| ✅
| -
| Open source
|-
| [[VirtualCPC|Virtual CPC]]
| [https://cpcrulez.fr/emulateurs_download-WIN-virtual_cpc.htm] [https://web.archive.org/web/20200112094913/http://users.otenet.gr/~sulfonic/cpc/ Archive]
| ✅
| ❌
| ❌
| 1.1
| Aug 8, 2011
| ⚠️
| ❌
| -
| Freeware
|-
| [[WinApe|WinAPE]]
| [http://www.winape.net/] [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPCWIN10.ZIP CPCwin]
| ✅
| ❌
| ❌
| 2.0b2
| Jan 5, 2016
| ✅
| ✅
| -
| Donationware
|-
| [[WinCPC|WinCPC]] / [[MacCPC|MacCPC]]
| [http://www.wincpc.ch/index.php?topic=projects] [https://web.archive.org/web/20050409133618/http://www.easypoint.ch/vbcpc/ vbCPC]
| ✅
| ✅
| ❌
| 0.9.2
| Jan 22, 2010
| ✅
| ❌
| -
| Freeware
|-
| [[XCPC|Xcpc]]
| [https://www.xcpc-emulator.net/] [https://github.com/ponceto/xcpc-emulator Repo]
| ❌
| ❌
| ✅
| 0.52.1
| Sep 8, 2024
| ❌
| ❌
| -
| Open source
|-
| [[XNACPC|XNACPC]]
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/] [https://www.gavpugh.com/old-code/ CPC3D]
| ✅
| ❌
| ❌
| 1.0
| Nov 11, 2011
| ❌
| ❌
| -
| Open source
|-
| [[ZEsarUX|ZEsarUX]]
| [https://github.com/chernandezba/zesarux] [https://depot.haiku-os.org/#!/pkg/zesarux Haiku]
| ✅
| ✅
| ✅
| 12.0
| Jan 16, 2025
| ⚠️
| ❌
| [[PCW]], [[ZX Spectrum]], [[ZX80/81]], [[MSX|MSX 1]], [[ColecoVision]], [[Spectravideo]], [[Jupiter ACE]], [[Sam Coupe]], [[SG-1000]], [[Master System]], [[Sinclair QL]], [[MK14]], [[Z88]]
| Donationware & Open source
|}

Legend: ❗= No Raspberry Pi / ARM build ; 🛠️ = Build it yourself ; ⚠️ = Incomplete tooling

=== Mobile ===

You can use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on '''Android and iOS'''. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Android
| [[andcpc]]
| [http://code.google.com/p/andcpc/]
| 1.5.1
| Apr 4, 2011
| ❌
| -
| Open source
|-
| Android
| [[Azimuth]]
| [https://play.google.com/store/apps/details?id=johnidis.azimuth]
| 1.20
| Feb 7, 2025
| ❌
| -
| Adware and in-app purchases💲
|-
| Android
| [[CPCDroid]]
| [https://fmsdevel.wisecoding.es/cpcdroid-amstrad-cpc-on-android-phone-2/]
| 1.5.1
| Mar 2, 2011
| ❌
| -
| Open source
|-
| Android
| [[CPCemu|CPCemu]]
| [https://cpc-emu.org/]
| 3.0.2
| Apr 24, 2025
| ❌
| -
| Freeware
|-
| Android
| [[Droid-CPC]]
| [http://play.google.com/store/apps/details?id=com.kokak.droidcpc]
| 1.1.01
| Dec 15, 2016
| ❌
| -
| Commercial💲
|-
| Android
| [[MAME4droid Current]]
| [http://play.google.com/store/apps/details?id=com.seleuco.mame4d2024] [https://github.com/seleuco/MAME4droid-2024 Repo]
| 1.24 (0.277)
| May 2, 2025
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|-
| iOS
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| 3.0.2
| May 11, 2025
| ❌
| -
| Freeware
|-
| iOS
| [[CrocoDS]]
| [https://crazypiri.eu/crocods/] [https://github.com/redbug26/crocods-ios Repo]
| 2.1
| Jun 21, 2013
| ❌
| -
| Open source
|-
| iOS
| [[MAME4iOS]]
| [https://github.com/yoshisuga/MAME4iOS]
| 2022.5
| Dec 12, 2022
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|}

=== Discontinued OS ===

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Acorn RISC OS
| [[!CPC|!CPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPC0728.ZIP] [http://ftp2.fr.openbsd.org/ftp/pub/amstrad/emulator/CPCS1124.ZIP]
|
| Jul 28, 1996
| ❌
| -
| Open source
|-
| Acorn RISC OS
| [[!CPCemu|!CPCemu]]
| [http://huggers-world.de/mops.html]
| 1.21
| Mar 22, 2016
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[A-CPC|A-CPC]]
| [https://cpctech.cpcwiki.de/download/a-cpc.lha]
| 2.0
| Mar 30, 2002
| ✅
| -
| Open source
|-
| AmigaOS m68k
| [[Ami-cpc|Ami-cpc]]
| [http://deplanque.chez.com/] [http://deplanque.chez.com/download_fr.html Ami-cpc2]
| 0.46
| Jan 21, 1998
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[CPE|CPE]]
| [https://cpcrulez.fr/emulateurs_download-AMIGA-CPE.htm]
|
| Feb 24, 1995
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[Emu-CPC|EmuCPC]]
| [https://cpcrulez.fr/emulateurs_download-AMIGA-emucpc.htm]
| 0.7
| Sep 15, 1996
| ❌
| -
| Open source
|-
| AROS
| [[Arnold]]
| [http://archives.aros-exec.org/?function=showfile&file=emulation/computer/arnold-aros-i386.lha]
|
| Oct 24, 2010
| ✅
| -
| Open source
|-
| AROS
| [[Caprice32]]
| [http://archives.aros-exec.org/?function=showfile&file=emulation/computer/caprice-aros-i386.lha]
| 4.2.0
| Oct 23, 2010
| ❌
| -
| Open source
|-
| BlackBerry OS
| [[BB-CPC|BB-CPC]]
| [http://appworld.blackberry.com/webstore/content/30963891/] (dead link)
| 1.0.1.3
| Jul 15, 2013
| ❌
| -
| Commercial💲
|-
| Classic Mac OS
| [[CPCplusplus|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| 1.3.2
| Oct 6, 1997
| ❌
| -
| Shareware💲
|-
| DOS
| [[AdvanceMESS|AdvanceMESS]]
| [https://www.advancemame.it/readme]
| 3.9
| Sep 8, 2018
| ✅
| Tons of vintage computers and game consoles
| Open source
|-
| DOS
| [[Arnimedes|Arnimedes]]
| [http://www.arnimedes.de/]
| 0.8a
| Apr 15, 2000
| ❌
| -
| Freeware
|-
| DOS
| [[Caprice32]]
| [https://ftp.nvg.ntnu.no/pub/cpc/emulator/msdos/capriced.zip]
| 1.11
| Sep 20, 1999
| ❌
| -
| Open source
|-
| DOS
| [[CPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPC055B.ZIP]
| 0.55b
| May 16, 1997
| ❌
| -
| Freeware
|-
| DOS
| [[CPC-em|CPC-em]]
| [http://cpc-em.emuunlim.com/]
| 0.4
| Jul 7, 2004
| ❌
| -
| Open source
|-
| DOS
| [[CPCE|CPCE]]
| [http://cngsoft.no-ip.org/cpce/]
| 1.94
| Jun 2, 2011
| ❌
| -
| Freeware
|-
| DOS
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| 1.5
| Jul 7, 1998
| ❌
| -
| Freeware
|-
| DOS
| [[CPE|CPE]]
| [https://cpcrulez.fr/emulateurs_download-DOS-CPE.htm]
| 5.2
| Apr 21, 1997
| ❌
| -
| Open source
|-
| DOS
| [[NO$CPC|NO$CPC]]
| [http://problemkaputt.de/cpc.htm]
| 1.8
| Nov 2, 2000
| ✅
| -
| Freeware
|-
| DOS
| [[PC-CPC|PC-CPC]]
| [http://deplanque.chez.com/download_fr.html]
|
| Feb 3, 1998
| ❌
| -
| Open source
|-
| DOS
| [[CPCEMU (RWCPC)|RWCPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/RWCPC.ZIP]
|
| Mar 23, 1995
| ❌
| -
| Freeware
|-
| DOS
| [[SIMCPC|SIMCPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/SIMCPC.ZIP]
|
| Dec 10, 1989
| ❌
| -
| Shareware💲
|-
| DOS
| [[YAGE|YAGE]]
| [https://www.zophar.net/cpc/yage.html]
| 0.91
| Oct 24, 1998
| ❌
| -
| Freeware
|-
| EXOS
| [[Software CPC Emulator|Software CPC Emulator]]
| [http://www.ep128.hu/Ep_Util/Prg/Amstrad_CPC_Emulator_13.rar] [http://www.ep128.hu/Ep_Util/Amstrad_CPC_emu.htm]
| 1.3
| Jan 11, 2013
| ❌
| -
| Open source
|-
| Maemo
| [[CPCm]]
| [http://maemo.org/downloads/product/Maemo5/cpcm/]
| 1.20-1
| Apr 27, 2010
| ❌
| -
| Open source
|-
| MSX-DOS
| [[EMU6CPC|EMU6CPC]]
| [http://romu6.blogspot.com/2018/12/emu6cpc-emulador-de-amstrad-cpc-6128.html]
|
| Dec 17, 2018
| ❌
| -
| Freeware
|-
| OS/2
| [[SDLMAME|SDLMAME]]
| [https://ecsoft2.org/sdlmame]
| 0.170
| Jan 30, 2016
| ✅
| Tons of vintage computers, game consoles and arcade systems
| Open source
|-
| Palm OS
| [[CaPriCe for Palm OS|CaPriCe for Palm OS]]
| [http://coste.frederic.free.fr/cpc/cpc_en.htm]
| 2.8
| Jun 28, 2011
| ❌
| -
| Open source
|-
| Palm OS
| [[CoPaCabana|CoPaCabana]]
| [http://copacabana.emuunlim.com/]
| 0.75
| Dec 4, 2007
| ❌
| -
| Freeware
|-
| Pocket PC
| [[CaPriCe|PocketCaprice]]
| [https://web.archive.org/web/20160506010209/http://www.clubic.com/telecharger-fiche44888-pocketcaprice.html]
| 0.9
| Aug 19, 2007
| ❌
| -
| Freeware
|-
| SunOS
| [[CPCplusplus|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| 1.3.0
| Feb 22, 1997
| ❌
| -
| Shareware💲
|-
| Symbian
| [[S60-CPC|S60-CPC]]
| [http://kokak.free.fr/s60cpc.htm]
| 0.74
| Feb 21, 2006
| ❌
| -
| Open source
|-
| Windows 9x
| [[CPC-em|CPC-em]]
| [http://cpc-em.emuunlim.com/]
| 0.3
| Jan 22, 2004
| ❌
| -
| Open source
|-
| Windows 9x
| [[MTMW|MTMW]]
| [https://cpcrulez.fr/emulateurs_download-WIN-MTMW.htm]
| 1.30B
| Jan 11, 2000
| ✅
| [[ZX Spectrum]], [[ZX80/81]], [[Enterprise]], [[Jupiter ACE]]
| Freeware
|}

 

= Other Platforms =

=== Home Consoles ===

You can use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on '''Apple TV, Android TV, Nvidia Shield, Steam Link, Xbox One, Xbox Series, PS2, PS Vita TV, GameCube, Wii, Wii U and Switch'''. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Microsoft XBOX
| [[Arnold|ArnoldX]]
| [https://web.archive.org/web/20120705163939/http://forums.xbox-scene.com/index.php?showtopic=711667] [https://cpcrulez.fr/emulateurs_download-XBOX-ARNOLDX.htm]
| v5
| Apr 20, 2010
| ✅
| -
| Freeware
|-
| Microsoft XBOX
| [[CoinOPS|CoinOPS (RetroFE)]]
| [https://web.archive.org/web/20160518183115/https://coinopsproject.freeforums.org/viewtopic.php?f=0&t=1213]
| 5
| Oct 18, 2012
| ❌
| Tons of vintage computers, game consoles and arcade systems
| Freeware
|-
| Microsoft Xbox 360
| [[XNACPC|XNACPC]]
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
| 1.0
| Nov 11, 2011
| ❌
| -
| Open source
|-
| Nintendo Wii
| [[Wiituka|Wiituka]]
| [http://wiituka.dantoine.org/]
| 0.98.8
| May 15, 2009
| ❌
| -
| Open source
|-
| Sega Dreamcast
| [[CPCast|CPCast]]
| [http://www.dcemu.co.uk/vbulletin/showthread.php?t=24100]
|
| May 6, 2006
| ❌
| -
| Freeware
|-
| Sega Dreamcast
| [[DreamCPC|DreamCPC]]
| [https://www.jm1200.fr/index.php?r=2]
| Alpha 3
| Oct 16, 2005
| ❌
| -
| Freeware
|-
| Sony PS2
| [[CPC-em|CPC-em]]
| [https://cpcrulez.fr/emulateurs_download-ps2-CPC-EM.htm]
| 0.4
| Dec 22, 2004
| ❌
| -
| Freeware
|-
| Sony PS3
| [[Caprice32|Caprice32]]
| [https://web.archive.org/web/20171003153204/http://psx-scene.com/forums/content/caprice32-4-1-0-dbg-emulator-ps3-2119/]
| 4.1.0 DBG
| Apr 9, 2012
| ❌
| -
| Open source
|}

=== Handheld Consoles ===

Note: For Android handheld consoles (Razer Edge, Ayn Odin Pro, Retroid Pocket Flip, GPD XP, ...), see the Mobile/Android section.

You can use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on '''PSP, PS Vita, DS, 3DS, Switch, Steam Deck, RetroFW, Miyoo, OpenDingux, [https://muos.dev/systems/computer muOS] and [https://github.com/christianhaitian/arkos/wiki/ArkOS-Emulators-and-Ports-information ArkOS]'''. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Dingoo A320 / A330
| [[Pituka|Pituka Dingux]]
| [http://david.dantoine.org/proyecto/4/]
| 0.8pre
| Aug 19, 2010
| ❌
| -
| Open source
|-
| Dingoo A320 / A330
| [[Caprice|Dingux-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/105-Amstrad/]
| 1.1.2
| Oct 17, 2009
| ❌
| -
| Open source
|-
| GamePark Caanoo
| [[Caprice|Caanoo-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/165-Amstrad/]
| 1.1.3
| Apr 24, 2011
| ❌
| -
| Open source
|-
| GamePark GP2x
| [[Caprice|CapriceGP2x]]
| [https://web.archive.org/web/20130315195529/http://wiki.gp2x.org/wiki/CapriceGP2x]
| 0.5
| Feb 22, 2006
| ❌
| -
| Open source
|-
| GamePark GP2x
| [[Caprice|GP2X-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/42-Amstrad/]
| 1.5.1
| Aug 29, 2009
| ❌
| -
| Open source
|-
| GamePark GP32
| [[Pituka|Pituka GP32]]
| [http://david.dantoine.org/proyecto/4/]
| 1d
| May 15, 2010
| ❌
| -
| Open source
|-
| GamePark Wiz
| [[Caprice|Wiz-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/89-Amstrad/]
| 1.1.0
| Aug 29, 2009
| ❌
| -
| Open source
|-
| GCW Zero
| [[Caprice|Dingux-CAP32]]
| [https://github.com/kerheol/dingux-cap32]
| 1.1.2
| May 25, 2014
| ❌
| -
| Open source
|-
| JXD S5110 / S601 & Yinlips G18
| [[Caprice|JXD-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/206-Amstrad/]
| 1.1.1
| Oct 27, 2012
| ❌
| -
| Open source
|-
| Nintendo DS
| [[AmeDS|AmeDS]]
| [https://web.archive.org/web/20131021073302/http://www.portabledev.com/pages/ds/jeuxdev.-perso/ameds.php]
| 4.0
| Apr 25, 2010
| ❌
| -
| Freeware
|-
| Nintendo DS
| [[CrocoDS|CrocoDS]]
| [http://www.kyuran.be/blog/2007/11/09/crocods-20-2/] [https://github.com/redbug26/crocods-nds Repo]
| 2.0
| Nov 9, 2007
| ❌
| -
| Open source
|-
| Nintendo GameBoy Advance
| [[Mini Amstrad Emulator|Mini Amstrad Emulator]]
| [https://playeradvance.org/forum/showthread.php?t=765]
|
| Dec 26, 2005
| ❌
| -
| Open source
|-
| Odroid GO
| [[CapriceESP32|CapriceESP32]]
| [https://github.com/grantrismo/CapriceESP32]
|
| Dec 3, 2020
| ❌
| -
| Open source
|-
| OpenDingux
| [[CrocoDS|CrocoDS]]
| [https://crazypiri.eu/crocods/] [https://github.com/redbug26/crocods Repo]
|
| Jan 15, 2020
| ❌
| -
| Open source
|-
| Pandora
| [[Caprice|Pandora-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/131-Amstrad/]
| 1.1.0
| Jun 27, 2010
| ❌
| -
| Open source
|-
| Sony PSP
| [[Caprice32 PSP]]
| [http://psp.akop.org/caprice32]
| 4.2.0.2
| Nov 28, 2007
| ❌
| -
| Open source
|-
| Sony PSP
| [[CPCPSP|CPCPSP]]
| [https://web.archive.org/web/20130325143915/http://dl.qj.net/psp/emulators/cpcpsp-v01.html]
| 0.1
| Dec 24, 2005
| ❌
| -
| Freeware
|-
| Sony PSP
| [[PSPCAP32|PSPCAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/3-Amstrad/]
| 1.5.1
| Aug 21, 2009
| ❌
| -
| Open source
|-
| Trimui Model S
| [[Arnold|Arnold Trimui]]
| [https://github.com/liartes/arnold_gcw0]
|
| Oct 19, 2021
| ✅
| -
| Open source
|}

=== FPGA ===

*[[CPC TREX|CPC TREX]] [[C-ONE|CPC-One]] TurboCPC core by TobiFlex running on different FPGA boards
*[http://ralferoo.blogspot.fr/ CPC FPGA] CPC emulation by Ranulf (Ralferoo) Doswell, running on a custom made FPGA board
*[[FPGAmstrad|FPGAmstrad]] [https://github.com/renaudhelias/CoreAmstrad CoreAmstrad] [https://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad CoreDocAmstrad] Translation by Renaud (Freemac) Hélias of JavaCPC from Java into VHDL for MiST board
*[https://github.com/sorgelig/Amstrad_MiST CPC for MiST and MiSTer] Started by Alexey (Sorgelig) Melnikov as a port of CoreAmstrad, but every module has been either rewritten or replaced
*[https://web.archive.org/web/20230330082645/https://intelligenttoasters.blog/cpc2-project-index/ CPC2 Project] CPC emulation running on a Cyclone V FPGA board
*[https://github.com/ZXMicroJack/amstrad-cpc AmstradCPC core] Based on McLeod's core and running on a ZXTres FPGA board

 

= Upcoming =

Amstrad CPC support is in the works for [https://github.com/TASEmulators/BizHawk BizHawk] and [https://bostjan-grandovec.si/Content/Pantheon.htm Pantheon].

Pure speculation but it would make sense that [https://web.libretro.com/ RetroArch Online] and [https://ares-emu.net/ Ares] add Amstrad CPC support.

 

= Hardware Replacements =

*[https://youtu.be/DykFhtNbgGk Just CPC4ATX] [https://www.sellmyretro.com/offer/details/60734] [https://memoryfull.net/party.php?id=240 CPC-ITX triple CRTC] CPC clones made from NOS chips
*[https://github.com/Bread80/CPCModular CPC Modular] Modular Amstrad CPC compatible computer
*[https://makerworld.com/fr/models/821842#profileId-765034 Amstrad CPC464 mini] [https://github.com/Board-Folk/CPC464-2MINI CPC464-2mini] Miniaturised CPCs
*[https://hackaday.io/project/187051-the-amstrad-cpc-portable Amstrad CPC Portable] World's first battery-powered portable Amstrad CPC
*[https://www.tindie.com/search/?q=amstrad+replica+pcb CPC 464/6128 replica PCBs] To be used as a direct replacement to the original PCBs
*[https://github.com/EremusOne/CPCESP_alpha CPCESP] [https://github.com/rpsubc8/ESP32TinyCPC/ ESP32 TinyCPC] CPC emulators for ESP32 SoC board
*[https://www.symbos.org/symbosvm.htm SymbOSVM] SymbOS for modern 32/64bit hardware

=== Chips ===

*[https://github.com/MicroCoreLabs/Projects MCLZ8] [https://github.com/rejunity/z80-open-silicon z80-open-silicon] Z80 emulators to be used as drop-in replacement
*[https://github.com/nukeykt/Nuked-MD-FPGA/blob/main/z80.v Nuked-MD-FPGA] [https://github.com/gdevic/A-Z80 A-Z80] Verilog Z80 implementations reverse engineered from decapped chip
*[https://github.com/floooh/v6502r Visual Z80 Remix] [https://github.com/gdevic/Z80Explorer Z80 Explorer] Netlist-level ultra accurate Z80 simulators
*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped! Forum thread] Reverse engineered Gate Array by Gerald from decapped chips [https://pastebin.com/ZQyL68Hv Ash Evans] [https://github.com/MiSTer-devel/Amstrad_MiSTer/tree/master/rtl/GA40010 Gyorgy Szombathelyi] [https://github.com/codedchip/AMSGateArray AMSGateArray] Subsequent Verilog/VHDL implementations [https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Signals analysis by Bread80]
*[https://www.sintech-shop.de/en/retro-commodore-sinclair-atari-etc/amstrad/cpc/hardware Sintech hardware replacements] Gate Array emulator chips and keyboard membranes
*[https://lotharek.pl/productdetail.php?id=408 AY_FPGA] AY-3-8912 FPGA replacement with few extra features
*[https://k3pi.chickenkiller.com/dzi/ ASIC and Pre-ASIC] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg133264/#msg133264 Gate Array] [https://siliconpr0n.org/map/zilog/z0840008psc-z80cpu/ Z80 CPU] [https://www.seanriddle.com/6845/ HD6845SP CRTC] [http://seanriddledecap.blogspot.com/2023/12/blog-post_31.html AY-3-8912 PSG] [http://seanriddledecap.blogspot.com/2017/01/blog-post_42.html NEC D765 FDC] [https://www.pastraiser.com/pictures/8255/layers/Total.png 8255 PPI] Die shots of decapped CPC chips
*[https://github.com/veniamin-ilmer/decoding_rom Optically decode the ROM of a decapped chip] [https://github.com/travisgoodspeed/gbrom-tutorial Automate ROM decoding] [https://c128.se/posts/silicon-adventures/ Decap, image and reverse engineer the C128 PLA chip] [https://youtu.be/r8Vq5NV4Ens How I reverse engineer a chip] [https://youtu.be/KohIewYHHMY Looking at silicon] Tutorials
*[https://thecheshirec.at/2023/11/21/5-multi-crtcs-a-vendre/ Multi-CRTC Board] [https://www.pcbway.com/project/shareproject/multi_crtc_selector_for_amstrad_cpc_464_664_6128_2ca49a09.html Multi-CRTC Selector] Host and select between multiple CRTC chip types in one CPC

=== Floppy drives ===

*[[SDiskEmul]] Floppy-drive emulator released in 2007. Abandoned now. Supports DSK, EDSK disk-images
*[https://hxc2001.com/floppy_drive_emulator/ HxC Floppy Emulator] Commercial floppy-drive emulator. Supports directly DSK, EDSK, HFE disk-images. IPF, CTRAW, SCP disk-images supported through conversion to HFE disk-image [https://hxc2001.com/docs/gotek-floppy-emulator-hxc-firmware/pages/emulation-from-images.html]
*[https://github.com/keirf/flashfloppy/ FlashFloppy] Open source floppy-drive emulator for the ubiquitous Gotek hardware. Supports DSK, EDSK, HFE disk-images. Can also be bought already built: [https://www.sellmyretro.com/offer/details/zax-drive-sd-63195 Zax Drive SD] [https://www.micomputer.es/en/gotek/390-3856-emulador-usb-gotek.html Micomputer floppy emulator] [https://pixel.rodrik.ch/gotekcpc Gotek CPC 664/6128] [https://pixel.rodrik.ch/gotekcpcplus Gotek 6128 Plus]
*[https://github.com/keirf/greaseweazle GreaseWeazle] Open source USB floppy adapter Flux reader/writer
*[https://www.cbmstuff.com/index.php?route=product/product&product_id=52 SuperCard Pro] Claims to be the most advanced flux level copier/imager/converter system
*[https://kryoflux.com/ KryoFlux] Proprietary floppy adapter Flux reader/writer
*[https://cpcrulez.fr/forum/viewtopic.php?f=5&t=100&start=690#p55437 Pauline] FPGA-based floppy-drive dumper and emulator
*[https://lotharek.pl/productdetail.php?id=376 DriveRDY] Emulates the Ready signal necessary for floppy drives on Amstrad machines
*[https://cpcrulez.fr/hardware-lecteurs_externe-interface_ddi3_usb_floppy_emulator.htm DDI-3] USB floppy-drive emulator including a real FDC chip, floppy data separator and AMSDOS ROM for CPC464. Current evolution [https://www.sellmyretro.com/offer/details/64558 DDI-6] has also integrated a RAM/ROM box
*[[M4 Board]] Supports DSK, EDSK images in a limited fashion. Protected disks are not supported
*[[USIFAC]] [[ULIfAC]] Supports DSK, EDSK images in a limited fashion. Protected disks are not supported

=== Tapes ===

*[https://hobbyretro.com/en/retro/tzxduino TZXduino] [https://ultimatemister.com/product/ultimate-maxduino-pro/ MAXduino] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/abatape-my-contribution-to-tape-lovers/ Abatape] Arduino-based tape deck emulator. Supports many formats of tape-images including CDT and TZX
*[https://youtu.be/j4__v6ojPt0 SVI-CAS] Digital Tape Drive for Playback & Recording. Supports many formats of tape-images including CDT and TZX
*[https://retrowiki.es/viewtopic.php?t=200032717 TapeRider] TZX/CDT tape-images player for Android
*[https://chrome.google.com/webstore/detail/tapdancer/fcibbcbgbeioacfcnfgjianglchlcokh tapDancer] [https://web.archive.org/web/20160110003844/http://tapdancer.info/] Chrome and Android app that plays back many formats of tape-images including CDT and TZX
*[https://pelrun.github.io/PlayUEF/ PlayUEF] [https://pelrun.github.io/PlayUEF/PlayUEF.html Online version including Pelrun's CDT collection] Web-browser based tape deck emulator, supporting CDT/TZX/UEF tape-images
*[https://cdtplayer.hypha.ws/ Hypha's CDT collection and player] Web-browser based cdt/wav/flac/mp3 player

=== Cartridges ===

*[https://github.com/f1ac0/CPC-plus-cartridge CPC-plus-cartridge] Different PCB designs and code to make a CPC-plus cartridge
*[https://github.com/zeus074/Amstrad_Multicart Amstrad Multicart] 16-in-1 cartridge for the GX4000 or Amstrad Plus computer
*[https://cpcrulez.fr/hardware-interface_ROM-gx4000_homebrew_player.htm GX4000 Homebrew Player] [https://cpcrulez.fr/hardware-interface_ROM-gx4000_homebrew_player-32_in_one.htm CPC+ 32-in-one multigames] by Retroelectronik
*[[CPC_GX4000-Multi_EPROM_Cartridge|Multi-EPROM cartridge]] for CPC+/GX4000
*[[Multi Cartridge 8 ROMs]] by ETO, for GX4000 / Amstrad Plus
*[[C4CPC]] Cartridge replacement for the Amstrad Plus range and the GX4000
*[https://overange.weebly.com/amstrad-gx4000-cpc-464-6128-plus-reflashable-flash-cartridge.html Flash+ cartridge] [https://youtu.be/UDaw-nd4L9c Youtube] Amstrad CPC+ GX4000 reflashable cartridge
*[https://store.backbit.io/product/backbit-pro/ BackBit Pro] [https://youtu.be/tI2wkelVzyw Tutorial] Universal instant loading cartridge
*[[Cartridge Emulator]] Part of the [[Amsteam]] online service
*[[M4 Board]] Supports CPR cartridges, among many other features

=== Printers ===

*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/acpcpe-amstrad-cpc-printer-emulator-(diy)/ Amstrad CPC Printer Emulator] [https://github.com/lgv2018/ACPCPE] Arduino-based CPC printer emulator that can output text, markdown or HTML
*[https://www.retroprinter.com/ Retro-Printer] Plugin module for the Raspberry Pi that makes it possible to connect retro computers to modern USB or network printers
*[https://github.com/nzeemin/escparser ESCParser] Command-line utility, ESC/P printer emulator that can output PostScript, SVG or PDF

=== Other ===

*[https://simonowen.com/spectrum/lenskey/ LensKey] LensLok copy-protection decoder for Windows
*[https://github.com/ArcherEG/CPCPS2Firmware CPCPS2 Keyboard Firmware] Emulates the keyboard matrix of Amstrad CPC using modern hardware
*[https://sindenlightgun.com/ Sinden Lightgun] LCD-compatible lightgun
*[https://github.com/grzegorz-gr/vga4cpc vga4cpc] VGA output for Amstrad CPC based on Raspberry Pi Pico
*[https://pixel.rodrik.ch/mp2fj MP2F-J] [https://pixel.rodrik.ch/mp2p MP-2 Plus] Evolution of the [[Amstrad MP1/MP2 modulator|Amstrad MP-2F]] modulator
*[https://xn--multipli-i1a.fr/minimit/ Minimit] To connect your [[Minitel]] to servers as the PSTN has been retired

 

= Peripherals supported in emulators =

Note: The [[RSF3]] is mentioned in multiple places in the following list as, besides its native functionalities, it also emulates the [[M4 Board]], the [[Symbiface II]], etc...

=== Mass storage devices ===

*[[Dobbertin Harddisc]] or compatible ([[RSF3]]) is emulated by MAME and CPCemu.
*[[UIDE Universal IDE adapter cards for Z-80 computers|uIDE]] is emulated by Arnold
*[[Symbiface II]] IDE/PATA interface or compatible ([[X-Mass]], [https://github.com/salafek/cyboard-for-cpc Cyboard], [[RSF3]]) is emulated by ACE, ACE-DL, Caprice Forever, MAME, WinAPE, WinCPC, Arnold, Virtual CPC
*[[Albireo]] is partially emulated (mass storage only and no direct sector) by ACE, ACE-DL, Caprice Forever
*[[M4 Board]] or compatible ([[RSF3]]) is emulated by CPCemu
*[[Vortex Winchester Drive]], [[IDE8255|Yarek's IDE8255]], [[IDE/8255|RPalmer's IDE/8255]], [[ULIfAC]], [[RSF3|RSF3 native]], [https://hxc2001.com/download/floppy_drive_emulator/SDCard_HxC_Floppy_Emulator_Direct_Access_mode.pdf Gotek direct access mode] are not supported

=== Real Time Clock ===

*[[Dobbertin Smart Watch]] or compatible ([[Dobbertin Smart Watch|DXS RTC]]) is emulated by MAME, WinAPE
*[[Symbiface II]] RTC or compatible ([https://github.com/salafek/cyboard-for-cpc Cyboard], [[RSF3]]) is emulated by ACE-DL, MAME, WinAPE, WinCPC
*[[Nova]] is emulated by ACE, ACE-DL
*[[M4 Board]] NTP is emulated by CPCemu
*[[Dk'tronics Real Time Clock]], [[RSF3|RSF3 native]], [https://github.com/lambdamikel/LambdaSpeak3 LambdaSpeak RTC] and [[URTC-8 Universal RTC for Z80 computers|uRTC-8]] are not supported

=== Network devices ===

There is a plethora of serial communication devices (using [[RS232]], USB, Modem, Minitel, [[CB radio]], [[Virtual Net 96]], etc...) on Amstrad CPC:
* [[Amstrad Serial Interface|Amstrad/Pace RS232 Serial Port]] is emulated by MAME
* Other devices are not supported

Higher-level Ethernet or TCP/IP network devices are less common:
* [[M4 Board]] Wifi or compatible ([[RSF3]]) is emulated by CPCemu
* [[CPC-ENet]], [https://github.com/salafek/Net4CPC/ Net4CPC], [[RSF3|RSF3 native]], [https://cpcrulez.fr/forum/viewtopic.php?t=6886 TMTNET], [[FujiNet]] are not supported

=== Audio devices ===

*[[Amstrad SSA-1 Speech Synthesizer|SSA-1 speech synthesizer]] is emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, MAME
*[[Dk'tronics Speech Synthesizer|Dk'Tronics speech synthesizer]] is emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, MAME
*[[TMPI speech synthesizer|Techni-Musique speech synthesizer]] is emulated by ACE, ACE-DL, Caprice Forever
*[[Amdrum]] is emulated by ACE, ACE-DL, JavaCPC, MAME, WinAPE
*[[Digiblaster]] is emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, MAME, WinAPE, WinCPC, CPCEC, CPCEPower, Virtual CPC
*[[PlayCity]] is fully emulated by ACE, ACE-DL, MAME, Arnold, SugarBox. It is partially emulated (no CTC) by Caprice Forever, JavaCPC, CPCEC
*[[Play2CPC]] is partially emulated (no FM and no digidrums) by ACE, ACE-DL
*[[Willy|Willy OPL3]] is emulated by ACE, ACE-DL
*[[Willy|Willy MIDI]] is emulated by ACE (software synth emulation on Haiku, MIDI OUT support on MorphOS)
*[[Music Machine]], [[EMR MIDI Interface]], [https://github.com/lambdamikel/BluePillCPC Ultimate MIDI Board], [[Symbiface 3|Symbiface 3 buzzer]], [[RSF3|RSF3 SID]], [https://github.com/lambdamikel/Speak-SID Speak&SID], [https://github.com/lambdamikel/LambdaSpeak3 LambdaSpeak], [https://youtu.be/kahDREIaOog Amsdap MoonSound], Amsdap SE-One ([https://youtu.be/3xEyNQA6Weg MP3 player] / [https://youtu.be/vvlGBS3nNiY FM radio]), [https://www.amibay.com/threads/cpcradio-fm-radio-receiver-module.2446509/ CPC Radio], [https://www.gitlab.com/doragasu/romba/ Romba], [[CPC Booster]] are not supported

Note: the [[RSF3]] is actually the best soundcard available for Amstrad CPC, supporting Digiblaster [https://youtu.be/rXqbQp9WKJc Source], Amdrum [https://youtu.be/Ken5KxYXv5c Source], EMR MIDI Interface [https://youtu.be/YOjV9AaIVKM Source1] [https://youtu.be/WQdV7UmeuPk Source2], Speech synthesis [https://youtu.be/vb-v98m_g0g Source], SID soundchip [https://youtu.be/_LWbnjvXN4g Source], a lot of music file formats (AAC, MP3, MP4, M4A, WMA, WAV, MID, OGG) [https://youtu.be/4f5lvXV_vWM Source] and even Webradios [https://youtu.be/PeVsdNtsOW4 Source].

=== Graphics devices ===

[https://youtu.be/plQf9_7zPSA AMSDAP V9990] graphics card is supported by CPCemu.

[https://thecheshirec.at/category/8bits/amstrad-cpc/crtc/crtc5/ CRTC Type 5] is not supported.

CPC graphics acquisition devices ([[Dart Scanner for DMP-Printers|Dart Scanner]], [[VIDI digitizer]], [[ARA Video Digitizer|Digitaliseur Ara]]) are not supported.

CPC printers are poorly supported. The only emulators that at least do some print rendering emulation are JavaCPC and Caprice Forever.

=== Input devices ===

Some lightguns / lightpens are emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, CPCEC, CPCEPower, Virtual CPC, PC-CPC, Wiituka.

CPC mouse support is as follows:
*[[AMX Mouse|AMX mouse (1-bit axis, 3 buttons (CPC) / 2 buttons (CPC+))]] or compatible ([https://imperium.spinpoint.org/ Imperium Solo], [https://github.com/f1ac0/Dual-USB-Controller-adapter-CPC Dual USB Controller], [[Dk'tronics Mouse Interface|Dk'Tronics Genius adapter]], [https://cpcrulez.fr/hardware_montage_8x-geos-mouse_am_joystick-port.htm DIY GEOS adapter], [[Atari-ST mouse adapter]], [[PS2Mouse]], [[Marconi|Marconi Trackerball]]) is emulated by ACE, ACE-DL, Caprice Forever, WinAPE, Arnold, Virtual CPC, CPCemu, Retro Virtual Machine
*[[Kempston Mouse|Kempston mouse (8-bit axis, 2 buttons)]] is emulated by ACE, ACE-DL, Arnold
*[[CPC-Mousepack 2.0|Reisware mouse (8-bit axis, 2 buttons)]] is emulated by CPCemu
*[[Symbiface II|Symbiface II PS/2 mouse (6-bit axis, 5 buttons, scroll wheel)]] or compatible ([https://github.com/salafek/cyboard-for-cpc Cyboard], [[RSF3]]) is emulated by ACE-DL, Caprice Forever, MAME, WinAPE, Arnold, CPCemu
*[[MultiPlay|MultiPlay Amiga mouse (4-bit axis, 3 buttons)]] is emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, Arnold, Retro Virtual Machine
*[[Albireo|Albireo USB mouse (8-bit axis, 3 buttons)]], [[RSF3|RSF3 USB native (8-bit axis, 5 buttons, scroll wheel)]], [https://youtu.be/4Rm1psdePbg Imperium Solo USB custom mode (6-bit axis, 3 buttons)] are not supported

=== Hacking devices ===

*[[Multiface II]] is emulated by ACE, ACE-DL, Caprice Forever, JavaCPC, MAME, WinAPE, Arnold
*[[Hackit|HackIt]] or compatible ([[RSF3]]) is emulated by ACE-DL, Arnold
*[[Mirage Imager]] is emulated by ACE
*[[Transtape]] is emulated by MAME
*[[PDS development system|Programmers Development System]] is emulated by MAME
*[[Demon Development Cartridge]], [[Action Replay AMX]], [[Disc Wizard]] are not supported

 

= Rewind feature =

The RetroArch CPC emulator has the most convenient rewind feature: [https://youtu.be/YwilYlSe5LQ Demonstration]. To reverse the game, the user press and hold the rewind button. And at any point, releasing the button makes time goes forward again.

ACE-DL also has a rewind feature, but it is not as good as it could be: [https://youtu.be/wIKGvpnJLUo Demonstration].

One 128KB snapshot per frame allows 10 seconds of rewind with 64MB (128KB * 50 frames * 10 seconds) of memory for the rewind feature. A more efficient method saves only the previous RAM values that are changed between 2 frames, allowing much longer rewinds (even if the CPC is equipped with 4MB RAM expansion) while using less memory, as shown by the GBA emulator [https://youtu.be/Sfc_1NKbiKg SkyEmu].

For step-back debugging, the emulator just needs to store the time when the previous instruction was executed so that he can go back to that instruction. In the same way, emulators can provide access to the previous HBL, IRQ, VBL, etc.

 

= File format specifications =

*[https://www.cpcwiki.eu/index.php/Format:DSK_disk_image_file_format DSK / EDSK] [https://hxc2001.com/download/floppy_drive_emulator/SDCard_HxC_Floppy_Emulator_HFE_file_format.pdf HFE] [http://info-coach.fr/atari/documents/_mydoc/IPF-Documentation.pdf IPF] [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=386 CTRAW] [https://www.cbmstuff.com/downloads/scp/scp_image_specs.txt SCP] File formats of disk-image
*[https://www.cpcwiki.eu/index.php/Format:CDT_tape_image_file_format CDT / TZX] [http://zxds.raxoft.cz/pzx.html PZX] [https://acorn.huininga.nl/pub/unsorted/software/pc/CSW/csw.html CSW] [https://xiph.org/flac/format.html FLAC] [http://soundfile.sapp.org/doc/WaveFormat/ WAV] [http://fileformats.archiveteam.org/wiki/MP3 MP3] File formats of tape-image
*[https://www.cpcwiki.eu/index.php/Format:CPR_CPC_Plus_cartridge_file_format CPR cartridge] [https://www.cpcwiki.eu/index.php/Format:SNA_snapshot_file_format SNA snapshot] Other file formats used in CPC emulators
*[https://www.cpcwiki.eu/forum/emulators/javacpc-desktop-available-as-beta!/100/ Official SNR session spec] [https://www.cpcwiki.eu/forum/emulators/playback-format-for-scenes/ Discussion about SNR format] [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=10 Archive of SNR sessions]
*[http://leonard.oxg.free.fr/ymformat.html YM] [https://www.cpcwiki.eu/index.php/AYC AYC] [https://www.cpcwiki.eu/index.php/MYM MYM] [https://vgmrips.net/wiki/VGM_Specification VGM] Soundchip logging file formats
*[https://shaker.logonsystem.eu/sslcsl CSL] Cpc Scripting Language, a macro/scripting system to automate emulators
*[https://github.com/redbug26/crocods-core/wiki/kcr KCR] Game launching configuration

 

= Emulation Tools =

*[http://www.cpcmania.com/news.htm CPCDiskXP] [https://web.archive.org/web/20230602152816/https://cpc-live.com/data/index.php?dir=-tools DiskUtil] [https://github.com/Tom1975/SugarConvDsk SugarConvDsk] [https://github.com/jeromelesaux/dsk DSK] [https://github.com/cpcsdk/idsk iDSK] [https://www.seasip.info/Unix/LibDsk/ Diskette Tools] [https://github.com/cpcitor/dsktools dsktools] [https://github.com/EdouardBERGE/edsktool edsktool] [[ManageDSK|ManageDSK]] [[WriteDSK|WriteDSK]] [https://simonowen.com/samdisk/ SAMdisk] [https://github.com/damieng/DiskImageManager Disk Image Manager] [https://github.com/neuro-sys/sector-cpc sector-cpc] [https://hxc2001.com/download/floppy_drive_emulator/ HxCFloppyEmulator software] [https://github.com/keirf/disk-utilities/ Disk Utilities] [https://github.com/ClaireCheshireCat/dsk-lua dsk-lua] [https://github.com/karmic64/upd765pro upd765pro] [https://github.com/muckypaws/AmstradDSKExplorer Amstrad DSK Explorer] [http://www.shlock.co.uk/Utils/OmniFlop/OmniFlop.htm OmniFlop] [https://github.com/tomas-nestorovic/RIDE RIDE] [https://github.com/cpcsdk/hideur_maikeur Hideur Maikeur] Set of tools about disk-images
*[http://www.cpcmania.com/news.htm CPCTapeXP] [https://web.archive.org/web/20230602152816/https://cpc-live.com/data/index.php?dir=-tools TapeUtil] [https://github.com/Tom1975/SugarConvTape SugarConvTape] [https://sourceforge.net/projects/cdtmaster/ CDTMaster] [https://cpcrulez.fr/emulateurs_UTIL-CDT-samp2cdt.htm 2CDT/Samp2CDT] [http://cngsoft.no-ip.org/csw2cdt.htm CSW2CDT] [https://cpcrulez.fr/emulateurs_UTIL-CDT-CDT2WAV.htm CDT2WAV] [https://github.com/stripwax/wav2tzx wav2tzx] [https://github.com/raxoft/pzxtools PZXtools] [https://monocrun.com/cpc-tape-to-cdt/ Online Tape to CDT] Set of tools about tape-images
*[http://www.cpcmania.com/news.htm CPRTools] [https://github.com/reidrac/cpr-tools cpr-tools] [https://github.com/renaudguerin/cpr2bin cpr2bin] [https://problemkaputt.de/no$cart.htm No$cart] [http://amsnet.chez.com/ UniDOS Cartridge Creator] Set of tools about CPR cartridge-images
*[https://bochs.sourceforge.io/doc/docbook/user/winimage.html WinImage, DiskExplorer, Ultimate Imager] [https://github.com/ProgrammingHobby/CPM_Image-File_Explorer CP/M Image File Explorer] Access and edit hard-drive images
*[https://colourclash.co.uk/cpc-analyser/ CPC Analyser] [https://imhex.werwolv.net/ ImHex] [https://github.com/cormacj/AmstradCPCRomHacks CPCRomHacks] [https://bitbucket.org/zzarko/runemu/src/main/ RunEmu] Other tools
*[[WinApe|WinAPE]] [[WinCPC]] [[JavaCPC]] [https://code.google.com/archive/p/cpcsdk/ Caprice Reloaded] [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73 Caprice Forever] [[CPCemu]] Emulators with an integrated Z80 Assembler

=== Cross-Platform Development ===

*[https://cpcrulez.fr/coding-crossdev_coding-Java-Z80Assembler.htm Java Z80Assembler] [https://grauw.nl/projects/glass/ Glass] [https://pasmo.speccy.org/ Pasmo] [http://cngsoft.no-ip.org/uz80.htm UZ80] [https://github.com/EdouardBERGE/rasm Rasm] [https://cpcsdk.github.io/rust.cpclib/basm/ BASM] [https://github.com/fragarco/abasm/ ABASM] [https://k1.spdns.de/Develop/Projects/zasm/Distributions/ zasm] [http://www.compilers.de/vasm.html vasm] [https://github.com/z00m128/sjasmplus SjASMPlus] [https://github.com/cpcsdk/cpctools cpctools] [https://github.com/cpcsdk/rust.cpclib cpclib] [https://github.com/cpcsdk/rust.cpclib/tree/master/cpclib-bndbuild bndbuild] [http://julien-nevo.com/disark/ Disark] [https://github.com/santiontanon/mdlz80optimizer MDL] [https://marketplace.visualstudio.com/items?itemName=maziac.asm-code-lens ASM Code Lens] [https://marketplace.visualstudio.com/items?itemName=floooh.vscode-kcide KC IDE] Tools for CPC cross-development in Z80 Assembler
*[https://sdcc.sourceforge.net SDCC] [https://www.cpcwiki.eu/forum/programming/phrozen-c/msg180715/#msg180715 SDCC vs PhrozenC] [http://www.cpcmania.com/Docs/Programming/SDCC_vs_z88dk_Comparing_size_and_speed.htm SDCC vs z88dk] [https://z88dk.org/site/ z88dk can be used with SDCC and provides a huge library] [https://ccz80.webcindario.com/ccz80en.html ccz80] [http://norecess.cpcscene.net/phactory.html Phactory] [https://github.com/cpcitor/cpc-dev-tool-chain cpc-dev-tool-chain] [https://lronaldo.github.io/cpctelera/ CPCtelera] [https://github.com/Arnaud6128/wincpctelera WinCPCtelera] Cross-platform CPC development in C
*[https://github.com/Bread80/Quiche Quiche] [https://lemonspawn.com/turbo-rascal-syntax-error-expected-but-begin/ Turbo Rascal Syntax Error] [https://www.youtube.com/watch?v=NTfnE4kXqt8 CPC demo made with TRSE] [https://www.youtube.com/watch?v=XjnqXiUHekY TRSE CPC tutorial] CPC cross-development in Pascal
*[https://github.com/KarolS/millfork Millfork] [https://github.com/wiz-lang/wiz Wiz] [https://github.com/davidgiven/cowgol Cowgol] [https://www.mikekohn.net/micro/java_grinder.php Java Grinder] CPC cross-development with other programming languages
*[https://jonathan-cauldwell.itch.io/multi-platform-arcade-game-designer Multi-Platform Arcade Game Designer] [https://xavisan.itch.io/mpagdgen2 MPAGD Gen2] The most user-friendly Windows tool for creating CPC games
*[https://vitno.org/2023/09/17/punyinform-a-new-library-for-writing-text-adventures-for-old-computers/ PunyInform] [https://github.com/Utodev/DRC/ DAAD Reborn Compiler] for developing adventure games
*[https://github.com/danielgaskell/scc SymbOS C Compiler] [http://www.symbos.de/quigs.htm Quigs IDE] SymbOS application development
*[https://cpcbasic.webcindario.com/CPCBasicEn.html CPC Basic cross-compiler] [https://github.com/benchmarko/CPCBasic CPCBasic Unchained] [https://github.com/benchmarko/LocoBasic LocoBasic] [https://marketplace.visualstudio.com/items?itemName=cebe74.amstrad-basic-helper-vscode Amstrad Basic Helper] [https://github.com/destroyer-dcf/sdkcpc SDKCPC] [https://auamstrad.es/taller/herramientas/ide8bp-portable-para-windows/ IDE 8BP] [https://www.cpcalive.com/cpcalive_en.html CpcAlive] [https://ugbasic.iwashere.eu/ ugBASIC] [https://spotlessmind1975.itch.io/ugbasic-ide ugBASIC IDE] Cross-platform CPC development in BASIC
*[https://github.com/einar-saukas/ZX0 ZX0] [https://github.com/emmanuel-marty/salvador Salvador] [https://github.com/ClaireCheshireCat/amstrad-cpc-dzx0 ZX0 decompressor in BASIC] [https://www.cpcwiki.eu/forum/programming/new-cruncher-zx0/msg197727/ Comparative study] Compression tools

=== Cross-Platform Art ===

*[https://github.com/EdouardBERGE/convgeneric ConvGeneric] [http://ldeplanque.free.fr/ConvImgCpc/new/ ConvImgCPC] [https://anto80.itch.io/image-to-amstrad-cpc-converter ImgToCpc] [https://github.com/AugustoRuiz/Img2CPC img2cpc] [https://github.com/cpcsdk/rust.cpclib/tree/master/cpclib-imgconverter cpclib-img2cpc] [https://github.com/bignaux/Magick2CPC Magick2CPC] [https://github.com/cpcsdk/gfx2crtc gfx2crtc] [https://www.dadither.com/ DaDither] [https://8bitworkshop.com/dithertron/#sys=cpc.mode0 Online Dithertron] [https://pixsaur.netlify.app/ Pixsaur] [https://github.com/jeromelesaux/martine Martine] [https://www.cpcwiki.eu/forum/applications/splitraster-v3/ Splitraster+] [https://www.pouet.net/prod.php?which=88808 UniPixelViewer] [https://www.youtube.com/watch?v=KBcxPWGmr6Q UniPixelViewer tutorial] Image converters from PC to CPC
*[http://grafx2.chez.com/ GrafX2] [http://multipaint.kameli.net/ Multipaint] [https://github.com/xmessner/RePAINT RePAINT!] [https://www.octoate.de/2010/09/06/cpcpaint/ CPCPaint] [https://cpcrulez.fr/coding-crossdev_coding-amstrad_cpc_tools_kit.htm Amstrad CPC Tools Kit] [[Retro Game Asset Studio]] [https://cpcrulez.fr/emulateurs_UTIL-GRA-akusprite_editor.htm AkuSprite Editor] [https://github.com/GameDevCodeur/z80Editor Z80Editor] [http://gcajdev.epizy.com/sprite_creator.php Online Sprite Creator] [https://www.aseprite.org/ Aseprite] [https://libresprite.github.io/ LibreSprite] [https://www.mapeditor.org/ Tiled] [https://github.com/Cwiiis/maped/ Maped] [https://logiker.itch.io/amstrad-ascii-exporter Amstrad ASCII Exporter] [https://recoil.sourceforge.net/ RECOIL] Cross-platform CPC graphics art editors and viewers
*[https://github.com/digital-sound-antiques/vgm-conv vgm-conv] [https://github.com/QuinnPainter/YMtoVGM YMtoVGM] [https://cpcrulez.fr/emulateurs_UTIL-MUSIC-YMCruncher.htm YMcruncher] [https://osdk.org/index.php?page=documentation&subpage=ym2mym Ym2Mym] [https://github.com/EdouardBERGE/wav2ay wav2ay] [https://kichiki.github.io/waon/ WaoN (wav2midi)] [https://cpcrulez.fr/coding-crossdev-music-ym_to_midi.htm YMtoMIDI] Music converters
*[http://cngsoft.no-ip.org/chipnsfx.htm CHIPNSFX] [https://grimware.org/doku.php/sources/pt3 Vortex Tracker II] [https://github.com/AugustoRuiz/WYZTracker WYZTracker] [https://www.julien-nevo.com/arkostracker/ Arkos Tracker] [https://tildearrow.org/furnace/ Furnace] [https://drsnuggles.github.io/AYSir/ AYSir] [https://aym-js.emaxilde.net AYM.JS] [https://norbertkehrer.github.io/st_player.html Soundtrakker Player in JS] Cross-platform CPC music suites

 

= Emulators running on the Amstrad CPC =

{| class="wikitable sortable"
! Emulator name
! External link
! Current version
! Latest release
! License
! Emulates
|-
| [[Amstrad BBC BASIC]]
| [https://www.cpc-power.com/index.php?page=detail&num=9862]
| 2.30
| Apr 2, 1986
| Commercial💲
| [[BBC BASIC]]
|-
| [[BASIC 1.1 Fuer CPC464]]
| [https://www.cpc-power.com/index.php?page=detail&num=4403]
|
| Oct 1986
| Open source
| [[Locomotive BASIC 1.1]]
|-
| [[Brainfuck]]
| [http://www.symbos.de/appinfo.htm?00067]
| 1.0
| Aug 12, 2020
| Freeware
| [[Brainfuck]]
|-
| [[Chip8 CPC]]
| [https://www.cpcwiki.eu/forum/games/chip8-emulator-for-amstrad-cpc/] [https://github.com/ajcasado/Chip8_CPC Repo]
|
| Nov 12, 2024
| Open source
| [[CHIP-8]]
|-
| [[CPCZVM]]
| [https://www.cpcwiki.eu/index.php/Z-Machine]
|
| Jul 6, 2019
| Open source
| [[Z-Machine]]
|-
| [[CPvM]]
| [http://www.symbos.org/cpvm.htm] [https://github.com/danielgaskell/CPvM Repo]
| 1.0
| Apr 17, 2024
| Open source
| [[CP/M]]
|-
| [[Fuzix OS]]
| [https://www.cpcwiki.eu/forum/applications/port-of-fuzix-for-the-cpc6128/] [https://github.com/ajcasado/FUZIX Repo]
| 0.5.1
| Apr 11, 2025
| Open source
| [[POSIX]] (UNIX)
|-
| [[Kersten PC Emulator]]
| [https://cpcrulez.fr/hardware-autres-PC_Emulator.htm]
|
| Sep 1986
| Hardware💲
| [[IBM PC]]
|-
| [[Pac-Man]]
| [https://www.cpc-power.com/index.php?page=detail&num=7270]
| 1.1
| Jun 5, 2014
| Open source
| [[Pac-Man arcade|Pac-Man arcade]]
|-
| [[PDP-8 Emulator]]
| [http://www.symbos.org/appinfo.htm?00063]
| 1.0
| Jan 14, 2025
| Open source
| [[DEC PDP-8]]
|-
| [[Phoenix]]
| [https://norbertkehrer.github.io/phoenix_cpc.html]
|
| Jan 6, 2019
| Freeware
| [[Phoenix arcade|Phoenix arcade]]
|-
| [[Space Invaders|Space Invaders]]
| [https://www.cpc-power.com/index.php?page=detail&num=13098]
| 1.02
| Mar 18, 2017
| Freeware
| [[Space Invaders arcade|Space Invaders arcade]]
|-
| [[SymbOS Basic]]
| [http://www.symbos.de/appinfo.htm?00070]
| 0.1
| Oct 19, 2021
| Freeware
| [[MSX-Basic]]
|-
| [[Vezza]]
| [https://sijnstra.itch.io/vezza] [https://gitlab.com/sijnstra1/vezza Repo]
|
| Feb 9, 2025
| Open source
| [[Z-Machine]]
|-
| [[ZXM]]
| [https://www.cpc-power.com/index.php?page=detail&num=14208]
|
| 1993
| Freeware
| [[ZX Spectrum|ZX Spectrum]]
|-
| [[Zym]]
| [http://www.symbos.org/appinfo.htm?00054]
| 0.9
| Feb 19, 2022
| Open source
| [[Z-Machine]]
|}

[[Category:Emulator]] [[Category:CrossDev]] [[Category:Emulation Tools]]

Gate Array

2025-05-30T11:58:37Z

Longshot: correction of an error relating to IC

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]

The CPU maskable interrupts are generated by the Gate Array.
This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC.

On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.

When the CPU acknowledge the interrupt (eg. it is going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 32 HSync.

When a VSync occurs, the Gate Array will wait for two HSync and:

* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.
* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.

This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed.

So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.

The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

=== Timings ===
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]

The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).

=== DI in peace ===
[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]

The GA maintains its int request until it is accepted.
RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.
But after the EI, a test similar to the one seen for the VBL is performed:
The interrupt is generated anyway, but:
* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).
* Otherwise bit 5 of IC is set to zero.

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Gate Array

2025-05-30T11:18:20Z

Longshot: Interruption chapter

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]

The CPU maskable interrupts are generated by the Gate Array.
This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC.

On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.

When the CPU acknowledge the interrupt (eg. it is going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 32 HSync.

When a VSync occurs, the Gate Array will wait for two HSync and:

* If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.
* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.

This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed.

So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.

The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

=== Timings ===
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]

The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).

=== DI in peace ===
[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]

The GA maintains its int request until it is accepted.
RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.
But after the EI, a test similar to the one seen for the VBL is performed:
The interrupt is generated anyway, but:
* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).
* Otherwise, IC = 0.

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

CRTC

2025-05-29T17:47:10Z

Longshot:

[[File:CRTC Type 0.jpg|thumb|right|CRTC Type 0 (Hitachi)]]
[[File:CRTC UMC Type 0.png|thumb|right|CRTC Type 0 (UMC)]]
[[File:CRTC Type 1.png|thumb|right|CRTC Type 1]]
[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]

The 6845 '''CRTC''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC.

This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode.

It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

== Timings and relating with Z80 instructions count ==

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register||Write only
|-
|&BExx||0||1||0||
* CRTCs 0/2: —
* CRTC 1: Read Status Register
* CRTCs 3/4: Read from selected internal 6845 register
||Read only
|-
|&BFxx||0||1||1||Read from selected internal 6845 register||Read only
|-
|}

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

==Addressing==

The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:

{| class="wikitable"
|-
!Video Memory Address
!Signal source
!Signal name
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

 

=== Overscan bits ===

It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

{| class="wikitable"
|+ CRTC Display Start Address
|-
! colspan="8" | Register 12
! colspan="8" | Register 13
|-
! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
| colspan="2" | Unused
| colspan="2" | Video Page
| colspan="2" | Page Size
| colspan="10" | Start Address (1024 positions)
|}

{| style="white-space: nowrap;"
|-
|
{| class="wikitable" style="margin-right: 32px"
|-
! Bit 13 !! Bit 12 !! Video Page
|-
| 0 || 0 || 0000 - 3FFF
|-
| 0 || 1 || 4000 - 7FFF
|-
| 1 || 0 || 8000 - BFFF
|-
| 1 || 1 || C000 - FFFF
|}
|
{| class="wikitable"
|-
! Bit 11 !! Bit 10 !! Page Size
|-
| 0 || 0 || 16KB
|-
| 0 || 1 || 16KB
|-
| 1 || 0 || 16KB
|-
| 1 || 1 || '''32KB'''
|}
|}

 

=== Coarse hardware scrolling ===

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

*To move right: <code>start_address := start_address + 1</code>
*To move left: <code>start_address := start_address - 1</code>
*To move down: <code>start_address := start_address + R1</code>
*To move up: <code>start_address := start_address - R1</code>

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984.

The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input:

<pre>
10 ma%=0
20 IF INKEY(1)=0 THEN GOSUB 100
30 IF INKEY(2)=0 THEN GOSUB 300
40 IF INKEY(8)=0 THEN GOSUB 500
50 IF INKEY(0)=0 THEN GOSUB 700
60 GOTO 20
100 ' right
110 ma%=ma%+1: GOSUB 900: RETURN
300 ' down
310 ma%=ma%+40: GOSUB 900: RETURN
500 ' left
510 ma%=ABS(ma%-1): GOSUB 900: RETURN
700 ' up
710 ma%=ABS(ma%-40): GOSUB 900: RETURN
900 ' set R12 and R13
910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%
930 RETURN
</pre>

Which looks like the following:

[[File:CRTC-Coarse-scroll.gif]]

 

=== Advanced hardware scrolling ===

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993.

Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there].

 

== Split screen (aka Rupture) ==

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]

And this is basically the bread and butter of innumerable CPC demos.

Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
* changes to the screen address have to be done anywhere in the previous split
* changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
* changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:
*reg 0 (63) = x-screenwidth (usually always 63)
*reg 1 (50) = x-splitwidth (e.g.50)
*reg 2 (51) = x-splitstart (e.g. 51)
*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
*reg 4 (##) = y-splitheight-1 (set this inside the current split)
*reg 5 (00) = y-finestart
*reg 6 (25) = y-max visible splitpart (same like 4)
*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
*reg 9 (07) = y-lines/char-1

Set this inside the previous split:
*reg12 (##) = address high (char / 256 + block * 16)
*reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas.

Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)]

 

== CUDISP (aka CURSOR) ==

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.

 

== DISPTMG (aka Display Enable) ==

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

 

=== HBORDER ===

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

 

=== VBORDER ===

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

 

=== SBORDER ===

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]].

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

 

=== Border bytes ===

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

To see the border bytes with your own eyes, type this BASIC line after reset:
<pre>
BORDER 6:OUT &BC00,6:OUT &BD00,0
</pre>

== HSYNC and VSYNC ==

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

== The 6845 Registers ==

The Internal registers of the 6845 are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1µs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (Low)||00000000||||Read Only
|-
|}

registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

 

=== Screen size ===

We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2 to have the screen size in bytes.

With the default CRTC values, we obtain 40 x 25 x (7+1) x 2 = 16000 bytes.

So we can observe that only part of the 16384 bytes (=16KB) page of VRAM is actually displayed on screen.

 

== CRTC Differences ==

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 1

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|}

Type 2

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 3 and 4

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1||2||3||4
|-
|0||Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}

'''Notes'''

1. On type 0 and 1, if a Write Only register is read from, "0" is returned.

2. See the document "Extra CPC Plus Hardware Information" for more details.

3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.

== Horizontal and Vertical Sync (R3) ==

=== Horizontal and Vertical Sync (R3) ===

Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

 

=== Interlace and Skew (R8) ===

Types 0/3/4:
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.

 

=== R31 on Type 1 ===

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

 

== UM6845R and R12/R13 ==

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

== UM6845R status register ==

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

== CRTC Type Detection ==

It is possible to detect the CRTC Type using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported

Detection routine in BASIC:
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>

Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.

 

== CRTC Timing Diagrams ==
[[File:CRTC Timing Diagram Rockwell.png]]

 

[[File:CRTC timing small.gif]]

 

== Block Diagrams ==

{| class="wikitable"
|-
!Hitachi
!UMC
!Motorola
|-
|[[File:CRTC Block Diagram.png|Hitachi]]
|[[File:UMC CRTC Block Diagram.png|UMC]]
|[[File:Motorola CRTC Block Diagram.png|Motorola]]
|}

 

== CRTC-II (aka Type 5) ==

The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]

 

== Datasheets ==
==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)

 

==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory. It is used in the [[Aleste 520EX]].
* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
* [[Media:VL6845 VTi.pdf|VL6845]] by VTi
* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast
* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845
* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features
* [[Media:Mos 6545-1 crtc.pdf|MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845. Its differences are found in the R8 register.
* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845

 

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

 

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

*[[VIDI digitizer]] This extension contains its own CRTC chip

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

CRTC

2025-05-24T18:48:52Z

Longshot: Updated for infringement of copyrighted material protected

Gate Array

2025-05-24T12:17:06Z

Longshot:

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Longshot

2025-05-24T12:13:55Z

Longshot: flowstate, gege, jb, phi2x et j'en passe de bruz tu vas avoir des problèmes si tu continues à troller ici

[[Image:Longshot1996.jpg|thumb|Longshot 1996]]

'''Longshot''' was a demo coder, founder and leader of the famous [[Logon System]] demo group. A pseudonym for Serge Querné, he was initially based in southern France but later moved to Paris.

== Biography ==

Initially going under the pseudonym 'Logon 1' (the name Logon he explained in a scrolltext as "a Belgian idea"), he released a series of single-part demos, each of them showcasing a new technique he had learned ‒ or, in many cases, discovered. These included raster bars, overscan, and split modes in the earliest productions. The first demo was coded while he was working at [http://fr.wikipedia.org/wiki/Ubisoft Ubi Soft]'s "castle" headquarters. Though some of these demos seem fairly simple in retrospect, at the time, Serge's demo-coding skill was only equalled by perhaps [[Fefesse]] and [[NWC]].

A stepchange came with the [[Longshot Demo]], the first in which he adopted his new pseudonym. This included hardware splitting and combined more effects on screen at once. [[Revolog]] (or Revolution) followed in a similar vein but was a level more accomplished again. At the same time, Longshot participated in the [[Amazing Demo]] with [[Naminu]] and [[P007]] of [[Malibu Crackers]].

[[Naminu]] would soon become one of the members of the new, expanded [[Logon System]]. The "supergroup"'s first release was the stunning [[The Demo]], where Longshot contributed three parts but, perhaps more significantly, oversaw the polished, coherent design that was unlike any CPC megademo previously released.

The [[Euromeeting Demo]] would turn out to be his last demo release, but a further innovation was the [[B-ASIC]] utility which enabled Plus programmers to use the new features of their machines from BASIC. Longshot went on to the PC in turn, but has recently participated in French CPC forums such as [http://phenixinformatique.free.fr/ Phenix Informatique] once again. His [http://www.logonsystem.fr/ homepage] contains screenshots from the Logon era, a brief history, and downloads of his personal disc collection.

Though most respected for his coding skills and innovations, Serge's main achievement was perhaps the creation and fostering of the Logon System supergroup, the like of which has not been seen since.

Longshot has written technical articles in some columns of the French magazine [[Amstrad Cent Pour Cent]].

== Demos ==

* [[Logon Demo 1]]
* [[Logon Demo 2]]
* [[Logon Demo 3]]
* [[Logon Demo 5]]
* [[Longshot Demo]]
* [[Revolog]]
* [[Amazing Demo]]
* [[The Demo]]
* [[Euromeeting Demo]]
* [[DSC 4]]

== Other productions ==

* [[Atlantis]]
* [[B-ASIC]]
* [[AntiMultiface]]
* [[MagicDOS]]

== Groups ==

* [[Logon System]]

== Links ==

* [http://www.logonsystem.eu/ Longshot's homepage]
* [http://norecess.cpcscene.net/interview-longshot.html Interview with Longshot by NoRecess]

[[Category:CPC scene members]]

Longshot

2025-05-24T08:40:02Z

Longshot: deleted as a malicious troll

Gate Array

2025-05-24T08:37:02Z

Longshot: Deleted for infringement of copyrighted material protected under the CC BY-NC-ND 4.0 license

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Gate Array

2025-05-21T18:09:13Z

Longshot:

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné (Longshot)''

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

 

== CSYNC signal ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné (Longshot)''

The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Gate Array

2025-05-21T18:07:06Z

Longshot: Added information on citation issues

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné (Longshot)''

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

 

== CSYNC signal ==
* '''This section relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné (Longshot)''

The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]
 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

CRTC

2025-05-21T18:02:47Z

Longshot: Added information on citation issues

[[File:CRTC Type 0.jpg|thumb|right|CRTC Type 0 (Hitachi)]]
[[File:CRTC UMC Type 0.png|thumb|right|CRTC Type 0 (UMC)]]
[[File:CRTC Type 1.png|thumb|right|CRTC Type 1]]
[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]

The 6845 '''CRTC''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC.

This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode.

It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.

NOTES:
* This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
* '''This article relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information.
** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''
** ''Author: Serge Querné (Longshot)''

 

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{| class="wikitable"
|-
!Part number
!Manufacturer
!Type number (note 3)
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|AMS40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 Plus, 6128 Plus and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

 

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register||Write only
|-
|&BExx||0||1||0||
* CRTCs 0/2: —
* CRTC 1: Read Status Register
* CRTCs 3/4: Read from selected internal 6845 register
||Read only
|-
|&BFxx||0||1||1||Read from selected internal 6845 register||Read only
|-
|}

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

 

=== Z80 I/O access timings ===

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

{| class="wikitable"
|+
! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4
|-
| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec
|-
| OUTI || 5 µsec || 5th µsec || 5th µsec
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}

 

==Video Memory Address (VMA)==

The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:

{| class="wikitable"
|-
!Video Memory Address
!Signal source
!Signal name
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

 

=== Overscan bits ===

It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

{| class="wikitable"
|+ CRTC Display Start Address
|-
! colspan="8" | Register 12
! colspan="8" | Register 13
|-
! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
| colspan="2" | Unused
| colspan="2" | Video Page
| colspan="2" | Page Size
| colspan="10" | Start Address (1024 positions)
|}

{| style="white-space: nowrap;"
|-
|
{| class="wikitable" style="margin-right: 32px"
|-
! Bit 13 !! Bit 12 !! Video Page
|-
| 0 || 0 || 0000 - 3FFF
|-
| 0 || 1 || 4000 - 7FFF
|-
| 1 || 0 || 8000 - BFFF
|-
| 1 || 1 || C000 - FFFF
|}
|
{| class="wikitable"
|-
! Bit 11 !! Bit 10 !! Page Size
|-
| 0 || 0 || 16KB
|-
| 0 || 1 || 16KB
|-
| 1 || 0 || 16KB
|-
| 1 || 1 || '''32KB'''
|}
|}

 

=== Coarse hardware scrolling ===

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

*To move right: <code>start_address := start_address + 1</code>
*To move left: <code>start_address := start_address - 1</code>
*To move down: <code>start_address := start_address + R1</code>
*To move up: <code>start_address := start_address - R1</code>

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984.

The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input:

<pre>
10 ma%=0
20 IF INKEY(1)=0 THEN GOSUB 100
30 IF INKEY(2)=0 THEN GOSUB 300
40 IF INKEY(8)=0 THEN GOSUB 500
50 IF INKEY(0)=0 THEN GOSUB 700
60 GOTO 20
100 ' right
110 ma%=ma%+1: GOSUB 900: RETURN
300 ' down
310 ma%=ma%+40: GOSUB 900: RETURN
500 ' left
510 ma%=ABS(ma%-1): GOSUB 900: RETURN
700 ' up
710 ma%=ABS(ma%-40): GOSUB 900: RETURN
900 ' set R12 and R13
910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%
930 RETURN
</pre>

Which looks like the following:

[[File:CRTC-Coarse-scroll.gif]]

 

=== Advanced hardware scrolling ===

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993.

Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there].

 

== Split screen (aka Rupture) ==

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]

And this is basically the bread and butter of innumerable CPC demos.

Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
* changes to the screen address have to be done anywhere in the previous split
* changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
* changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:
*reg 0 (63) = x-screenwidth (usually always 63)
*reg 1 (50) = x-splitwidth (e.g.50)
*reg 2 (51) = x-splitstart (e.g. 51)
*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
*reg 4 (##) = y-splitheight-1 (set this inside the current split)
*reg 5 (00) = y-finestart
*reg 6 (25) = y-max visible splitpart (same like 4)
*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
*reg 9 (07) = y-lines/char-1

Set this inside the previous split:
*reg12 (##) = address high (char / 256 + block * 16)
*reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas.

Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)]

 

== CUDISP (aka CURSOR) ==

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.

 

== DISPTMG (aka Display Enable) ==

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

 

=== HBORDER ===

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

 

=== VBORDER ===

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

 

=== SBORDER ===

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]].

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

 

=== Border bytes ===

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:
<pre>
BORDER 6:OUT &BC00,6:OUT &BD00,0
</pre>

 

== HSYNC ==

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

=== Contiguous HSYNCs ===

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

=== Signal delay ===

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

=== Discolouration effect ===

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

=== Screen wobbling and Fine horizontal hardware scroll ===

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

[[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

 

== VSYNC ==

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

=== Blocked VSYNC ===

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

=== Ghost VSYNC ===

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

=== PPI VSYNC ===

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

=== Subpixel vertical hardware scroll ===

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

=== Mid-VSYNC ===

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

 

== Interlace modes ==

Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

[[File:CRTC Interlace modes.png]]

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

=== Interlace sync mode (ISM) ===

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

=== Interlace sync and video mode (IVM) ===

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

=== Interlace adjustment line ===

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

 

== CRTC registers ==

The Internal registers of the 6845 are:

{| class="wikitable"
|-
!rowspan=2|Register Index
!rowspan=2|Register Name
!colspan=3|Read/Write
!rowspan=2|Range
!rowspan=2|CPC Setting
!rowspan=2|Notes
|-
!CRTC 0
!CRTCs 1/2
!CRTCs 3/4
|-
|0||Horizontal Total (-1)||colspan=3 style="text-align: center;"|Write||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||colspan=3 style="text-align: center;"|Write||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||colspan=3 style="text-align: center;"|Write||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||colspan=3 style="text-align: center;"|Write||VVVVHHHH||128+14||VSync width in scan-lines (Not present on all CRTCs, fixed to 16 lines on these) ; HSync pulse width in characters.
|-
|4||Vertical Total (-1)||colspan=3 style="text-align: center;"|Write||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||colspan=3 style="text-align: center;"|Write||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||colspan=3 style="text-align: center;"|Write||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync Position||colspan=3 style="text-align: center;"|Write||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||colspan=3 style="text-align: center;"|Write||CCDDxxII||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4). DD: Display Skew (Only in CRTCs 0, 3 and 4). II: Interlace Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored.
|-
|10||Cursor Start Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx00000||0||Sets last raster row of character that cursor is on to invert.
|-
|12||Display Start Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).
|-
|13||Display Start Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0||
|-
|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.
|-
|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.
|-
|}

 

=== Screen size ===

We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2 to have the screen size in bytes.

With the default CRTC values, we obtain 40 x 25 x (7+1) x 2 = 16000 bytes.

So we can observe that only part of the 16384 bytes (=16KB) page of VRAM is actually displayed on screen.

 

=== Register access ===

On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.

On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.

On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:
* On CRTCs 0/2, registers 18-31 read as 0
* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF

On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:

{| class="wikitable"
!Nb
!Register
!Definition
|-
|0||R16||Light Pen Address (High)
|-
|1||R17||Light Pen Address (Low)
|-
|2||R10||Cursor Start Raster
|-
|3||R11||Cursor End Raster
|-
|4||R12||Display Start Address (High)
|-
|5||R13||Display Start Address (Low)
|-
|6||R14||Cursor Address (High)
|-
|7||R15||Cursor Address (Low)
|}

 

== CRTC register differences ==

CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]].

 

=== R10/R11 on ASIC/Pre-ASIC ===

The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write.

{| class="wikitable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}

{| class="wikitable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}

 

=== Horizontal and Vertical Sync (R3) ===

Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

 

=== Interlace and Skew (R8) ===

Types 0/3/4:
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.

 

=== R31 on Type 1 ===

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

 

=== Status register on Type 1 ===

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

 

== CRTC Type Detection ==

It is possible to detect the CRTC Type using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported

Detection routine in BASIC:
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>

Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.

 

== CRTC Timing Diagrams ==
[[File:CRTC Timing Diagram Rockwell.png]]

 

[[File:CRTC timing small.gif]]

 

== Internal Counters ==

{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Compared with
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|R0, R1, R2
| Increments on every clock cycle
|-
|Horizontal Sync Counter
|HSC
|C3l
|R3l
|
|-
|Vertical Character Counter
|VCC
|C4
|R4, R6, R7
|
|-
|Vertical Sync Counter
|VSC
|C3h
|R3h
|R3h is fixed to 0 on CRTCs 1/2. This gives 16 lines of VSYNC
|-
|Vertical Line Counter
|VLC
|C9
|R9, R10, R11
|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5
|R5
|This counter does not exist on CRTCs 0/3/4. C9 is reused instead
|-
|Frame Counter
|FC
|
|
|Used to alternate frames in interlace and for CRTC cursor blinking
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}

When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).

 

== CRTC counter differences ==

=== MA buffering ===

No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.

At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.

CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.

 

=== MA reload ===

On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.

On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.

On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.

==== Rupture For Dummies (R5 bug) ====

CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.

This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.

The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.

This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].

 

=== VSC (C3h) overflow ===

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

 

=== HSC (C3l) overflow ===

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

 

=== VCC (C4) overflow ===

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

 

=== HCC (C0) overflow ===

If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

 

=== VLC (C9) overflow ===

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== VTAC (C5/C9) overflow ===

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== Vertical Adjustment mode ===

On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.

On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.

On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.

Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.

 

=== Counter freezes ===

On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.

On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.

 

== Block Diagrams ==

{| class="wikitable"
|-
!Hitachi
!UMC
!Motorola
|-
|[[File:CRTC Block Diagram.png|Hitachi]]
|[[File:UMC CRTC Block Diagram.png|UMC]]
|[[File:Motorola CRTC Block Diagram.png|Motorola]]
|}

 

== CRTC-II (aka Type 5) ==

The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]

 

== Datasheets ==

==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)

 

==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory. It is used in the [[Aleste 520EX]].
* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
* [[Media:VL6845 VTi.pdf|VL6845]] by VTi
* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast
* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845
* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features
* [[Media:Mos 6545-1 crtc.pdf|MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845. Its differences are found in the R8 register.
* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845

 

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

 

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]

 

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

*[[VIDI digitizer]] This extension contains its own CRTC chip

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

Gate Array

2025-05-18T22:07:15Z

Longshot: /* External links */

[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]]
[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

 

== CSYNC signal ==

The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]
 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

CRTC

2025-05-18T20:03:26Z

Longshot:

[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]

The 6845 '''CRTC''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC.

This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode.

It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.

NOTES:
* This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
* Much information has been drawn from the [https://shaker.logonsystem.eu/ CRTC Compendium] documentation. For more details, timing diagrams, code examples, coding tips, and more, refer to that documentation.

 

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{| class="wikitable"
|-
!Part number
!Manufacturer
!Type number (note 3)
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|AMS40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 Plus, 6128 Plus and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported

 

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register||Write only
|-
|&BExx||0||1||0||
* CRTCs 0/2: —
* CRTC 1: Read Status Register
* CRTCs 3/4: Read from selected internal 6845 register
||Read only
|-
|&BFxx||0||1||1||Read from selected internal 6845 register||Read only
|-
|}

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

 

=== Z80 I/O access timings ===

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

{| class="wikitable"
|+
! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4
|-
| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec
|-
| OUTI || 5 µsec || 5th µsec || 5th µsec
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}

 

==Video Memory Address (VMA)==

The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:

{| class="wikitable"
|-
!Video Memory Address
!Signal source
!Signal name
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

 

=== Overscan bits ===

It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

{| class="wikitable"
|+ CRTC Display Start Address
|-
! colspan="8" | Register 12
! colspan="8" | Register 13
|-
! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
| colspan="2" | Unused
| colspan="2" | Video Page
| colspan="2" | Page Size
| colspan="10" | Start Address (1024 positions)
|}

{| style="white-space: nowrap;"
|-
|
{| class="wikitable" style="margin-right: 32px"
|-
! Bit 13 !! Bit 12 !! Video Page
|-
| 0 || 0 || 0000 - 3FFF
|-
| 0 || 1 || 4000 - 7FFF
|-
| 1 || 0 || 8000 - BFFF
|-
| 1 || 1 || C000 - FFFF
|}
|
{| class="wikitable"
|-
! Bit 11 !! Bit 10 !! Page Size
|-
| 0 || 0 || 16KB
|-
| 0 || 1 || 16KB
|-
| 1 || 0 || 16KB
|-
| 1 || 1 || '''32KB'''
|}
|}

 

=== Coarse hardware scrolling ===

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

*To move right: <code>start_address := start_address + 1</code>
*To move left: <code>start_address := start_address - 1</code>
*To move down: <code>start_address := start_address + R1</code>
*To move up: <code>start_address := start_address - R1</code>

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984.

The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input:

<pre>
10 ma%=0
20 IF INKEY(1)=0 THEN GOSUB 100
30 IF INKEY(2)=0 THEN GOSUB 300
40 IF INKEY(8)=0 THEN GOSUB 500
50 IF INKEY(0)=0 THEN GOSUB 700
60 GOTO 20
100 ' right
110 ma%=ma%+1: GOSUB 900: RETURN
300 ' down
310 ma%=ma%+40: GOSUB 900: RETURN
500 ' left
510 ma%=ABS(ma%-1): GOSUB 900: RETURN
700 ' up
710 ma%=ABS(ma%-40): GOSUB 900: RETURN
900 ' set R12 and R13
910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%
930 RETURN
</pre>

Which looks like the following:

[[File:CRTC-Coarse-scroll.gif]]

 

=== Advanced hardware scrolling ===

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993.

Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there].

 

== Split screen (aka Rupture) ==

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]

And this is basically the bread and butter of innumerable CPC demos.

Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
* changes to the screen address have to be done anywhere in the previous split
* changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
* changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:
*reg 0 (63) = x-screenwidth (usually always 63)
*reg 1 (50) = x-splitwidth (e.g.50)
*reg 2 (51) = x-splitstart (e.g. 51)
*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
*reg 4 (##) = y-splitheight-1 (set this inside the current split)
*reg 5 (00) = y-finestart
*reg 6 (25) = y-max visible splitpart (same like 4)
*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
*reg 9 (07) = y-lines/char-1

Set this inside the previous split:
*reg12 (##) = address high (char / 256 + block * 16)
*reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas.

Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)]

 

== CUDISP (aka CURSOR) ==

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.

 

== DISPTMG (aka Display Enable) ==

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

 

=== HBORDER ===

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

 

=== VBORDER ===

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

 

=== SBORDER ===

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]].

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

 

=== Border bytes ===

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:
<pre>
BORDER 6:OUT &BC00,6:OUT &BD00,0
</pre>

 

== HSYNC ==

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

=== Contiguous HSYNCs ===

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

=== Signal delay ===

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

=== Discolouration effect ===

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

=== Screen wobbling and Fine horizontal hardware scroll ===

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

[[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

 

== VSYNC ==

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

=== Blocked VSYNC ===

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

=== Ghost VSYNC ===

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

=== PPI VSYNC ===

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

=== Subpixel vertical hardware scroll ===

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

=== Mid-VSYNC ===

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

 

== Interlace modes ==

Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

[[File:CRTC Interlace modes.png]]

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

=== Interlace sync mode (ISM) ===

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

=== Interlace sync and video mode (IVM) ===

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

=== Interlace adjustment line ===

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

 

== CRTC registers ==

The Internal registers of the 6845 are:

{| class="wikitable"
|-
!rowspan=2|Register Index
!rowspan=2|Register Name
!colspan=3|Read/Write
!rowspan=2|Range
!rowspan=2|CPC Setting
!rowspan=2|Notes
|-
!CRTC 0
!CRTCs 1/2
!CRTCs 3/4
|-
|0||Horizontal Total (-1)||colspan=3 style="text-align: center;"|Write||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||colspan=3 style="text-align: center;"|Write||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||colspan=3 style="text-align: center;"|Write||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||colspan=3 style="text-align: center;"|Write||VVVVHHHH||128+14||VSync width in scan-lines (Not present on all CRTCs, fixed to 16 lines on these) ; HSync pulse width in characters.
|-
|4||Vertical Total (-1)||colspan=3 style="text-align: center;"|Write||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||colspan=3 style="text-align: center;"|Write||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||colspan=3 style="text-align: center;"|Write||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync Position||colspan=3 style="text-align: center;"|Write||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||colspan=3 style="text-align: center;"|Write||CCDDxxII||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4). DD: Display Skew (Only in CRTCs 0, 3 and 4). II: Interlace Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored.
|-
|10||Cursor Start Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx00000||0||Sets last raster row of character that cursor is on to invert.
|-
|12||Display Start Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).
|-
|13||Display Start Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0||
|-
|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.
|-
|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.
|-
|}

 

=== Screen size ===

We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2 to have the screen size in bytes.

With the default CRTC values, we obtain 40 x 25 x (7+1) x 2 = 16000 bytes.

So we can observe that only part of the 16384 bytes (=16KB) page of VRAM is actually displayed on screen.

 

=== Register access ===

On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.

On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.

On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:
* On CRTCs 0/2, registers 18-31 read as 0
* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF

On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:

{| class="wikitable"
!Nb
!Register
!Definition
|-
|0||R16||Light Pen Address (High)
|-
|1||R17||Light Pen Address (Low)
|-
|2||R10||Cursor Start Raster
|-
|3||R11||Cursor End Raster
|-
|4||R12||Display Start Address (High)
|-
|5||R13||Display Start Address (Low)
|-
|6||R14||Cursor Address (High)
|-
|7||R15||Cursor Address (Low)
|}

 

== CRTC register differences ==

CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]].

 

=== R10/R11 on ASIC/Pre-ASIC ===

The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write.

{| class="wikitable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}

{| class="wikitable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}

 

=== Horizontal and Vertical Sync (R3) ===

Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

 

=== Interlace and Skew (R8) ===

Types 0/3/4:
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.

 

=== R31 on Type 1 ===

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

 

=== Status register on Type 1 ===

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

 

== CRTC Type Detection ==
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>

Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.

 

== CRTC Timing Diagrams ==
[[File:CRTC Timing Diagram Rockwell.png]]

 

[[File:CRTC timing small.gif]]

 

== Internal Counters ==

{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Compared with
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|R0, R1, R2
| Increments on every clock cycle
|-
|Horizontal Sync Counter
|HSC
|C3l
|R3l
|
|-
|Vertical Character Counter
|VCC
|C4
|R4, R6, R7
|
|-
|Vertical Sync Counter
|VSC
|C3h
|R3h
|R3h is fixed to 0 on CRTCs 1/2. This gives 16 lines of VSYNC
|-
|Vertical Line Counter
|VLC
|C9
|R9, R10, R11
|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5
|R5
|This counter does not exist on CRTCs 0/3/4. C9 is reused instead
|-
|Frame Counter
|FC
|
|
|Used to alternate frames in interlace and for CRTC cursor blinking
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}

When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).

 

== CRTC counter differences ==

=== MA buffering ===

No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.

At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.

CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.

 

=== MA reload ===

On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.

On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.

On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.

==== Rupture For Dummies (R5 bug) ====

CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.

This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.

The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.

This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].

 

=== VSC (C3h) overflow ===

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

 

=== HSC (C3l) overflow ===

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

 

=== VCC (C4) overflow ===

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

 

=== HCC (C0) overflow ===

If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

 

=== VLC (C9) overflow ===

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== VTAC (C5/C9) overflow ===

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== Vertical Adjustment mode ===

On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.

On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.

On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.

Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.

 

=== Counter freezes ===

On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.

On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.

 

== Block Diagrams ==

{| class="wikitable"
|-
!Hitachi
!UMC
!Motorola
|-
|[[File:CRTC Block Diagram.png|Hitachi]]
|[[File:UMC CRTC Block Diagram.png|UMC]]
|[[File:Motorola CRTC Block Diagram.png|Motorola]]
|}

 

== CRTC-II (aka Type 5) ==

The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]

 

== Datasheets ==

==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)

 

==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory. It is used in the [[Aleste 520EX]].
* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
* [[Media:VL6845 VTi.pdf|VL6845]] by VTi
* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast
* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845
* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features
* [[Media:Mos 6545-1 crtc.pdf|MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845. Its differences are found in the R8 register.
* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845

 

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

 

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]

 

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

*[[VIDI digitizer]] This extension contains its own CRTC chip

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

CRTC

2025-05-18T19:50:31Z

Longshot: /* Links */

[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]

The 6845 '''CRTC''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC.

This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode.

It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.

NOTES:
* This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
* Much information has been drawn from the [https://shaker.logonsystem.eu/ CRTC Compendium] documentation, condensed and rearranged for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentation.

 

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{| class="wikitable"
|-
!Part number
!Manufacturer
!Type number (note 3)
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|AMS40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 Plus, 6128 Plus and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported

 

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register||Write only
|-
|&BExx||0||1||0||
* CRTCs 0/2: —
* CRTC 1: Read Status Register
* CRTCs 3/4: Read from selected internal 6845 register
||Read only
|-
|&BFxx||0||1||1||Read from selected internal 6845 register||Read only
|-
|}

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

 

=== Z80 I/O access timings ===

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

{| class="wikitable"
|+
! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4
|-
| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec
|-
| OUTI || 5 µsec || 5th µsec || 5th µsec
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}

 

==Video Memory Address (VMA)==

The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:

{| class="wikitable"
|-
!Video Memory Address
!Signal source
!Signal name
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

 

=== Overscan bits ===

It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

{| class="wikitable"
|+ CRTC Display Start Address
|-
! colspan="8" | Register 12
! colspan="8" | Register 13
|-
! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
| colspan="2" | Unused
| colspan="2" | Video Page
| colspan="2" | Page Size
| colspan="10" | Start Address (1024 positions)
|}

{| style="white-space: nowrap;"
|-
|
{| class="wikitable" style="margin-right: 32px"
|-
! Bit 13 !! Bit 12 !! Video Page
|-
| 0 || 0 || 0000 - 3FFF
|-
| 0 || 1 || 4000 - 7FFF
|-
| 1 || 0 || 8000 - BFFF
|-
| 1 || 1 || C000 - FFFF
|}
|
{| class="wikitable"
|-
! Bit 11 !! Bit 10 !! Page Size
|-
| 0 || 0 || 16KB
|-
| 0 || 1 || 16KB
|-
| 1 || 0 || 16KB
|-
| 1 || 1 || '''32KB'''
|}
|}

 

=== Coarse hardware scrolling ===

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

*To move right: <code>start_address := start_address + 1</code>
*To move left: <code>start_address := start_address - 1</code>
*To move down: <code>start_address := start_address + R1</code>
*To move up: <code>start_address := start_address - R1</code>

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984.

The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input:

<pre>
10 ma%=0
20 IF INKEY(1)=0 THEN GOSUB 100
30 IF INKEY(2)=0 THEN GOSUB 300
40 IF INKEY(8)=0 THEN GOSUB 500
50 IF INKEY(0)=0 THEN GOSUB 700
60 GOTO 20
100 ' right
110 ma%=ma%+1: GOSUB 900: RETURN
300 ' down
310 ma%=ma%+40: GOSUB 900: RETURN
500 ' left
510 ma%=ABS(ma%-1): GOSUB 900: RETURN
700 ' up
710 ma%=ABS(ma%-40): GOSUB 900: RETURN
900 ' set R12 and R13
910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%
930 RETURN
</pre>

Which looks like the following:

[[File:CRTC-Coarse-scroll.gif]]

 

=== Advanced hardware scrolling ===

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993.

Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there].

 

== Split screen (aka Rupture) ==

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]

And this is basically the bread and butter of innumerable CPC demos.

Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
* changes to the screen address have to be done anywhere in the previous split
* changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
* changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:
*reg 0 (63) = x-screenwidth (usually always 63)
*reg 1 (50) = x-splitwidth (e.g.50)
*reg 2 (51) = x-splitstart (e.g. 51)
*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
*reg 4 (##) = y-splitheight-1 (set this inside the current split)
*reg 5 (00) = y-finestart
*reg 6 (25) = y-max visible splitpart (same like 4)
*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
*reg 9 (07) = y-lines/char-1

Set this inside the previous split:
*reg12 (##) = address high (char / 256 + block * 16)
*reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas.

Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)]

 

== CUDISP (aka CURSOR) ==

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.

 

== DISPTMG (aka Display Enable) ==

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

 

=== HBORDER ===

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

 

=== VBORDER ===

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

 

=== SBORDER ===

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]].

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

 

=== Border bytes ===

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:
<pre>
BORDER 6:OUT &BC00,6:OUT &BD00,0
</pre>

 

== HSYNC ==

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

=== Contiguous HSYNCs ===

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

=== Signal delay ===

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

=== Discolouration effect ===

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

=== Screen wobbling and Fine horizontal hardware scroll ===

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

[[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

 

== VSYNC ==

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

=== Blocked VSYNC ===

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

=== Ghost VSYNC ===

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

=== PPI VSYNC ===

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

=== Subpixel vertical hardware scroll ===

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

=== Mid-VSYNC ===

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

 

== Interlace modes ==

Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

[[File:CRTC Interlace modes.png]]

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

=== Interlace sync mode (ISM) ===

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

=== Interlace sync and video mode (IVM) ===

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

=== Interlace adjustment line ===

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

 

== CRTC registers ==

The Internal registers of the 6845 are:

{| class="wikitable"
|-
!rowspan=2|Register Index
!rowspan=2|Register Name
!colspan=3|Read/Write
!rowspan=2|Range
!rowspan=2|CPC Setting
!rowspan=2|Notes
|-
!CRTC 0
!CRTCs 1/2
!CRTCs 3/4
|-
|0||Horizontal Total (-1)||colspan=3 style="text-align: center;"|Write||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||colspan=3 style="text-align: center;"|Write||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||colspan=3 style="text-align: center;"|Write||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||colspan=3 style="text-align: center;"|Write||VVVVHHHH||128+14||VSync width in scan-lines (Not present on all CRTCs, fixed to 16 lines on these) ; HSync pulse width in characters.
|-
|4||Vertical Total (-1)||colspan=3 style="text-align: center;"|Write||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||colspan=3 style="text-align: center;"|Write||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||colspan=3 style="text-align: center;"|Write||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync Position||colspan=3 style="text-align: center;"|Write||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||colspan=3 style="text-align: center;"|Write||CCDDxxII||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4). DD: Display Skew (Only in CRTCs 0, 3 and 4). II: Interlace Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored.
|-
|10||Cursor Start Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx00000||0||Sets last raster row of character that cursor is on to invert.
|-
|12||Display Start Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).
|-
|13||Display Start Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0||
|-
|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.
|-
|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.
|-
|}

 

=== Screen size ===

We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2 to have the screen size in bytes.

With the default CRTC values, we obtain 40 x 25 x (7+1) x 2 = 16000 bytes.

So we can observe that only part of the 16384 bytes (=16KB) page of VRAM is actually displayed on screen.

 

=== Register access ===

On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.

On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.

On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:
* On CRTCs 0/2, registers 18-31 read as 0
* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF

On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:

{| class="wikitable"
!Nb
!Register
!Definition
|-
|0||R16||Light Pen Address (High)
|-
|1||R17||Light Pen Address (Low)
|-
|2||R10||Cursor Start Raster
|-
|3||R11||Cursor End Raster
|-
|4||R12||Display Start Address (High)
|-
|5||R13||Display Start Address (Low)
|-
|6||R14||Cursor Address (High)
|-
|7||R15||Cursor Address (Low)
|}

 

== CRTC register differences ==

CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]].

 

=== R10/R11 on ASIC/Pre-ASIC ===

The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write.

{| class="wikitable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}

{| class="wikitable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}

 

=== Horizontal and Vertical Sync (R3) ===

Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

 

=== Interlace and Skew (R8) ===

Types 0/3/4:
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.

 

=== R31 on Type 1 ===

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

 

=== Status register on Type 1 ===

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

 

== CRTC Type Detection ==
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>

Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.

 

== CRTC Timing Diagrams ==
[[File:CRTC Timing Diagram Rockwell.png]]

 

[[File:CRTC timing small.gif]]

 

== Internal Counters ==

{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Compared with
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|R0, R1, R2
| Increments on every clock cycle
|-
|Horizontal Sync Counter
|HSC
|C3l
|R3l
|
|-
|Vertical Character Counter
|VCC
|C4
|R4, R6, R7
|
|-
|Vertical Sync Counter
|VSC
|C3h
|R3h
|R3h is fixed to 0 on CRTCs 1/2. This gives 16 lines of VSYNC
|-
|Vertical Line Counter
|VLC
|C9
|R9, R10, R11
|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5
|R5
|This counter does not exist on CRTCs 0/3/4. C9 is reused instead
|-
|Frame Counter
|FC
|
|
|Used to alternate frames in interlace and for CRTC cursor blinking
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}

When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).

 

== CRTC counter differences ==

=== MA buffering ===

No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.

At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.

CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.

 

=== MA reload ===

On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.

On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.

On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.

==== Rupture For Dummies (R5 bug) ====

CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.

This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.

The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.

This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].

 

=== VSC (C3h) overflow ===

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

 

=== HSC (C3l) overflow ===

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

 

=== VCC (C4) overflow ===

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

 

=== HCC (C0) overflow ===

If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

 

=== VLC (C9) overflow ===

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== VTAC (C5/C9) overflow ===

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== Vertical Adjustment mode ===

On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.

On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.

On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.

Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.

 

=== Counter freezes ===

On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.

On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.

 

== Block Diagrams ==

{| class="wikitable"
|-
!Hitachi
!UMC
!Motorola
|-
|[[File:CRTC Block Diagram.png|Hitachi]]
|[[File:UMC CRTC Block Diagram.png|UMC]]
|[[File:Motorola CRTC Block Diagram.png|Motorola]]
|}

 

== CRTC-II (aka Type 5) ==

The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]

 

== Datasheets ==

==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)

 

==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory. It is used in the [[Aleste 520EX]].
* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
* [[Media:VL6845 VTi.pdf|VL6845]] by VTi
* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast
* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845
* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features
* [[Media:Mos 6545-1 crtc.pdf|MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845. Its differences are found in the R8 register.
* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845

 

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

 

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]

 

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

*[[VIDI digitizer]] This extension contains its own CRTC chip

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

CRTC

2025-05-18T19:46:47Z

Longshot: /* Rupture For Dummies (R5 bug) */

[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]

The 6845 '''CRTC''' (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the [[Gate Array]] to generate the video signal on the Amstrad CPC.

This chip is also used in the [[BBC Micro]], [[Lynx|Camputers Lynx]], [[EG2000 Colour Genie]], [[Sharp X1]], [[MicroBee]], [[Commodore PET]] and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for [[IBM PC]]. And it is found in some [https://www.msx.org/wiki/Hitachi_HD6845 MSX1 expansions], providing an 80-column text mode.

It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.

NOTES:
* This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
* Much information has been drawn from the [https://shaker.logonsystem.eu/ CRTC Compendium] documentation, condensed and rearranged for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentation.

 

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{| class="wikitable"
|-
!Part number
!Manufacturer
!Type number (note 3)
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|AMS40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 Plus, 6128 Plus and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported

 

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

{| class="wikitable"
|-
!I/O port address
!/CS (A14)
!R/W (A9)
!RS (A8)
!Function
!Read/Write
|-
|&BCxx||0||0||0||Select 6845 register||Write only
|-
|&BDxx||0||0||1||Write to selected internal 6845 register||Write only
|-
|&BExx||0||1||0||
* CRTCs 0/2: —
* CRTC 1: Read Status Register
* CRTCs 3/4: Read from selected internal 6845 register
||Read only
|-
|&BFxx||0||1||1||Read from selected internal 6845 register||Read only
|-
|}

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

 

=== Z80 I/O access timings ===

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

{| class="wikitable"
|+
! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4
|-
| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec
|-
| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec
|-
| OUTI || 5 µsec || 5th µsec || 5th µsec
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}

 

==Video Memory Address (VMA)==

The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:

{| class="wikitable"
|-
!Video Memory Address
!Signal source
!Signal name
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

 

=== Overscan bits ===

It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

{| class="wikitable"
|+ CRTC Display Start Address
|-
! colspan="8" | Register 12
! colspan="8" | Register 13
|-
! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8
! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0
|-
| colspan="2" | Unused
| colspan="2" | Video Page
| colspan="2" | Page Size
| colspan="10" | Start Address (1024 positions)
|}

{| style="white-space: nowrap;"
|-
|
{| class="wikitable" style="margin-right: 32px"
|-
! Bit 13 !! Bit 12 !! Video Page
|-
| 0 || 0 || 0000 - 3FFF
|-
| 0 || 1 || 4000 - 7FFF
|-
| 1 || 0 || 8000 - BFFF
|-
| 1 || 1 || C000 - FFFF
|}
|
{| class="wikitable"
|-
! Bit 11 !! Bit 10 !! Page Size
|-
| 0 || 0 || 16KB
|-
| 0 || 1 || 16KB
|-
| 1 || 0 || 16KB
|-
| 1 || 1 || '''32KB'''
|}
|}

 

=== Coarse hardware scrolling ===

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

*To move right: <code>start_address := start_address + 1</code>
*To move left: <code>start_address := start_address - 1</code>
*To move down: <code>start_address := start_address + R1</code>
*To move up: <code>start_address := start_address - R1</code>

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984.

The following BASIC program demonstrates the coarse scrolling by setting the R12 and R13 registers based on keyboard input:

<pre>
10 ma%=0
20 IF INKEY(1)=0 THEN GOSUB 100
30 IF INKEY(2)=0 THEN GOSUB 300
40 IF INKEY(8)=0 THEN GOSUB 500
50 IF INKEY(0)=0 THEN GOSUB 700
60 GOTO 20
100 ' right
110 ma%=ma%+1: GOSUB 900: RETURN
300 ' down
310 ma%=ma%+40: GOSUB 900: RETURN
500 ' left
510 ma%=ABS(ma%-1): GOSUB 900: RETURN
700 ' up
710 ma%=ABS(ma%-40): GOSUB 900: RETURN
900 ' set R12 and R13
910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%
930 RETURN
</pre>

Which looks like the following:

[[File:CRTC-Coarse-scroll.gif]]

 

=== Advanced hardware scrolling ===

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993.

Everything you need to know about hardware scrolling on CPC can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there].

 

== Split screen (aka Rupture) ==

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source]

And this is basically the bread and butter of innumerable CPC demos.

Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:
* changes to the screen address have to be done anywhere in the previous split
* changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
* changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:
*reg 0 (63) = x-screenwidth (usually always 63)
*reg 1 (50) = x-splitwidth (e.g.50)
*reg 2 (51) = x-splitstart (e.g. 51)
*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
*reg 4 (##) = y-splitheight-1 (set this inside the current split)
*reg 5 (00) = y-finestart
*reg 6 (25) = y-max visible splitpart (same like 4)
*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
*reg 9 (07) = y-lines/char-1

Set this inside the previous split:
*reg12 (##) = address high (char / 256 + block * 16)
*reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas.

Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)]

 

== CUDISP (aka CURSOR) ==

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.

 

== DISPTMG (aka Display Enable) ==

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

 

=== HBORDER ===

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

 

=== VBORDER ===

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

 

=== SBORDER ===

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]].

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

 

=== Border bytes ===

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:
<pre>
BORDER 6:OUT &BC00,6:OUT &BD00,0
</pre>

 

== HSYNC ==

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

=== Contiguous HSYNCs ===

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

=== Signal delay ===

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

=== Discolouration effect ===

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

=== Screen wobbling and Fine horizontal hardware scroll ===

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

[[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

 

== VSYNC ==

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

=== Blocked VSYNC ===

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

=== Ghost VSYNC ===

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

=== PPI VSYNC ===

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

=== Subpixel vertical hardware scroll ===

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

=== Mid-VSYNC ===

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

 

== Interlace modes ==

Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

[[File:CRTC Interlace modes.png]]

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

=== Interlace sync mode (ISM) ===

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

=== Interlace sync and video mode (IVM) ===

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

=== Interlace adjustment line ===

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

 

== CRTC registers ==

The Internal registers of the 6845 are:

{| class="wikitable"
|-
!rowspan=2|Register Index
!rowspan=2|Register Name
!colspan=3|Read/Write
!rowspan=2|Range
!rowspan=2|CPC Setting
!rowspan=2|Notes
|-
!CRTC 0
!CRTCs 1/2
!CRTCs 3/4
|-
|0||Horizontal Total (-1)||colspan=3 style="text-align: center;"|Write||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||colspan=3 style="text-align: center;"|Write||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||colspan=3 style="text-align: center;"|Write||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||colspan=3 style="text-align: center;"|Write||VVVVHHHH||128+14||VSync width in scan-lines (Not present on all CRTCs, fixed to 16 lines on these) ; HSync pulse width in characters.
|-
|4||Vertical Total (-1)||colspan=3 style="text-align: center;"|Write||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||colspan=3 style="text-align: center;"|Write||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||colspan=3 style="text-align: center;"|Write||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync Position||colspan=3 style="text-align: center;"|Write||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||colspan=3 style="text-align: center;"|Write||CCDDxxII||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4). DD: Display Skew (Only in CRTCs 0, 3 and 4). II: Interlace Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored.
|-
|10||Cursor Start Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx00000||0||Sets last raster row of character that cursor is on to invert.
|-
|12||Display Start Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).
|-
|13||Display Start Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0||
|-
|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.
|-
|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.
|-
|}

 

=== Screen size ===

We can calculate the screen size in words by multiplying R1 x R6 x (R9+1). And then multiplying the result by 2 to have the screen size in bytes.

With the default CRTC values, we obtain 40 x 25 x (7+1) x 2 = 16000 bytes.

So we can observe that only part of the 16384 bytes (=16KB) page of VRAM is actually displayed on screen.

 

=== Register access ===

On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.

On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.

On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:
* On CRTCs 0/2, registers 18-31 read as 0
* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF

On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:

{| class="wikitable"
!Nb
!Register
!Definition
|-
|0||R16||Light Pen Address (High)
|-
|1||R17||Light Pen Address (Low)
|-
|2||R10||Cursor Start Raster
|-
|3||R11||Cursor End Raster
|-
|4||R12||Display Start Address (High)
|-
|5||R13||Display Start Address (Low)
|-
|6||R14||Cursor Address (High)
|-
|7||R15||Cursor Address (Low)
|}

 

== CRTC register differences ==

CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]].

 

=== R10/R11 on ASIC/Pre-ASIC ===

The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write.

{| class="wikitable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}

{| class="wikitable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}

 

=== Horizontal and Vertical Sync (R3) ===

Type 0:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 1:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts).

Type 2:
*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

Types 3/4:
*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.
*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16.

 

=== Interlace and Skew (R8) ===

Types 0/3/4:
*Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
*Bits 3..2 are ignored.
*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:
*Bits 7..2 are ignored.
*Bits 1..0 define the interlace mode.

 

=== R31 on Type 1 ===

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

 

=== Status register on Type 1 ===

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

 

== CRTC Type Detection ==
<pre>
10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"
</pre>

Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input.

 

== CRTC Timing Diagrams ==
[[File:CRTC Timing Diagram Rockwell.png]]

 

[[File:CRTC timing small.gif]]

 

== Internal Counters ==

{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Compared with
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|R0, R1, R2
| Increments on every clock cycle
|-
|Horizontal Sync Counter
|HSC
|C3l
|R3l
|
|-
|Vertical Character Counter
|VCC
|C4
|R4, R6, R7
|
|-
|Vertical Sync Counter
|VSC
|C3h
|R3h
|R3h is fixed to 0 on CRTCs 1/2. This gives 16 lines of VSYNC
|-
|Vertical Line Counter
|VLC
|C9
|R9, R10, R11
|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5
|R5
|This counter does not exist on CRTCs 0/3/4. C9 is reused instead
|-
|Frame Counter
|FC
|
|
|Used to alternate frames in interlace and for CRTC cursor blinking
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}

When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).

 

== CRTC counter differences ==

=== MA buffering ===

No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.

At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.

CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.

 

=== MA reload ===

On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.

On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.

On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.

==== Rupture For Dummies (R5 bug) ====

CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.

This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.

The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.

This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].

 

=== VSC (C3h) overflow ===

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

 

=== HSC (C3l) overflow ===

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

 

=== VCC (C4) overflow ===

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

 

=== HCC (C0) overflow ===

If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

 

=== VLC (C9) overflow ===

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== VTAC (C5/C9) overflow ===

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.

 

=== Vertical Adjustment mode ===

On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.

On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.

On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.

Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.

 

=== Counter freezes ===

On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.

On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.

 

== Block Diagrams ==

{| class="wikitable"
|-
!Hitachi
!UMC
!Motorola
|-
|[[File:CRTC Block Diagram.png|Hitachi]]
|[[File:UMC CRTC Block Diagram.png|UMC]]
|[[File:Motorola CRTC Block Diagram.png|Motorola]]
|}

 

== CRTC-II (aka Type 5) ==

The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC].

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirec.at/2024/05/19/des-crtc5-a-129e/ Source]

 

== Datasheets ==

==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [[Media:UM6845-UMC.pdf|UM6845 (UMC)]] aka Type 0
* [[Media:Um6845r.umc.pdf|UM6845R (UMC)]] aka Type 1
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola)]] aka Type 2
* [[Media:CPC_Plus_Asic_Schematic.GIF|AMS40489 (Amstrad)]] aka Type 3 ([[ASIC]])
* [[AMS40226 (Amstrad)]] aka Type 4 (Pre-ASIC)

 

==== Unused clones ====
* [[CM607P]] a Bulgarian clone made in Pravetz factory. It is used in the [[Aleste 520EX]].
* [[Media:hd6845.hitachi.pdf|HD6845R]] by Hitachi. According to Kevin Thacker, the [[KC Compact]] used HD6845R only.
* [[Media:UM6845E-UMC.pdf|UM6845E]] by UMC
* [[Media:Mc6845.pdf|MC6845-1]] by Motorola
* [[Media:F6845.pdf|F6845]] by Fairchild
* [[Media:EF6845P.pdf|EF6845]] by Thomson Semiconductors
* [[Media:VL6845 VTi.pdf|VL6845]] by VTi
* [[Media:C6845 CRTC (CAST).pdf|C6845]] by Cast
* [[Media:MB89321B FUJ.pdf|MB89321B]] by Fujitsu. It is pin-compatible with the 6845
* [[Media:MB89321A datasheet CRTC.pdf|MB89321A]] by Fujitsu. Enhanced version that adds smooth scroll, screen partitioning, independent scrolling of screen partitions, and other convenient features
* [[Media:Mos 6545-1 crtc.pdf|MOS 6545]] (MOS, Rockwell, Synertek) is pin-compatible with the 6845. Its differences are found in the R8 register.
* [https://www.cpcwiki.eu/forum/other-retro/interesting-discussion-about-the-c128-s-cpm-poor-performance/msg223058/#msg223058 MOS 8563] It is an evolution of the 6545/6845 CRTC chip, with blitter abilities to autonomously perform block memory copies within its dedicated video RAM.
* [https://github.com/hoglet67/BeebFpga/blob/dev/src/common/mc6845.vhd BeebFpga] [https://github.com/MiSTer-devel/Amstrad_MiSTer/blob/master/rtl/UM6845R.v MiSTer] [https://opencores.org/websvn/filedetails?repname=System09&path=%2FSystem09%2Ftrunk%2Frtl%2FVHDL%2Fcrtc6845.vhd OpenCores] Verilog/VHDL implementations of the 6845

 

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker26.dsk]] Shaker - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)

 

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html PulkoMandy's table] [https://www.theoddys.com/acorn/the_6845_crtc/6845%20Variants.xlsx Oddy's table] Differences between CRTC types
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:ACCC1.8-EN.pdf]] [[Media:ACCC1.8-FR.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]

 

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

*[[VIDI digitizer]] This extension contains its own CRTC chip

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

Gate Array

2025-05-18T19:20:30Z

Longshot: /* CSYNC signal */

[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

 

== CSYNC signal ==

The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]
 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Gate Array

2025-05-18T19:19:45Z

Longshot: /* Interrupt generation */

[[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]

Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).

 

== Introduction ==

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.

 

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

 

== Bus arbitration ==

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

 

== DRAM refresh ==

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]

 

== Interrupt generation ==

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.

[https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Source]

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page.

 

== CSYNC signal ==

The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:
* H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

 

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

{| class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
!rowspan=2| Register
!rowspan=2| Description
!rowspan=2| Chip
|-
! 7
! 6
! 5
! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select a color register || Gate Array
|-
| 0 || 1 || x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Gate Array
|-
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

 

== Registers ==

Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.

=== Register PENR (Select a color register) ===

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array PENR register
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register INKR (Change the value of the currently selected color register) ===

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 0 || rowspan="2" | Gate Array INKR register
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) ===

This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration.

==== Graphics mode selection ====

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{| class="wikitable"
!Bit 1
!Bit 0
!Screen mode
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

==== ROM configuration selection ====

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

==== Summary ====

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array RMR register
|-
| 6 || 0
|-
| 5 || - || ''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Graphics Mode selection
|-
| 0 || x
|}

 

=== Register RMR2 (ASIC & Advanced ROM mapping) ===

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0
|-
| 5 || 1
|-
| 4 || x || rowspan="2" |RMR addressing mode
|-
| 3 || x
|-
| 2 || x || rowspan="3" | Physical ROM number (0..7)
|-
| 1 || x
|-
| 0 || x
|}

{| class="wikitable"
|+ RMR addressing modes
!Bit 4
!Bit 3
!Lower ROM
![[ASIC|ASIC I/O page]]
|-
|0
|0
|&0000-&3FFF
|Disabled
|-
|0
|1
|&4000-&7FFF
|Disabled
|-
|1
|0
|&8000-&BFFF
|Disabled
|-
|1
|1
|&0000-&3FFF
|&4000-&7FFF
|}

The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.

 

=== Register MMR (RAM memory mapping) ===

This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]].

Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip.

{| class="wikitable"
!Bit
!Value
!Function
|-
| 7 || 1 || rowspan="2" | Gate Array MMR register
|-
| 6 || 1
|-
| 5 || x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || x
|-
| 3 || x
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7'''
8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

 

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

 

== Video memory structure ==

{| class="wikitable"
!rowspan=2|Graphics Mode
!colspan=8|VRAM byte
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
!6
!5
!4
!3
!2
!1
!0
!1
!2
!3
!4
!5
!6
!7
!8
|-
|0
|A0
|B0
|A2
|B2
|A1
|B1
|A3
|B3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colours
|4 MHz
|160x200, 20-column text
|-
|1
|A0
|B0
|C0
|D0
|A1
|B1
|C1
|D1
|colspan=2 style="text-align: center;"|A
|colspan=2 style="text-align: center;"|B
|colspan=2 style="text-align: center;"|C
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|A0
|B0
|C0
|D0
|E0
|F0
|G0
|H0
|A
|B
|C
|D
|E
|F
|G
|H
|8 pixels in 2 colours
|16 MHz
|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}

 

== Split rasters ==

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

 

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

 

=== Palette sorted by Firmware Colour Numbers ===

The firmware colour palette is sorted by luminance value.

{| class="wikitable"
|-
|-
!Firmware Number
!Hardware Number
!Colour Name
!R %
!G %
!B %
!ASIC
!Colour
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50|| #006||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100|| #00F||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0|| #600||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50|| #606||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0|| #F00||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50|| #F06||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100|| #F0F||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0|| #060||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50|| #066||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100|| #06F||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0|| #660||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||#666||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0|| #F60|| bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50|| #F66||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100|| #F6F||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0|| #0F0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50|| #0F6||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100|| #0FF||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0|| #6F0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50|| #6F6||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100|| #6FF||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0|| #FF0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}

Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.

 

=== Amstrad Colour Names ===

<gallery>
Cpc 6128 master colour chat.jpg|Master colour chart
Cpc 6128 farbtabelle.jpg|Farbtabelle
Cpc 6128 palette des couleurs.jpg|Palette des couleurs
Cpc 6128 tabla de colores.jpg|Tabla de colores
</gallery>

 

=== Palette sorted by Hardware Colour Numbers ===

{| class="wikitable"
|-
!Hardware Number
!Firmware Number
!R %
!G %
!B %
!ASIC
!Colour
!Colour Name
!German Name
!French Name
!Spanish Name
|-
| 0 (40h) || 13 || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 1 (41h) || (13) || 50|| 50|| 50|| #666|| bgcolor="#808080" | || White || Weiß || Blanc || Blanco
|-
| 2 (42h) || 19 || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4 (44h) || 1 || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 5 (45h) || 7 ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 6 (46h) || 10 || 0|| 50|| 50|| #066|| bgcolor="#008080" | || Cyan || Blaugrün || Turquoise || Ciano
|-
| 7 (47h) || 16 ||100|| 50|| 50|| #F66|| bgcolor="#ff8080" | || Pink || Rosa || Rose || Rosa
|-
| 8 (48h) || (7) ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" | || Purple || Purpur || Pourpre || Púrpura
|-
| 9 (49h) || (25) ||100||100|| 50|| #FF6|| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 10 (4Ah) || 24 ||100||100|| 0|| #FF0|| bgcolor="#ffff00" | || Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 11 (4Bh) || 26 ||100||100||100|| #FFF|| bgcolor="#ffffff" | || Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 12 (4Ch) || 6 ||100|| 0|| 0|| #F00|| bgcolor="#ff0000" | || Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 13 (4Dh) || 8 ||100|| 0||100|| #F0F|| bgcolor="#ff00ff" | || Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 14 (4Eh) || 15 ||100|| 50|| 0|| #F60|| bgcolor="#ff8000" | || Orange || Orange || Orange || Naranja
|-
| 15 (4Fh) || 17 ||100|| 50||100|| #F6F|| bgcolor="#ff80ff" | || Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
| 16 (50h) || (1) || 0|| 0|| 50|| #006|| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 17 (51h) || (19) || 0||100|| 50|| #0F6|| bgcolor="#00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino
|-
| 18 (52h) || 18 || 0||100|| 0|| #0F0|| bgcolor="#00ff00" | || Bright Green || Hellgrün || Vert vif || Verde brillante
|-
| 19 (53h) || 20 || 0||100||100|| #0FF|| bgcolor="#00ffff" | || Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
| 20 (54h) || 0 || 0|| 0|| 0|| #000|| bgcolor="#000000" | || Black || Schwarz || Noir || Negro
|-
| 21 (55h) || 2 || 0|| 0||100|| #00F|| bgcolor="#0000ff" | || Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
| 22 (56h) || 9 || 0|| 50|| 0|| #060|| bgcolor="#008000" | || Green || Grün || Vert || Verde
|-
| 23 (57h) || 11 || 0|| 50||100|| #06F|| bgcolor="#0080ff" | || Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
| 24 (58h) || 4 || 50|| 0|| 50|| #606|| bgcolor="#800080" | || Magenta || Magenta || Magenta || Magenta
|-
| 25 (59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
| 26 (5Ah) || 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima
|-
| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo
|-
| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}

 

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details

This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F

 

=== Green Screen Colours ===

On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

==== To calculate the luminance value ====

'''Red'''

*0% => do not add anything
*50% => add 3
*100% => add 6

'''Green'''

*0% => do not add anything
*50% => add 9
*100% => add 18

'''Blue'''

*0% => do not add anything
*50% => add 1
*100% => add 2

 

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]

 

== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]

 

==See also==

*[[Gate Array and ASIC Pin-Outs]]
*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users

*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

*[[Video modes]] : for other informations on colours and pixels.

*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

PAL16L8

2024-05-31T14:45:49Z

Longshot:

The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.

== Fixed version (Gerald) ==
Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.

A14OUT = !( !A14
# !A15 & !Q0 & Q2 );

A15OUT = !( !A15 & !A14
# !A15 & !Q1
# !A15 & !Q0 & !Q2 );

Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q0
# nRESET & A15 & Q0
# nRESET & nIOWR & Q0 );

Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q1
# nRESET & A15 & Q1
# nRESET & nIOWR & Q1 );

Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q2
# nRESET & A15 & Q2
# nRESET & nIOWR & Q2 );

nCAS0 = ( nCAS
# RAMDIS & !nCPU & nCAS0
# !A15 & A14 & !nCPU & Q2 & nCAS0
# A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS1 );

nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
# !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
# !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
# !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );

[[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement

[[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.

== Initial replacement equation (Porchy) ==

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

A15OUT = (!X2 & !X1 & A14
# !X3 & !X2 & A14
# A15);

!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
# !X1 & RESET & IOWR
# !X1 & !D7ANDD6 & RESET
# !X1 & A15 & RESET);

!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
# !X2 & RESET & IOWR
# !X2 & !D7ANDD6 & RESET
# !X2 & A15 & RESET);

!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
# !X3 & RESET & IOWR
# !X3 & !D7ANDD6 & RESET
# !X3 & A15 & RESET);

!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
# !NCAS & CAS0 & !CAS1);

!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
# X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
# !X3 & A15 & !NCAS & !RAMDIS & CAS1
# !X1 & !A14 & !NCAS & !RAMDIS & CAS1
# !X3 & !A14 & !NCAS & !RAMDIS & CAS1
# !NCAS & !RAMDIS & CPU & CAS1
# !NCAS & !CAS0 & CAS1);

A14OUT = (A15 & A14
# !X1 & A14
# X3 & A14);

[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum

== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the Gate Array can only access the Base 64k page of RAM.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|colspan=2|'''MMR'''||colspan=3|'''64K page'''||'''S'''||colspan=2|'''MM'''||colspan=4 style="text-align: center;"|'''CPU Memory Mapping'''
|-
|'''7'''
|'''6'''
|'''5'''
|'''4'''
|'''3'''
|'''2'''
|'''1'''
|'''0'''
|style="text-align: center;"|'''&0000-&3fff'''
|style="text-align: center;"|'''&4000-&7fff'''
|style="text-align: center;"|'''&8000-&bfff'''
|style="text-align: center;"|'''&c000-&ffff'''
|-
|1
|1
|colspan=3 style="text-align: center;"|x
|0
|0
|0
|Base 64k / Bank 0
|Base 64k / Bank 1
|Base 64k / Bank 2
|Base 64k / Bank 3
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|0
|1
|Base 64k / Bank 0
|Base 64k / Bank 1
|Base 64k / Bank 2
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|1
|0
|'''Page p / Bank 0'''
|'''Page p / Bank 1'''
|'''Page p / Bank 2'''
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|0
|1
|1
|Base 64k / Bank 0
|'''Base 64k / Bank 3'''
|Base 64k / Bank 2
|'''Page p / Bank 3'''
|-
|1
|1
|colspan=3 style="text-align: center;"|p
|1
|colspan=2 style="text-align: center;"|b
|Base 64k / Bank 0
|'''Page p / Bank b'''
|Base 64k / Bank 2
|Base 64k / Bank 3
|}

== PAL I/O port ==

Note that no settings are stored in the Gate Array regarding register 3, but the PAL and Gate Array share an I/O port address.

Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4.
It must be at 1 on CRTCs 0, 1 and 2 (The result is not guaranteed).

For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.

== PAL Type Detection ==
<pre>
10 OUT &7F00,&C0:POKE &4000,&C0
20 OUT &7F00,&C7:POKE &4000,&C7:OUT &7F00,&C0
30 IF PEEK(&4000)=&C7 THEN PRINT"PAL chip absent/inactive":END
40 OUT &3FFF,&C7
50 IF PEEK(&4000)=&C7 THEN PRINT"PAL I/O layout Bit 14=0 PAL Select":END
60 IF PEEK(&4000)=&C0 THEN PRINT"PAL I/O layout Bit 14=0 PAL not selected":END
70 PRINT"Error!"
</pre>

== See also ==

*CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]

*[[Gate Array and ASIC Pin-Outs]]

*[[Standard Memory Expansions]]

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:Datasheet]]

Longshot

2023-12-06T17:16:08Z

Longshot: update url logonsystem portal

[[Image:Longshot1996.jpg|thumb|Longshot 1996]]

'''Longshot''' was a demo coder, founder and leader of the famous [[Logon System]] demo group. A pseudonym for Serge Querné, he was initially based in southern France but later moved to Paris.

== Biography ==

Initially going under the pseudonym 'Logon 1' (the name Logon he explained in a scrolltext as "a Belgian idea"), he released a series of single-part demos, each of them showcasing a new technique he had learned ‒ or, in many cases, discovered. These included raster bars, overscan, and split modes in the earliest productions. The first demo was coded while he was working at [http://fr.wikipedia.org/wiki/Ubisoft Ubi Soft]'s "castle" headquarters. Though some of these demos seem fairly simple in retrospect, at the time, Serge's demo-coding skill was only equalled by perhaps [[Fefesse]] and [[NWC]].

A stepchange came with the [[Longshot Demo]], the first in which he adopted his new pseudonym. This included hardware splitting and combined more effects on screen at once. [[Revolog]] (or Revolution) followed in a similar vein but was a level more accomplished again. At the same time, Longshot participated in the [[Amazing Demo]] with [[Naminu]] and [[P007]] of [[Malibu Crackers]].

[[Naminu]] would soon become one of the members of the new, expanded [[Logon System]]. The "supergroup"'s first release was the stunning [[The Demo]], where Longshot contributed three parts but, perhaps more significantly, oversaw the polished, coherent design that was unlike any CPC megademo previously released.

The [[Euromeeting Demo]] would turn out to be his last demo release, but a further innovation was the [[B-ASIC]] utility which enabled Plus programmers to use the new features of their machines from BASIC. Longshot went on to the PC in turn, but has recently participated in French CPC forums such as [http://phenixinformatique.free.fr/ Phenix Informatique] once again. His [http://www.logonsystem.fr/ homepage] contains screenshots from the Logon era, a brief history, and downloads of his personal disc collection.

Though most respected for his coding skills and innovations, Serge's main achievement was perhaps the creation and fostering of the Logon System supergroup, the like of which has not been seen since.

Longshot has written technical articles in some columns of the French magazine [[Amstrad Cent Pour Cent]].

== Demos ==

* [[Logon Demo 1]]
* [[Logon Demo 2]]
* [[Logon Demo 3]]
* [[Logon Demo 5]]
* [[Longshot Demo]]
* [[Revolog]]
* [[Amazing Demo]]
* [[The Demo]]
* [[Euromeeting Demo]]

== Other productions ==

* [[Atlantis]]
* [[B-ASIC]]
* [[AntiMultiface]]
* [[MagicDOS]]

== Groups ==

* [[Logon System]]

== Links ==

* [http://www.logonsystem.eu/ Longshot's homepage]
* [http://norecess.cpcscene.net/interview-longshot.html Interview with Longshot by NoRecess]

[[Category:CPC scene members]]

Emulator IDs

2023-11-08T22:12:16Z

Longshot:

Some CPC emulators use Port &FEFE to provide a method to identify a specific CPC emulator. CPC programs could use this ID to detect an emulator and change some of their behaviour (e.g. changing graphic effechts which will not work on an emulator or using special emulator-specific features). Reading from this port returns the Emulator-ID or &FF on the real CPC and on emulators which do not provide this feature.

== List of known Emulator-IDs ==
<pre>
- #78: Amspirit
- #88: VirtualCPC
- #99: WinCPC
- #A0: JavaCPC
- #AA: PC-CPC
- #C0: C-One Normal
- #C1: C-One Turbo
- #C2: TREX Normal
- #C3: TREX Turbo
- #CE: CPCE
- #FF: Caprice, WinApe, MESS or a real CPC
</pre>
NOTE: It should be noted that the value #FF is just valid on a bare CPC (not plus!) and any extensions connected can change this!
[[Category:Emulator]] [[Category:Programming]]

Emulators

2023-09-20T11:22:29Z

Longshot: /* Desktop */

= Vote for your favorite emulator =

[https://www.cpcwiki.eu/forum/emulators/which-emulator-s-do-you-use/ There is a poll on CPCWiki forum]

= Software Platforms (Full OS independance) =

== Java Platform ==

{| class="wikitable sortable"
! Emulator name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[Arnold Jnr|Arnold Jnr]]
| [https://web.archive.org/web/20160727011826/http://www.arnoldemu.freeserve.co.uk/]
|
| Aug 27, 2001
| ❌
| ❌
| -
| Open source
|-
| [[JavaCPC|JavaCPC Desktop]]
| [https://sourceforge.net/projects/javacpc/] [http://sourceforge.net/projects/javagx4000/ JavaGX4000] [http://sourceforge.net/projects/cpcinajar/ CPCInAJar]
| 3.0.2
| Apr 8, 2022
| ✅
| ✅
| [[KC Compact]]
| Donationware & Open source
|-
| [[JEMU|JEMU]]
| [http://jemu.winape.net/]
|
| Feb 19, 2007
| ❌
| ❌
| [[BBC Micro]], [[ZX Spectrum]], [[ZX80/81]], [[VZ-300]]
| Open source
|-
| [[WebCPC|WebCPC]]
| [http://sourceforge.net/projects/webcpc/] [https://web.archive.org/web/20110903132520/http://java.cpc-live.com/ JavaCPC Applet]
| r15
| Dec 31, 2010
| ❌
| ❌
| -
| Open source
|}

== JS / Wasm / Web Platform ==

{| class="wikitable sortable"
|-
! Emulator name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[CPCBox|CPCBox]]
| [https://web.archive.org/web/20190702084943/http://www.cpcbox.com/] [https://bzhgames.xyz/index.php BZH Games]
| beta
| Dec 28, 2013
| ❌
| ❌
| -
| Freeware
|-
| [[CrocoDS|CrocoDS]]
| [http://crocods.org/web/]
|
| May 13, 2020
| ⚠️
| ❌
| -
| Freeware
|-
| [[MAME|Emularity (MAME)]]
| [https://github.com/db48x/emularity] [http://jsmess.textfiles.com/ JSMESS]
[https://archive.org/details/softwarelibrary_cpc_games CPC Games] [https://archive.org/details/softwarelibrary_cpc_demos CPC Demos] on Internet Archive
|
| Jul 15, 2023
| ❌
| ✅
| Lots of other computer systems
| Open source
|-
| [[Roland javascript emulator|Roland]]
| [https://web.archive.org/web/20190308142014/http://roland.retrolandia.net/]
|
| Sep 24, 2011
| ❌
| ❌
| -
| Open source
|-
| [[Ronald|Ronald]]
| [https://github.com/mdm/ronald]
|
| May 10, 2023
| ⚠️
| ❌
| -
| Open source
|-
| [[RVMplayer|RVMplayer]]
| [https://www.retrovirtualmachine.org/rvmplayer/]
| 0.1.1
| Apr 29, 2023
| ❌
| ❌
| [[ZX Spectrum]]
| Freeware
|-
| [[Tiny Emus]]
| [https://floooh.github.io/tiny8bit/] [https://floooh.github.io/tiny8bit/cpc-ui.html] [http://floooh.github.io/virtualkc/ yakc]
[https://devilmarkus.de/ WebGL 3d 8-bit] [https://www.amstradcpcgames.eu/ Amstrad CPC Games] [http://cpc.novidee.com/ zpz]
|
| Dec 15, 2021
| ✅
| ❌
| [[KC Compact]], [[ZX Spectrum]], [[VIC-20]], [[Commodore 64]], [[Acorn Atom]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]], [[LC80]]
| Open source
|-
| [[Griffin CPC emulator|Xiragon]]
| [https://web.archive.org/web/20191027200008/http://xiragon.com/]
|
| Nov 28, 2012
| ❌
| ❌
| -
| Open source
|}

== LibRetro (API for emulators) ==

{| class="wikitable sortable"
! Emulator name
! Type
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[libretro-cap32]]
| Emulation core
| [https://github.com/libretro/libretro-cap32]
| 4.5.3
| Mar 16, 2022
| ❌
| ✅
| -
| Open source
|-
| [[libretro-crocods]]
| Emulation core
| [https://github.com/libretro/libretro-crocods]
| 0.1
| Feb 28, 2017
| ❌
| ❌
| -
| Open source
|-
| [[MAME|MESS 2015]]
| Emulation core
| [https://docs.libretro.com/meta/core-list/]
| 0.160
| circa 2015
| ❌
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| [[SugarLibRetro]]
| Emulation core
| [https://github.com/Tom1975/SugarLibRetro] (wraps independent lib [https://github.com/Tom1975/CPCCore CPCCore])
| git
| Jan 10, 2020
| ❌
| ✅
| -
| Open source
|-
| [[EmuVR]]
| Frontend
| [https://www.emuvr.net/]
|
| Dec 25, 2022
| ❌
| -
| Depends on emulation cores
| Donationware
|-
| [[Hackable Console]]
| Frontend
| [https://github.com/leiradel/hackable-console]
|
| Mar 27, 2022
| ✅
| -
| Depends on emulation cores
| Open source
|-
| [[RetroArch]]
| Frontend
| [https://www.retroarch.com/]
| 1.15.0
| Mar 11, 2023
| ❌
| -
| Depends on emulation cores
| Donationware & Open source
|}

= Current Operating Systems =

== Desktop ==

{| class="wikitable sortable"
! Emulator name
! External link
! Windows
! macOS
! Linux
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| [[ACE|AceHacked]]
| [http://www.roudoudou.com/AceHacked/] [https://www.cpcwiki.eu/forum/emulators/ace-cpc-emulator-only-amiga-makes-it-possible/msg231201/] [https://www.youtube.com/watch?v=MJSFP7Hx3io wip] [https://www.youtube.com/watch?v=5zYVtGMWPVs wip2]
| ⚠️
| ⚠️
| ⚠️
|
| Sep 19, 2023
| ✅
| ✅
| -
| ❌ Unreleased
|-
| [[AMSpiriT|AMSpiriT]]
| [https://www.amspirit.fr/] [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535]
| ✅
| ❌
| ❌
| 0.863b
| May 13, 2023
| ❌ Unreleased
| ❌
| -
| Freeware
|-
| [[Arnimedes|Arnimedes]]
| [http://www.arnimedes.de/]
| ✅
| ❌
| ❌
| 1.02
| Jul 7, 2012
| ❌
| ❌
| -
| Freeware
|-
| [[Arnold_(Emulator)|Arnold]]
| [http://www.cpcwiki.eu/forum/emulators/arnold-wip/msg144749/#msg144749] [https://www.cpcwiki.eu/forum/emulators/another-version-of-arnold-emulator/ Aeliss fork] [http://www.yasara.org/cpc/ Arnold TNG] [https://web.archive.org/web/20191023094109/https://www.bannister.org/software/arnold.htm]
| ✅
| ⚠️
| ⚠️
| [http://www.cpcwiki.eu/imgs/d/dd/Arnoldwip_src.tar.bz2 WIP]
| May 13, 2017
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]]
| Open source
|-
| [[CaPriCe|Caprice32]]
| [https://github.com/ColinPitrat/caprice32/releases] [http://sourceforge.net/projects/caprice32/] [https://snapcraft.io/caprice32] [http://aleste520.narod.ru/caprice.html Caprice32-Aleste]
| ✅
| ✅
| ✅
| 4.6.0
| Oct 8, 2022
| ⚠️
| ✅
| -
| Donationware & Open source
|-
| [[Caprice Forever]]
| [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
| ✅
| ❌
| ❌
| 23.7
| Jul 10, 2023
| ✅
| ✅
| -
| Freeware
|-
| [[Caprice Reloaded]]
| [https://code.google.com/archive/p/cpcsdk/] [https://web.archive.org/web/20121203193335/https://aur.archlinux.org/packages.php?ID=38856]
| ✅
| ❌
| ⚠️
| r533
| Sep 25, 2011
| ✅
| ❌
| -
| Open source
|-
| [[Clock Signal|Clock Signal]]
| [https://github.com/TomHarte/CLK/releases] [https://snapcraft.io/clock-signal]
| ❌
| ✅
| ✅
|
| Sep 10, 2023
| ❌
| ❌
| [[ZX Spectrum]], [[Enterprise]], [[MSX]], [[ColecoVision]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos|Oric]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]]
| Donationware & Open source
|-
| [[CoPaCabana|CoPaCabana]]
| [http://copacabana.emuunlim.com/]
| ✅
| ❌
| ❌
| 0.74
| Apr 12, 2006
| ⚠️
| ❌
| -
| Donationware
|-
| [[CPC++|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| ✅
| ✅
| ⚠️
| b700
| May 31, 2015
| ❌
| ❌
| -
| Freeware
|-
| [[cpc4x|cpc4x]]
| [http://www.ulrich-cordes.de/cpc/english/cpcemu.htm]
| ❌
| ❌
| ⚠️
| 0.26
| Dec 11, 2004
| ❌
| ❌
| -
| Open source
|-
| [[CPCEC|CPCEC]]
| [http://cngsoft.no-ip.org/cpcec.htm] [https://github.com/cpcitor/cpcec] [http://cngsoft.no-ip.org/ CPCE] [https://github.com/AmatCoder/CPCEG CPCEG]
| ✅
| ❌
| ⚠️
|
| Aug 6, 2022
| ⚠️
| ✅
| [[ZX Spectrum]], [[Commodore 64]], [https://www.youtube.com/watch?v=5LwCy0gRAEc MSX (unreleased)]
| Open source
|-
| [[CPCEC|cpcec-gtk]]
| [https://bitbucket.org/norecess464/cpcec-gtk/]
| ❌
| ❌
| ✅
|
| Feb 4, 2023
| ✅
| ✅
| -
| Open source
|-
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| ✅
| ✅
| ✅
| 2.5
| Aug 13, 2022
| ⚠️
| ❌
| -
| Freeware
|-
| [[CPCEPower|CPCEPower]]
| [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
| ✅
| ✅
| ✅
| 2105
| Jun 4, 2021
| ❌
| ✅
| -
| Freeware
|-
| [[CPCSharp|CPCSharp]]
| [https://github.com/dolbz/CPCSharp/releases/]
| ✅
| ✅
| ❌
| 1.0.0-beta1
| Apr 7, 2021
| ⚠️
| ❌
| -
| Open source
|-
| [[CPvC|CPvC]]
| [https://github.com/alybaek2/cpvc]
| ✅
| ❌
| ❌
|
| Oct 7, 2020
| ❌
| ❌
| -
| Open source
|-
| [[DSP|DSP]]
| [https://github.com/leniad/dsp-emulator/]
| ✅
| ⚠️
| ⚠️
| 0.22wip5
| Aug 22, 2023
| ❌
| ❌
| [[ZX Spectrum]], [[Commodore 64]], [[ColecoVision]], [[Game Boy]], [[NES]], [[SG-1000]], [[Master System]], [[Game Gear]], [[Super Cassette Vision]], [[PV-1000]], [[PV-2000]], [[Arcade]]
| Open source
|-
| [[ep128emu|ep128emu]]
| [https://github.com/istvan-v/ep128emu]
| ✅
| ⚠️
| ⚠️
| 2.0.11.2
| Apr 19, 2019
| ⚠️
| ❌
| [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
|-
| [[MacCPC|MacCPC]]
| [http://www.wincpc.ch/index.php?topic=projects-maccpc]
| ❌
| ✅
| ❌
| 0.9.2
| Jan 22, 2010
| ✅
| ❌
| -
| Freeware
|-
| [[MESS|MAME]]
| [http://mamedev.org/release.html] [http://wiki.mamedev.org/index.php/SDL_Supported_Platforms] [http://sdlmame.lngn.net/]
| ✅
| ✅
| ✅
| 0.258
| Aug 30, 2023
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| [[NO$CPC|NO$CPC]]
| [http://problemkaputt.de/cpc.htm]
| ✅
| ❌
| ❌
| 1.8
| Nov 2, 2000
| ⚠️
| ✅
| -
| Freeware
|-
| [[PC-CPC|PC-CPC]]
| [http://cpcrulez.fr/emulateurs_download-WIN-PC-CPC.htm] [https://github.com/DemoniakLudo/PC-CPC]
| ✅
| ❌
| ❌
| 0.1at b29
| Nov 17, 2011
| ⚠️
| ❌
| -
| Open source
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| [https://www.retrovirtualmachine.org]
| ✅
| ✅
| ✅
| 2.1.8
| Sep 1, 2023
| ❌ Removed
| ✅
| [[ZX Spectrum]], [[MSX|MSX 1]], [[ColecoVision]], [[SG-1000]], [[Master System]]
| Donationware
|-
| [[Roland Emulator|Roland]]
| [https://www.rolandemu.de/en/downloads.html]/[https://github.com/raldus/roland GitHub]
| ✅
| ❌
| ✅
| 0.70
| Apr 20, 2017
| ❌
| ❌
| -
| Open source
|-
| [[Ronald|Ronald]]
| [https://github.com/mdm/ronald]
| ❌
| ❌
| ⚠️
|
| May 10, 2023
| ⚠️
| ❌
| -
| Open source
|-
| [[SugarBox|SugarBox]]
| [http://sugarbox.free.fr/] [https://github.com/Tom1975/SugarboxV2]
| ✅
| ✅
| ✅
| 2.0.1
| May 26, 2023
| ⚠️
| ✅
| -
| Open-Source
|-
| [[VirtualCPC|Virtual CPC]]
| [https://web.archive.org/web/20200112094913/http://users.otenet.gr/~sulfonic/cpc/] [https://cpcrulez.fr/emulateurs_download-WIN-virtual_cpc.htm]
| ✅
| ❌
| ❌
| 1.1
| Aug 8, 2011
| ⚠️
| ❌
| -
| Freeware
|-
| [[WinApe|WinAPE]]
| [http://www.winape.net/] [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPCWIN10.ZIP CPCwin]
| ✅
| ❌
| ❌
| 2.0b2
| Jan 5, 2016
| ✅
| ✅
| -
| Donationware
|-
| [[WinCPC|WinCPC]]
| [http://www.wincpc.ch/index.php?topic=projects-wincpc] [https://web.archive.org/web/20050409133618/http://www.easypoint.ch/vbcpc/ vbCPC]
| ✅
| ❌
| ❌
| 0.9.26
| Feb 1, 2007
| ✅
| ❌
| -
| Freeware
|-
| [[XCPC|Xcpc]]
| [https://www.xcpc-emulator.net/]
| ❌
| ❌
| ✅
| 0.38.1
| Apr 8, 2023
| ❌
| ❌
| -
| Open source
|-
| [[XNACPC|XNACPC]]
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/] [https://www.gavpugh.com/old-code/ CPC3D]
| ✅
| ❌
| ❌
| 1.0
| Nov 11, 2011
| ❌
| ❌
| -
| Open source
|-
| [[YACE|YACE]]
| [http://www.youtube.com/watch?v=uxQkljwc0i4]
| ❌
| ❌
| ⚠️
|
| Nov 12, 2014
| ✅
| ❌
| -
| ❌ Unreleased
|-
| [[ZEsarUX|ZEsarUX]]
| [https://github.com/chernandezba/zesarux]
| ✅
| ✅
| ✅
| X
| Sep 8, 2023
| ⚠️
| ❌
| [[PCW]], [[ZX Spectrum]], [[ZX80/81]], [[MSX|MSX 1]], [[ColecoVision]], [[Spectravideo]], [[Jupiter ACE]], [[Sam Coupe]], [[SG-1000]], [[Master System]], [[Sinclair QL]], [[MK14]], [[Z88]]
| Donationware & Open source
|}

== Alternative OS ==

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Developer tools
! Amstrad Plus
! Also emulates
! License
|-
| AmigaOS PPC
| [[Arnold|Arnold]]
| [http://hirudov.com/amiga/Arnold.php]
| 1.15
| Dec 17, 2012
| ❌
| ✅
| [[KC Compact]]
| Open source
|-
| AmigaOS PPC
| [[MESS|SDLMESS]]
| [http://se.os4depot.net/index.php?function=showfile&file=emulation/computer/sdl_mess.lha]
| 0.146u4
| Aug 19, 2012
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| Haiku
| [[ACE_(Emulator)|ACE]]
| [http://www.cpcwiki.eu/forum/emulators/ace-for-haiku/] [http://ace.cpcscene.net/]
| 1.25.0
| Feb 18, 2023
| ✅
| ✅
| -
| Freeware
|-
| Haiku
| [[AdvanceMAME|AdvanceMAME]]
| [https://depot.haiku-os.org/#!/pkg/advancemame_x86]
| 3.9-1
| Feb 3, 2020
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| MorphOS
| [[ACE_(Emulator)|ACE]]
| [http://ace.cpcscene.net/]
| 1.25
| September 8, 2022
| ✅
| ✅
| -
| Freeware
|-
| MorphOS
| [[MESS|MESS]]
| [http://fabportnawak.free.fr/mame/]
| 0.113
| Nov 1, 2007
| ⚠️
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|}

== Mobile ==

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Android
| [[andcpc]]
| [http://code.google.com/p/andcpc/]
| 1.5.1
| Apr 4, 2011
| ❌
| -
| Open source
|-
| Android
| [[Azimuth]]
| [https://play.google.com/store/apps/details?id=johnidis.azimuth]
| 1.11
| Aug 22, 2023
| ❌
| -
| Adware and in-app purchases💲
|-
| Android
| [[CPCDroid]]
| [https://fmsdevel.wisecoding.es/cpcdroid-amstrad-cpc-on-android-phone-2/]
| 1.5.1
| Mar 2, 2011
| ❌
| -
| Open source
|-
| Android
| [[CPCemu|CPCemu]]
| [https://play.google.com/store/apps/details?id=com.loritznet.softwarecreations.cpcemu]
| 2.5
| Aug 14, 2022
| ❌
| -
| Freeware
|-
| Android
| [[Droid-CPC]]
| [http://play.google.com/store/apps/details?id=com.kokak.droidcpc]
| 1.1.01
| Dec 15, 2016
| ❌
| -
| Commercial💲
|-
| iOS
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| 2.5
| Aug 13, 2022
| ❌
| -
| Software available on request
|-
| iOS
| [[CrocoDS]]
| [https://github.com/redbug26/crocods-ios]
| 2.1
| Jun 21, 2013
| ❌
| -
| Open source
|}

= Discontinued Operating Systems =

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Acorn RISC OS
| [[!CPC|!CPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPC0728.ZIP] [http://ftp2.fr.openbsd.org/ftp/pub/amstrad/emulator/CPCS1124.ZIP]
|
| Jul 28, 1996
| ❌
| -
| Open source
|-
| Acorn RISC OS
| [[!CPCemu|!CPCemu]]
| [http://huggers-world.de/mops.html]
| 1.21
| Mar 22, 2016
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[A-CPC|A-CPC]]
| [https://cpctech.cpcwiki.de/download/a-cpc.lha]
| 2.0
| Mar 30, 2002
| ✅
| -
| Open source
|-
| AmigaOS m68k
| [[Ami-cpc|Ami-cpc]]
| [http://deplanque.chez.com/] [http://deplanque.chez.com/download_fr.html Ami-cpc2]
| 0.46
| Jan 21, 1998
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[CPE|CPE]]
| [https://cpcrulez.fr/emulateurs_download-AMIGA-CPE.htm]
|
| Feb 24, 1995
| ❌
| -
| Open source
|-
| AmigaOS m68k
| [[Emu-CPC|EmuCPC]]
| [https://cpcrulez.fr/emulateurs_download-AMIGA-emucpc.htm]
| 0.7
| Sep 15, 1996
| ❌
| -
| Open source
|-
| BlackBerry OS
| [[BB-CPC|BB-CPC]]
| [http://appworld.blackberry.com/webstore/content/30963891/] (dead link)
| 1.0.1.3
| Jul 15, 2013
| ❌
| -
| Commercial💲
|-
| Classic Mac OS
| [[CPCplusplus|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| 1.3.2
| Oct 6, 1997
| ❌
| -
| Shareware💲
|-
| DOS
| [[AdvanceMESS|AdvanceMESS]]
| [https://www.advancemame.it/readme]
| 3.9
| Sep 8, 2018
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| DOS
| [[Arnimedes|Arnimedes]]
| [http://www.arnimedes.de/]
| 0.8a
| Apr 15, 2000
| ❌
| -
| Freeware
|-
| DOS
| [[Caprice32]]
| [https://ftp.nvg.ntnu.no/pub/cpc/emulator/msdos/capriced.zip]
| 1.11
| Sep 20, 1999
| ❌
| -
| Open source
|-
| DOS
| [[CPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/CPC055B.ZIP]
| 0.55b
| May 16, 1997
| ❌
| -
| Freeware
|-
| DOS
| [[CPC-em|CPC-em]]
| [http://cpc-em.emuunlim.com/]
| 0.4
| Jul 7, 2004
| ❌
| -
| Open source
|-
| DOS
| [[CPCE|CPCE]]
| [http://cngsoft.no-ip.org/cpce/]
| 1.94
| Jun 2, 2011
| ❌
| -
| Freeware
|-
| DOS
| [[CPCemu|CPCemu]]
| [http://www.cpc-emu.org/]
| 1.5
| Jul 7, 1998
| ❌
| -
| Freeware
|-
| DOS
| [[CPE|CPE]]
| [https://cpcrulez.fr/emulateurs_download-DOS-CPE.htm]
| 5.2
| Apr 21, 1997
| ❌
| -
| Open source
|-
| DOS
| [[NO$CPC|NO$CPC]]
| [http://problemkaputt.de/cpc.htm]
| 1.8
| Nov 2, 2000
| ✅
| -
| Freeware
|-
| DOS
| [[PC-CPC|PC-CPC]]
| [http://deplanque.chez.com/download_fr.html]
|
| Feb 3, 1998
| ❌
| -
| Open source
|-
| DOS
| [[CPCEMU (RWCPC)|RWCPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/RWCPC.ZIP]
|
| Mar 23, 1995
| ❌
| -
| Freeware
|-
| DOS
| [[SIMCPC|SIMCPC]]
| [https://www-ftp.lip6.fr/pub/amstrad/emulator/SIMCPC.ZIP]
|
| Dec 10, 1989
| ❌
| -
| Shareware💲
|-
| DOS
| [[YAGE|YAGE]]
| [https://www.zophar.net/cpc/yage.html]
| 0.91
| Oct 24, 1998
| ❌
| -
| Freeware
|-
| EXOS
| [[Software CPC Emulator|Software CPC Emulator]]
| [http://www.ep128.hu/Ep_Util/Prg/Amstrad_CPC_Emulator_13.rar] [http://www.ep128.hu/Ep_Util/Amstrad_CPC_emu.htm]
| 1.3
| Jan 11, 2013
| ❌
| -
| Open source
|-
| Maemo
| [[CPCm]]
| [http://maemo.org/downloads/product/Maemo5/cpcm/]
| 1.20-1
| Apr 27, 2010
| ❌
| -
| Open source
|-
| MSX-DOS
| [[EMU6CPC|EMU6CPC]]
| [http://romu6.blogspot.com/2018/12/emu6cpc-emulador-de-amstrad-cpc-6128.html]
|
| Dec 17, 2018
| ❌
| -
| Freeware
|-
| Palm OS
| [[CaPriCe for Palm OS|CaPriCe for Palm OS]]
| [https://web.archive.org/web/20230127143354/https://coste.frederic.free.fr/cpc/cpc_en.htm]
| 2.8
| Jun 28, 2011
| ❌
| -
| Open source
|-
| Palm OS
| [[CoPaCabana|CoPaCabana]]
| [http://copacabana.emuunlim.com/]
| 0.75
| Dec 4, 2007
| ❌
| -
| Freeware
|-
| Pocket PC
| [[CaPriCe|PocketCaprice]]
| [https://web.archive.org/web/20160506010209/http://www.clubic.com/telecharger-fiche44888-pocketcaprice.html]
| 0.9
| Aug 19, 2007
| ❌
| -
| Freeware
|-
| SunOS
| [[CPCplusplus|CPC++]]
| [http://bricerive.free.fr/cpc/cpcpp.html]
| 1.3.0
| Feb 22, 1997
| ❌
| -
| Shareware💲
|-
| Symbian
| [[S60-CPC|S60-CPC]]
| [http://kokak.free.fr/s60cpc.htm]
| 0.74
| Feb 21, 2006
| ❌
| -
| Open source
|-
| Windows 9x
| [[CPC-em|CPC-em]]
| [http://cpc-em.emuunlim.com/]
| 0.3
| Jan 22, 2004
| ❌
| -
| Open source
|-
| Windows 9x
| [[MTMW|MTMW]]
| [https://cpcrulez.fr/emulateurs_download-WIN-MTMW.htm]
| 1.30B
| Jan 11, 2000
| ✅
| [[ZX Spectrum]], [[ZX80/81]], [[Enterprise]], [[Jupiter ACE]]
| Freeware
|}

= Home Consoles =

You can use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on '''Apple TV, Android TV, Nvidia Shield, Xbox One, Xbox Series, PS2, GameCube, Wii, Wii U and Switch'''. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Microsoft XBOX
| [[Arnold|ArnoldX]]
| [https://web.archive.org/web/20120705163939/http://forums.xbox-scene.com/index.php?showtopic=711667] [https://cpcrulez.fr/emulateurs_download-XBOX-ARNOLDX.htm]
| v5
| Apr 20, 2010
| ✅
| -
| Freeware
|-
| Microsoft XBOX
| [[CoinOPS|CoinOPS (RetroFE)]]
| [https://web.archive.org/web/20160518183115/https://coinopsproject.freeforums.org/viewtopic.php?f=0&t=1213]
| 5
| Oct 18, 2012
| ❌
| Lots of other computer systems
| Freeware
|-
| Microsoft Xbox 360
| [[XNACPC|XNACPC]]
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
| 1.0
| Nov 11, 2011
| ❌
| -
| Open source
|-
| Nintendo Wii
| [[Wiituka|Wiituka]]
| [http://wiituka.dantoine.org/]
| 0.98.8
| May 15, 2009
| ❌
| -
| Open source
|-
| Sega Dreamcast
| [[CPCast|CPCast]]
| [http://www.dcemu.co.uk/vbulletin/showthread.php?t=24100]
|
| May 6, 2006
| ❌
| -
| Freeware
|-
| Sega Dreamcast
| [[DreamCPC|DreamCPC]]
| [https://www.jm1200.fr/index.php?r=2]
| Alpha 3
| Oct 16, 2005
| ❌
| -
| Freeware
|-
| Sony PS2
| [[CPC-em|CPC-em]]
| [https://cpcrulez.fr/emulateurs_download-ps2-CPC-EM.htm]
| 0.4
| Dec 22, 2004
| ❌
| -
| Freeware
|-
| Sony PS3
| [[Caprice32|Caprice32]]
| [https://web.archive.org/web/20171003153204/http://psx-scene.com/forums/content/caprice32-4-1-0-dbg-emulator-ps3-2119/]
| 4.1.0 DBG
| Apr 9, 2012
| ❌
| -
| Open source
|}

= Handheld Consoles =

Note: Android-based handheld consoles (Razer Edge, Ayn Odin Pro, Retroid Pocket Flip, GPD XP, ...) will work with stand-alone Android CPC emulators or with RetroArch, same as an Android phone.

You can use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on '''PSP, PS Vita, DS, 3DS, Switch, Steam Deck, RetroFW, Miyoo and OpenDingux'''. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Host system
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| Anbernic RG350
| [[CrocoDS|CrocoDS]]
| [https://crazypiri.eu/crocods/]
|
| Jan 15, 2020
| ❌
| -
| Freeware
|-
| Dingoo A320 / A330
| [[Pituka|Pituka Dingux]]
| [http://david.dantoine.org/proyecto/4/]
| 0.8pre
| Aug 19, 2010
| ❌
| -
| Open source
|-
| Dingoo A320 / A330
| [[Caprice|Dingux-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/105-Amstrad/]
| 1.1.2
| Oct 17, 2009
| ❌
| -
| Open source
|-
| GamePark Caanoo
| [[Caprice|Caanoo-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/165-Amstrad/]
| 1.1.3
| Apr 24, 2011
| ❌
| -
| Open source
|-
| GamePark GP2x
| [[Caprice|CapriceGP2x]]
| [https://web.archive.org/web/20130315195529/http://wiki.gp2x.org/wiki/CapriceGP2x]
| 0.5
| Feb 22, 2006
| ❌
| -
| Open source
|-
| GamePark GP2x
| [[Caprice|GP2X-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/42-Amstrad/]
| 1.5.1
| Aug 29, 2009
| ❌
| -
| Open source
|-
| GamePark GP32
| [[Pituka|Pituka GP32]]
| [http://david.dantoine.org/proyecto/4/]
| 1d
| May 15, 2010
| ❌
| -
| Open source
|-
| GamePark Wiz
| [[Caprice|Wiz-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/89-Amstrad/]
| 1.1.0
| Aug 29, 2009
| ❌
| -
| Open source
|-
| GCW Zero
| [[Caprice|Dingux-CAP32]]
| [https://github.com/kerheol/dingux-cap32]
| 1.1.2
| May 25, 2014
| ❌
| -
| Open source
|-
| JXD S5110 / S601 & Yinlips G18
| [[Caprice|JXD-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/206-Amstrad/]
| 1.1.1
| Oct 27, 2012
| ❌
| -
| Open source
|-
| Nintendo DS
| [[AmeDS|AmeDS]]
| [https://web.archive.org/web/20131021073302/http://www.portabledev.com/pages/ds/jeuxdev.-perso/ameds.php]
| 4.0
| Apr 25, 2010
| ❌
| -
| Freeware
|-
| Nintendo DS
| [[CrocoDS|CrocoDS]]
| [http://www.kyuran.be/blog/2007/11/09/crocods-20-2/]
| 2.0
| Nov 9, 2007
| ❌
| -
| Freeware
|-
| Nintendo GameBoy Advance
| [[Mini Amstrad Emulator|Mini Amstrad Emulator]]
| [https://playeradvance.org/forum/showthread.php?t=765]
|
| Dec 26, 2005
| ❌
| -
| Open source
|-
| Odroid GO
| [[CapriceESP32|CapriceESP32]]
| [https://github.com/grantrismo/CapriceESP32]
|
| Dec 3, 2020
| ❌
| -
| Open source
|-
| Pandora
| [[Caprice|Pandora-CAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/131-Amstrad/]
| 1.1.0
| Jun 27, 2010
| ❌
| -
| Open source
|-
| Sony PSP
| [[Caprice32 PSP]]
| [http://psp.akop.org/caprice32]
| 4.2.0.2
| Nov 28, 2007
| ❌
| -
| Open source
|-
| Sony PSP
| [[CPCPSP|CPCPSP]]
| [https://web.archive.org/web/20130325143915/http://dl.qj.net/psp/emulators/cpcpsp-v01.html]
| 0.1
| Dec 24, 2005
| ❌
| -
| Freeware
|-
| Sony PSP
| [[PSPCAP32|PSPCAP32]]
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/3-Amstrad/]
| 1.5.1
| Aug 21, 2009
| ❌
| -
| Open source
|-
| Trimui Model S
| [[Arnold|Arnold Trimui]]
| [https://github.com/liartes/arnold_gcw0]
|
| Oct 19, 2021
| ✅
| -
| Open source
|}

= Single-Board Computers / Raspberry Pi =

[https://www.libretro.com/index.php/powered-by-libretro/ LibRetro / RetroArch] is used as the foundation of [https://www.lakka.tv/ Lakka], [https://wiki.recalbox.com/en/advanced-usage/retroarch Recalbox], [https://batocera.org/ Batocera] and [https://retropie.org.uk/ RetroPie] alternative OSes for the Raspberry Pi and other SBC.
But you can also use [https://www.retroarch.com/index.php?page=platforms RetroArch] for Amstrad CPC emulation on a stock Raspberry Pi OS. Or you can use these stand-alone CPC emulators:

{| class="wikitable sortable"
! Emulator name
! External link
! Current version
! Latest release
! Amstrad Plus
! Also emulates
! License
|-
| [[CPC4Rpi|#CPC4Rpi]]
| [https://web.archive.org/web/20150321200308/http://store.raspberrypi.com/projects/cpc4rpi]
| 1.1
| Dec 19, 2013
| ❌
| -
| Commercial💲
|-
| [[CapriceRPI|CapriceRPI]]
| [https://github.com/KaosOverride/CapriceRPI]
| 1.3d
| Feb 28, 2016
| ❌
| -
| Open source
|-
| [[Clock Signal|Clock Signal]]
| [https://snapcraft.io/install/clock-signal/raspbian]
|
| May 15, 2023
| ❌
| [[ZX Spectrum]], [[Enterprise]], [[MSX]], [[ColecoVision]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos|Oric]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]]
| Donationware & Open source
|-
| [[CPCEPower|CPCEPower]]
| [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
| 2105
| Jun 4, 2021
| ✅
| -
| Freeware
|-
| [[MESS|MAME]]
| [https://stickfreaks.com/mame/]
| 0.258
| Aug 30, 2023
| ✅
| [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
|-
| [[SugarPi|SugarPi]]
| [https://github.com/Tom1975/SugarPi]
| 1.2.0
| Feb 3, 2021
| ✅
| -
| Open source
|-
| [[ZEsarUX|ZEsarUX]]
| [https://github.com/chernandezba/zesarux]
| X
| Sep 8, 2023
| ❌
| [[PCW]], [[ZX Spectrum]], [[ZX80/81]], [[MSX|MSX 1]], [[ColecoVision]], [[Spectravideo]], [[Jupiter ACE]], [[Sam Coupe]], [[SG-1000]], [[Master System]], [[Sinclair QL]], [[MK14]], [[Z88]]
| Donationware & Open source
|}

= Hardware =

*[[CPC TREX|CPC TREX]] [[C-ONE|CPC-ONE]] TurboCPC core running on a FPGA board
*[http://ralferoo.blogspot.fr/ CPC FPGA] CPC emulation running on a custom made FPGA board
*[[FPGAmstrad|FPGAmstrad]] [https://github.com/renaudhelias/CoreAmstrad CoreAmstrad] [https://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad CoreDocAmstrad] [https://github.com/mist-devel/mist-binaries/tree/master/cores/amstrad_alt CPC for MIST and MISTer] Translation of JavaCPC from Java into VHDL on a MiST board
*[https://intelligenttoasters.blog/cpc2-project-index/ CPC2 Project] CPC emulation running on a Cyclone V FPGA board
*[https://github.com/rpsubc8/ESP32TinyCPC/ ESP32 TinyCPC] Port from CPC-em emulator to TTGO VGA32 v1.x board with ESP32
*[[SDiskEmul]] Floppy-drive emulator released in 2007. Abandoned now. Supports DSK, EDSK disk-images
*[https://hxc2001.com/floppy_drive_emulator/ HxC Floppy Emulator] Commercial floppy-drive emulator. Supports HFE, DSK, EDSK, IPF disk-images
*[https://github.com/keirf/flashfloppy/ FlashFloppy] Open source floppy-drive emulator for the ubiquitous Gotek hardware. Supports HFE, DSK, EDSK disk-images

= Mass-storage, RTC and network dilemma =
Multiple mass-storage, RTC and network solutions already exist for the Amstrad CPC. We can put them in 3 categories:
*'''Historical''': The [[Vortex Winchester Drive]] and the [[Dobbertin Harddisc|Dobbertin HD20]] with [[Dobbertin Smart Watch]] were sold during the commercial lifetime of the CPC. But these solutions are clumsy today with their very small capacity, their CP/M filesystem and their non-standard hard-drives and interface.
*'''Historically-plausible''': The [[Symbiface II]] or [[X-Mass]] with [[Nova]] NVRAM/RTC are using the IDE/PATA interface created in 1986 for mass-storage access. However, the IDE interface was introduced on the CPC way after its commercial lifetime, the Symbiface II being released in 2006. The whole IDE/PATA sector access and FAT filesystem dance the CPC has to perform here is not necessary with more modern solutions. On the positive side, this isolation of the filesystem guarantees that the CPC software and the CPC emulator cannot inadvertently do wrong on the host filesystem, as the operations are limited to modifying the contents of the virtual hard-drive file. A direct file view on the host side can also make trouble if the CPC assumes it is the sole owner of the filesystem and doesn't accept that we change files and folders behind his back. The [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/cyboard-for-amstrad-cpc-yet-another-hardware-project/ Cyboard] is a Symbiface II clone that adds Ethernet support at a TCP/UDP level. The [https://github.com/salafek/Net4CPC Net4CPC] is the Ethernet part of the Cyboard provided without the Symbiface II.
*'''Modern''': [[Albireo]], [[ULIfAC]], [[Symbiface 3]] and [[M4 Board]] as they give the CPC a direct file view of the mass-storage instead of a sectors view. These solutions are well suited to provide network too, as HTTP and FTP are file access protocols. The Symbiface 3 and the M4 Board provide a NetAPI to access the Internet unlike the Albireo and the ULIfAC. The Symbiface 3 also emulates other peripherals (Dobbertin HD20, SSA-1 speech synthesizer, Digiblaster and AmDrum soundcards) but it is going overboard with its embedded MP3 player.

Emulator support is as follows:
*Dobbertin HD20 with Dobbertin SmartWatch is emulated by MAME
*Symbiface II or X-Mass IDE/PATA is emulated by ACE, Caprice Forever, MAME, WinAPE, WinCPC, Arnold, Virtual CPC
*Albireo is emulated by ACE, Caprice Forever
*M4 Board is emulated by CPCemu
*Vortex, Net4CPC, ULIfAC and Symbiface 3 are not supported by emulators

= CPC cartridge slot =
Emulator support for a CPC cartridge slot is as follows:
*[[Dandanator]] brings a non-standard physical cartridge port and a very exotic non-standard memory mapper that spies on Z80 instructions. It is emulated by ACE, Retro Virtual Machine, CPCEC, ZEsarUX
*[[Plus2CPC]] and [[Play2CPC]] bring a standard physical Plus cartridge port to the CPC. They are not supported by emulators
*[[M4 Board]] simulates a standard Plus cartridge port on the CPC and handles standard CPR files. M4 Board is emulated by CPCemu

Why is the Dandanator winning over standard Plus cartridge solutions like the Plus2CPC? It's because some CPC games (The Sword of Ianna, Los Amores de Brunilda, ...) are released exclusively for it. So emulators are then forced to support it.

The situation would be different if those games were converted to standard CPR format by the community.

= Audio devices =
Emulator support is as follows:
*[[Amstrad SSA-1 Speech Synthesizer|SSA-1 speech synthesizer]] is emulated by ACE, JavaCPC, MAME
*[[Dk'tronics Speech Synthesizer|Dk'Tronics speech synthesizer]] is emulated by ACE, JavaCPC, MAME
*[[TMPI speech synthesizer]] is emulated by ACE, Caprice Forever
*[[Amdrum|AmDrum]] is emulated by ACE, JavaCPC, MAME, WinAPE
*[[Digiblaster]] is emulated by ACE, JavaCPC, MAME, WinAPE, Caprice Forever, CPCEC, WinCPC, Virtual CPC
*[[PlayCity]] is fully emulated by ACE, MAME, Arnold, SugarBox. The audio part of [[PlayCity]] is emulated by JavaCPC, Caprice Forever, CPCEC
*[[Play2CPC]] is an amputated PlayCity, with no CTC chip and only one soundchip instead of two, but otherwise compatible with the PlayCity
*[[Willy|OPL3 (Willy)]] is emulated by ACE
*[https://github.com/lambdamikel/Speak-SID Speak&SID], [https://github.com/lambdamikel/LambdaSpeak3 LambdaSpeak], [[Willy|General MIDI (Willy)]], [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/amsdap-amstrad-msx-adapter-connecting-any-msx-io-hardware-to-the-cpc/ SE-One (Amsdap)] and [https://en.wikipedia.org/wiki/Moonsound Moonsound (Amsdap)] are not supported by emulators

= Emulator accuracy checking tools =
== Quick evaluation==
*[https://www.cpc-power.com/index.php?page=detail&num=7529 From Scratch demo] with reference images: [[Media:Fromscratch1.png]] [[Media:Fromscratch2.png]]
*[https://www.cpc-power.com/index.php?page=detail&num=7737 Camembert 4 demo] with reference images: [[Media:Camembert-real.jpg]] [[Media:Camembert 4 Pixel Precise.jpg]]

== Z80 CPU ==
*[https://cpcrulez.fr/applications_util-zexall.htm ZEXALL] and [https://cpcrulez.fr/applications_util-zexdoc.htm ZEXDOC] Z80 CPU instruction set exercisers
*[https://www.cpc-power.com/index.php?page=detail&num=12883 Z80 Full Test] [https://www.cpc-power.com/index.php?page=detail&num=12881 Z80 Doc Test] [https://www.cpc-power.com/index.php?page=detail&num=12882 Z80 Flags Test] [https://www.cpc-power.com/index.php?page=detail&num=12880 Z80 Doc Flags Test] [https://www.cpc-power.com/index.php?page=detail&num=12884 Z80 MEMPTR Test] [https://www.cpc-power.com/index.php?page=detail&num=12879 Z80 CCF Test]
*[https://www.cpc-power.com/index.php?page=detail&num=298 Arkanoid] [https://www.cpc-power.com/index.php?page=detail&num=1299 Light Corridor] Z80 IM2 usage, Z80 useless instruction prefixes
*[https://wikiti.brandonw.net/?title=Z80_Instruction_Set Z80 instruction set] [https://zx-pk.ru/attachment.php?attachmentid=2989&d=1143656567 Z80 MEMPTR (aka WZ) internal register] [https://github.com/hoglet67/Z80Decoder/wiki/Undocumented-Flags Even weirder Z80 behaviour] [https://zxe.io/software/Z80/documentation/latest/Thanks.html To get to the bottom of it] How the Z80 behaves
*[https://floooh.github.io/2021/12/06/z80-instruction-timing.html Z80 T-state timings] [https://baltazarstudios.com/zilog-z80-undocumented-behavior/ Other source about T-state timings] Ultra accurate timing behaviour

== Diagnostics ==
*[https://www.cpc-power.com/index.php?page=detail&num=5113 Official Amstrad CPC hardware diagnostics] [https://www.cpc-power.com/index.php?page=detail&num=17932 Non-official Amstrad Diagnostics v1.3a]
*[https://www.cpc-power.com/index.php?page=detail&num=6987 RAM Expansion Test] [https://www.cpc-power.com/index.php?page=detail&num=14833 MemTest] [https://www.cpc-power.com/index.php?page=detail&num=14834 RAM Test CRTC4] [https://www.cpc-power.com/index.php?page=detail&num=13386 Testprogram For All ERAM] [https://www.cpc-power.com/index.php?page=detail&num=19185 Xenon 2] [https://www.cpc-power.com/index.php?page=detail&num=12188 Take On Me] RAM testers
*[https://www.cpcwiki.eu/forum/emulators/amstrad-cpc-'acid'-test/ "Acid" test suite] [https://cpctech.cpcwiki.de/download/test.zip] [http://ace.cpcscene.net/tests:arnold_test_suite Tests results in ACE] [https://www.cpc-power.com/index.php?page=detail&num=17738 PPI tests] Chips tests by arnoldemu
*[http://www.winape.net/downloads.jsp Plus Test] [https://www.cpc-power.com/index.php?page=detail&num=15242] CPC and CPC+ Emulator test suite (including Instruction and Interrupt timing tests)

== Amstrad Plus ==
*[https://www.cpc-power.com/index.php?page=detail&num=9627 Plus diagnostics cartridge] Official Amstrad diagnostics
*[[File:Roudoudou CPR tests.zip]] [https://www.cpcwiki.eu/forum/emulators/amstrad-cpc-'acid'-test/75/] Amstrad Plus tests by Roudoudou
*[https://www.cpc-power.com/index.php?page=detail&num=18998 4096k Tester] [https://www.cpc-power.com/index.php?page=detail&num=3575 No Exit] Amstrad Plus palette, Floating bus problem
*[https://www.cpc-power.com/index.php?page=detail&num=8874 6128 Plus Dma] [https://cpcrulez.fr/demostestDO_fairy-breakpoint_2010.htm Fairy] [https://soundtrackerdma.cpcscene.net/doku.php?id=en:download Soundtracker DMA] To test DMA and to compare the PSG output with the output from a real Amstrad Plus
*[https://www.cpc-power.com/index.php?page=detail&num=7401 Black Sabbath] [https://www.cpc-power.com/index.php?page=detail&num=7532 X-Mas 2008] [https://www.cpc-power.com/index.php?page=detail&num=9169 Funerapolis] [https://www.cpc-power.com/index.php?page=detail&num=7935 Sappy] [https://www.pouet.net/prod.php?which=95133 USS Cygnus 192] To test hardware sprites emulation

== Graphics ==
*[http://www.logonsystem.eu/html/downloadlogon.htm Amstrad CPC CRTC Compendium with Shaker tool] [https://shaker.logonsystem.eu/ Shakerland Portal] Ultra accurate CRTC documentation and its associated CPC testing tool
*[https://www.cpc-power.com/index.php?page=detail&num=8524 Equalizor] [https://forum.system-cfg.com/viewtopic.php?p=229698#p229698 Revolog] [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535&start=285 Technical explanation] Unpredictable behaviour of the real Amstrad CPC chips (ie. outside the realm of emulation)
*[https://www.cpc-power.com/index.php?page=detail&num=10401 Test CRTC type v3.0] [https://www.planetemu.net/rom/amstrad-cpc-applications-dsk/crtc-editor-v5-1-1994-brain-of-chaos CRTC editor] [https://www.cpc-power.com/index.php?page=detail&num=15280 CRTC software] CRTC tools
*[https://cpcrulez.fr/coding_src-demo-smooth_crtc_register_3_scrolling_test.htm Smooth CRTC Register 3 scrolling test] [https://www.cpc-power.com/index.php?page=detail&num=6883 Edge Grinder] CRTC Register 3 horizontal scrolling trick [https://www.cpc-power.com/index.php?page=detail&num=99 Mission Genocide] CRTC hardware vertical scrolling
*[https://www.cpc-power.com/index.php?page=detail&num=12906 HSYNC test] [https://www.cpc-power.com/index.php?page=database&lemot=Rupture%20verticale HSYNC-based demo effects] Handling invalid CRTC HSYNC [https://www.cpc-power.com/index.php?page=detail&num=9211 Backtro] [https://www.cpc-power.com/index.php?page=detail&num=8041 Other World 3] CRTC effects
*[https://www.cpc-power.com/index.php?page=detail&num=12905 "Mode 5" Viewer] [https://www.cpc-power.com/index.php?page=detail&num=16466 Split-Rasters Test CRTC1] [https://www.cpc-power.com/index.php?page=detail&num=15519 Les split-rasters] [https://www.cpc-power.com/index.php?page=detail&num=7543 Odyssey] [https://www.cpc-power.com/index.php?page=detail&num=15101 Onescreen Colonies] [https://www.cpc-power.com/index.php?page=detail&num=13359 Imperial Mahjong] [https://www.cpcwiki.eu/forum/programming/mode-3/ Mode 3 Test] Split-rasters, multi-mode effects
*[https://www.cpc-power.com/index.php?page=detail&num=16027 Mire] [https://www.cpc-power.com/index.php?page=detail&num=14259 Test interlace color] [https://www.cpc-power.com/index.php?page=detail&num=13139 Perfect Pix Paint] [https://www.cpc-power.com/index.php?page=detail&num=7826 Climax-G] [https://www.cpc-power.com/index.php?page=detail&num=8307 4 Sins] [https://www.cpc-power.com/index.php?page=detail&num=7897 Twinblast] [https://www.cpc-power.com/index.php?page=detail&num=8081 MCS 6] [https://www.cpc-power.com/index.php?page=detail&num=2224 Thunder Blade] [https://www.cpc-power.com/index.php?page=detail&num=2318 Turrican] To test the VDU

== Peripherals ==
*[https://www.cpc-power.com/index.php?page=detail&num=3825 Magnum Light Phaser] [https://www.cpc-power.com/index.php?page=detail&num=3583 SkeetShoot for Trojan Phazer] [https://www.cpc-power.com/index.php?page=detail&num=3992 Dk'Tronics Light Pen] [https://www.cpc-power.com/index.php?page=detail&num=4955 Light Pen Mark II] To test lightguns and lightpens connected to expansion port
*[https://www.cpc-power.com/index.php?page=detail&num=1825 West Phaser] [https://www.cpc-power.com/index.php?page=detail&num=5325 Gunstick] [https://www.cpc-power.com/index.php?page=detail&num=4303 Trojan LP-1] To test lightguns and lightpens connected to joystick port
*[https://www.cpc-power.com/index.php?page=detail&num=4725 Amstrad SSA-1] [https://www.cpc-power.com/index.php?page=detail&num=4724 Dk'Tronics] [https://www.cpc-power.com/index.php?page=detail&num=4660 TMPI] To test speech synthesizers emulation
*[https://www.cpc-power.com/index.php?page=database&lemot=AmDrum AmDrum] [https://www.cpc-power.com/index.php?page=database&lemot=Digitracker Digitracker] [[File:DigiTracker Amdrum.zip]] [https://www.cpcwiki.eu/forum/applications/prodatrons-digitrackker-1-4-now-vor-lambdaspeak-amdrum-in-8-bit-mode!/] To test [[Amdrum|AmDrum]] and [[Digiblaster]] soundcards emulation
*[https://www.cpc-power.com/index.php?page=detail&num=4012 Advanced OCP Art Studio] To test [[AMX Mouse|AMX]] and [[Kempston Mouse|Kempston mouse]] emulation
*[[UniDOS]] [[SymbOS]] [[HDCPM]] To test mass-storage and RTC emulation
*[http://theswordofianna.retroworks.es/ The Sword of Ianna] [http://retroworks.es/php/game_en.php?id=11 Los Amores de Brunilda] [http://www.dandare.es/Proyectos_Dandare/Descargas.html MojonTwins romset] To test the [[Dandanator]] emulation

== Copy-protection ==
*[https://cpctech.cpcwiki.de/download/fdctest.zip FDC test suite] [https://cpctech.cpcwiki.de/download/drivetest.zip Disk drive tests] [https://cpctech.cpcwiki.de/download/cdttst.zip CDT/TZX test suite for emulators] Set of tests by arnoldemu
*[https://www.cpc-power.com/index.php?page=detail&num=15518 DskTest] [https://cpcrulez.fr/applications_disc-dlfrsilver_dump_tool_test_suite.htm Dlfrsilver Dump Tool Test Suite] [[ParaDOS]] [https://www.cpc-power.com/index.php?page=detail&num=6117 Discology] [https://www.cpc-power.com/index.php?page=detail&num=6118 Discology plus] [https://www.cpc-power.com/index.php?page=detail&num=4179 Hercule II] [https://www.cpc-power.com/index.php?page=detail&num=7542 Midline Process] To test FDC emulation
*[https://cpcrulez.fr/demostestDM_fatmag_01.htm FatMag] The HFE trackload version is designed as a very rigorous test of the FDC emulation [https://www.cpc-power.com/index.php?page=detail&num=17853 Open Tower Defense] Emulator detection through a FDC test
*[https://www.cpc-power.com/index.php?page=detail&num=1501 Le Nécromancien] [https://www.cpc-power.com/index.php?page=detail&num=839 E.X.I.T] [https://www.cpc-power.com/index.php?page=detail&num=1005 Basun] [https://www.cpc-power.com/index.php?page=detail&num=2195 Tensions] [https://www.cpc-power.com/index.php?page=detail&num=1589 Pacific] [https://www.cpc-power.com/index.php?page=detail&num=1784 Wild Streets] [https://www.cpc-power.com/index.php?page=detail&num=1958 Skyx] Some copy-protected disk-images
*[https://www.cpc-power.com/cpcarchives/index.php?page=articles&cat=12 Protection schemes documented] [https://simonowen.com/samdisk/sys_cpc/ Copy-protection in EDSK images] [https://forum.system-cfg.com/viewtopic.php?p=195705#p195705 Implementation in SugarBox emulator] [https://64nops.wordpress.com/2021/07/04/a-la-decouverte-du-fdc/ FDC blog articles (in french)] Technical explanations

= File format specifications =

*[https://www.cpcwiki.eu/index.php/Format:DSK_disk_image_file_format DSK / EDSK] [https://hxc2001.com/download/floppy_drive_emulator/SDCard_HxC_Floppy_Emulator_HFE_file_format.pdf HFE] File formats of disk-image
*[http://soundfile.sapp.org/doc/WaveFormat/ WAV PCM] [https://acorn.huininga.nl/pub/unsorted/software/pc/CSW/csw.html CSW] [https://www.cpcwiki.eu/index.php/Format:CDT_tape_image_file_format CDT / TZX] File formats of tape-image
*[https://www.cpcwiki.eu/index.php/Format:CPR_CPC_Plus_cartridge_file_format CPR cartridge] [https://www.cpcwiki.eu/index.php/Format:SNA_snapshot_file_format SNA snapshot] [https://www.cpcwiki.eu/forum/emulators/javacpc-desktop-available-as-beta!/100/ SNR session] Other file formats used in CPC emulators
*[https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=10 Archive of SNR sessions]
*[https://en.wikipedia.org/wiki/IMG_(file_format) IMG] [https://web.archive.org/web/20120202144328/http://download.microsoft.com/download/f/f/e/ffef50a5-07dd-4cf8-aaa3-442c0673a029/Virtual%20Hard%20Disk%20Format%20Spec_10_18_06.doc VHD] File formats of flat hard-drive image

= Emulation Tools =

*[http://www.cpcmania.com/news.htm CPCDiskXP] [https://github.com/jeromelesaux/dsk DSK] [https://github.com/cpcsdk/idsk iDSK] [[Dsktools|Dsktools]] [[ManageDSK|ManageDSK]] [[WriteDSK|WriteDSK]] [https://simonowen.com/samdisk/ SAMdisk] [https://github.com/Tom1975/SugarConvDsk SugarConvDsk] [https://web.archive.org/web/20230602152816/https://cpc-live.com/data/index.php?dir=-tools DiskUtil] [https://hxc2001.com/download/floppy_drive_emulator/ HxCFloppyEmulator software] [https://github.com/damieng/DiskImageManager Disk Image Manager] [https://github.com/neuro-sys/sector-cpc sector-cpc] Set of tools about disk-images
*[http://www.cpcmania.com/news.htm CPCTapeXP] [https://sourceforge.net/projects/cdtmaster/ CDTMaster] [https://cpctech.cpcwiki.de/download/2cdt.zip 2CDT] [http://cngsoft.no-ip.org/csw2cdt.htm CSW2CDT] [https://cpcrulez.fr/emulateurs_UTIL-CDT-CDT2WAV.htm CDT2WAV] [https://github.com/Tom1975/SugarConvTape SugarConvTape] [https://web.archive.org/web/20230602152816/https://cpc-live.com/data/index.php?dir=-tools TapeUtil] [https://github.com/shred/tzxtools tzxtools] Set of tools about tape-images
*[http://www.cpcmania.com/news.htm CPRTools] Edit Amstrad Plus CPR cartridge-images
*[https://bochs.sourceforge.io/doc/docbook/user/winimage.html WinImage, DiskExplorer, Mtools] [https://www.fysnet.net/ultimate/index.htm Ultimate Imager] [https://github.com/ProgrammingHobby/CPM_Image-File_Explorer CP/M Image File Explorer] Access and edit IMG hard-drive images. No need of tools for VHD images with FAT filesystem, they are supported directly in Windows Explorer: it works the same way as ISO files
*[[CPCGamesCD-CPCLoader|CPCGamesCD-CPCLoader]] CDROM containing a navigable database with all the games of the Amstrad CPC
*[https://colourclash.co.uk/cpc-analyser/ CPC Analyser] Help reverse engineer Amstrad CPC games
*[[Emulator tooling]] UI screenshots of tooling in CPC emulators
*[[WinApe|WinAPE]] [[WinCPC]] [[JavaCPC]] [https://code.google.com/archive/p/cpcsdk/ Caprice Reloaded] [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73 Caprice Forever] Emulators with an integrated Z80 Assembler
*[https://cpcrulez.fr/coding-crossdev_coding-Java-Z80Assembler.htm Java Z80Assembler] [https://pasmo.speccy.org/ Pasmo] [http://cngsoft.no-ip.org/uz80.htm UZ80] [https://github.com/EdouardBERGE/rasm Rasm] [https://cpcsdk.github.io/rust.cpclib/basm/ BASM] [https://github.com/z00m128/sjasmplus SjASMPlus] [https://github.com/cpcsdk/cpctools cpctools] [http://julien-nevo.com/disark/ Disark] Tools for CPC cross-development in Z80 Assembler
*[https://ccz80.webcindario.com/ccz80en.html ccz80] [https://sdcc.sourceforge.net SDCC] [https://www.cpcwiki.eu/forum/programming/phrozen-c/msg180715/#msg180715 SDCC vs PhrozenC] [http://www.cpcmania.com/Docs/Programming/SDCC_vs_z88dk_Comparing_size_and_speed.htm SDCC vs z88dk] [http://norecess.cpcscene.net/phactory.html Phactory] [https://github.com/cpcitor/cpc-dev-tool-chain cpc-dev-tool-chain] [https://lronaldo.github.io/cpctelera/ CPCtelera] Cross-platform CPC development in C
*[https://lemonspawn.com/turbo-rascal-syntax-error-expected-but-begin/ Turbo Rascal Syntax Error] [https://www.youtube.com/watch?v=NTfnE4kXqt8 CPC demo made with TRSE] [https://www.youtube.com/watch?v=XjnqXiUHekY TRSE CPC tutorial] A complete suite (IDE, compiler, resource editor) for developing CPC games/demos in Pascal
*[https://cpcbasic.webcindario.com/CPCBasicEn.html CPC Basic] [https://github.com/benchmarko/CPCBasic CPCBasic Unchained] [https://www.cpcalive.com/cpcalive_en.html CpcAlive] [https://ugbasic.iwashere.eu/ ugBASIC] Cross-platform CPC development in BASIC
*[https://github.com/jjaranda13/8BP 8BP] [https://www.cpc-power.com/index.php?page=detail&num=16035 CPC games made with 8BP] [[Laser Basic]] [[Laser BASIC Compiler]] [https://www.cpc-power.com/index.php?page=detail&num=7100 CPC game made with Laser Basic] [[Sprites Alive]] [https://www.youtube.com/watch?v=X53XF0txftQ CPC game made with Sprites Alive] [[B-ASIC]] [https://www.cpc-power.com/index.php?page=detail&num=4380 CPC+ game made with B-ASIC] Useful CPC tools to beef up the BASIC language
*[http://ldeplanque.free.fr/ConvImgCpc/new/ ConvImgCPC] [https://www.dadither.com/ DaDither] [https://github.com/jeromelesaux/martine Martine] [https://www.cpcwiki.eu/forum/applications/splitraster-v3/ Splitraster+] [https://www.pouet.net/prod.php?which=88808 UniPixelViewer] [https://www.youtube.com/watch?v=KBcxPWGmr6Q UniPixelViewer tutorial] Image converters from PC to CPC
*[http://grafx2.chez.com/ GrafX2] [http://multipaint.kameli.net/ Multipaint] [[Retro Game Asset Studio]] Cross-platform CPC pixel art editors
*[http://cngsoft.no-ip.org/chipnsfx.htm CHIPNSFX] [https://www.julien-nevo.com/arkostracker/ Arkos Tracker 2] [https://github.com/AugustoRuiz/WYZTracker WYZTracker] Cross-platform CPC music creation suites

= Emulator Detection =

If you want to promote usage of real CPC computers, you can detect CPC emulators by:
*Checking if the memory is initialized with zeroes, as real machines have random memory values at boot
*Focusing on the minute details in emulated Z80, CRTC, and PPI chips. They are most often wrong in emulators
*Examining the FDC chip. It is only replicated more or less superficially in all emulators because the internals of the chip are still unknown

Combining these methods will definitely get you a 100% success rate in detecting emulators, even the toughest ones.

<gallery>
Emulator undetected.png|Emulator undetected
Emulator detected.png|Emulator detected
</gallery>

There is also this initiative for emulators who willingly want to be detected: [[Emulator_IDs|Emulator IDs]]

= Emulators running on the Amstrad CPC =

{| class="wikitable sortable"
! Emulator name
! External link
! Current version
! Latest release
! License
! Emulates
|-
| [[CPCZVM|CPCZVM]]
| [https://www.cpcwiki.eu/index.php/Z-Machine]
|
| Jul 6, 2019
| Open source
| [[Z-Machine]]
|-
| [[Pac-Man|Pac-Man]]
| [http://www.cpcwiki.eu/forum/games/speed-up-patch-for-pac-man-emulator-for-cpc-by-syx-toto/msg81222/#msg81222]
| 1.1
| Jun 5, 2014
| Open source
| [[Pac-Man arcade|Pac-Man arcade]]
|-
| [[Phoenix|Phoenix]]
| [https://norbertkehrer.github.io/phoenix_cpc.html]
|
| Jan 6, 2019
| Freeware
| [[Phoenix arcade|Phoenix arcade]]
|-
| [[Space Invaders|Space Invaders]]
| [http://www.cpcwiki.eu/forum/games/space-invaders-arcade-emulator-for-amstrad-cpc/]
| 1.0
| Jun 11, 2016
| Freeware
| [[Space Invaders arcade|Space Invaders arcade]]
|-
| [[ZXM|ZXM]]
| [https://cpcrulez.fr/applications_util-ZXm.htm]
|
| 1993
| Freeware
| [[ZX Spectrum|ZX Spectrum]]
|-
| [[Zym|Zym]]
| [http://www.symbos.org/appinfo.htm?00054]
| 0.9
| Feb 19, 2022
| Open source
| [[Z-Machine]]
|}

[[Category:Emulator| ]]

Logon System

2023-07-24T08:44:38Z

Longshot: /* Links */

[[Image:LogonTeam1990.jpg|thumb|Logon System 1990 Amstrad Expo]]
[[Image:LogonSystem2006.jpg|thumb|Logon System. 22 Sept 2006]]
[[Image:Booth2018 01137.jpg|thumb|Logon System at [[Revision]] 2018.]]
'''Logon System''' is a French demo group which is very famous due to really great demos and new techniques the coders at Logon use. While [[The Demo]] was for a very long time the best megademo ever released on the CPC, [[Overflow]]'s demo III was one of the most extreme hardware demo ever produced.

== History ==

* Members of the group regularly wrote articles published in the French Magazine [[Amstrad Cent Pour Cent]] during its later life.

* During the 2010s decade, [[Overflow]] still wears the mantle of '''Logon System''''s legacy, sometimes competing successfully at demoparties or trying to be a legend again with goodies to match his ambition.

== Historical Members ==
* [[Digit]]
* [[Eros]]
* [[Fred Crazy]]
* [[Longshot]]
* [[Overflow]]
* [[Pict]]
* [[Slash]]
* [[Brad]]
* [[Naminu]]
* [[Rubi]]

== Releases ==

=== 2010s ===

* 2017 : [[Eerie Forest]] (PLUS/GX4000)
* 2017 : [[Logon's run - 3D meets the aging bits]] (CPC6128)
* 2015 : [http://www.pouet.net/prod.php?which=65232 '''iO'''] (MSX)
* 2012 : [[Yet Another Plasma!]] (CPC 4k intro)

=== 2000s ===

=== 1990s ===

=== 1980s ===

== Links ==

* [http://www.pouet.net/groups.php?which=483 POUËT's page on Logon System]

* [https://demozoo.org/groups/46351/ Demozoo's page on Logon system]

[[Category:Scene group]]

Programming methods used in games

2022-12-03T09:48:12Z

Longshot:

This section describes specific programming methods which are used in games and the games that use them.

=== Sampled Sound ===

Sampled music:
* Prehistorik 2
* Xyphoes Fantasy

The sampled speech is often stored as 4-bit values with 2 values packed into each byte. Each value is sent to one of the AY volume registers at a fixed rate.

Sampled speech:
* Chase HQ
* Bad Dudes vs Dragon Ninja
* Robocop

=== Rasters ===

[[Rasters]] is a colour changing effect.

Examples:

Zynaps.

=== Hardware Double Buffer ===

Most good CPC games use the hardware double buffer technique in order to display sprites and/or to scroll the play area smoothly.

In particular, two memory areas (instead of one) are reserved for the screen ram.

In each frame, one of the two screens is displayed while the other is not visible but is drawn to. After the draw is done, the screens are exchanged using the hardware, so that the previously invisible one is now visible and the previously visible one is invisible.

The exchange is done using the hardware specifically by changing the screen-offset, Reg 12 and 13 of the [[CRTC|CRTC]]).

This process is repeated.

The big advantage of this technique is that we can use a whole frame (or more) machine-time for our code (with no problems that arise when we alter screen ram at the same time the electron beam displays it on the monitor such as tearing or flickering).

However, page flipping eats up a lot of memory area (which is crucial especially for 64Kb machines). This explains why a lot of games can have small game-areas !

For example:
Pac-Man Emulator

=== Scrolling ===

The following types of scroll are used:

1. The player controls a character on the screen. When the character is moved the screen scrolls but the character remains in the same position on the screen. If they get to the edge of the map, they may walk up to the sides of the screen. If they walk back the other way when they reach a particular point on the screen it starts to scroll again and they remain in the same position.

2. The player controls a character on the screen. When the character is moved towards the edges of the screen, the scroll moves a whole screen in width or height. The character is now on the opposite side. e.g. the character moves left, the screen scrolls by a whole screen width, the character is now on the right. The screen only scrolls when they get close to the sides.

3. The screen always scrolls. The player controls a character who is either static or moves freely around the screen.

=== Parallax/Multi Layer Scroll===

Parallax or Multi Layer Scroll is an effect where there are 2 layers of tiles which scroll, one has priority over the other and often they move at different scroll rates.

For example, the following games have parallax or multi layer scroll:

* Wizard Willy
* Teenage Mutant Hero Turtles
* Astro Marine Corps (AMC)
* Turrican I and II
* Shadow Dancer

==== Software Scrolling ====

The screen is scrolled using the CPU only. This can be done by moving the data on the screen, or re-drawing it in a different position to give the illusion of scrolling.

Examples:

* Robocop
* Batman the Movie.

==== Hardware Scrolling ====

Hardware scrolling is performed by changing the CRTC registers R12 and R13 to define the start address of the screen. The display is automatically wrapped at 16K, so continuous incrementation of these values will scroll the screen and wrap around. The code must then update the display for new graphics.

The scrolling is in CRTC character sizes.
* 1 CRTC char horizontally is 2 bytes of RAM at a time which corresponds to 4 mode 0 pixels, 8 mode 1 pixels or 16 mode 2 pixels.
* The height of a CRTC char is defined by CRTC Register 9 (Max Raster), which is normally set to 7. Resulting in 8 scanlines per character.

Horizontal scrolling can be made smoother by using R3 (Hsync Width), in addition to using R12 and R13 and makes the scrolling effectively half a CRTC char (therefore 2 mode 0 pixels, 4 mode 1 pixels or 8 mode 2 pixels). This can be done by changing the HSYNC width values between 5 and 6. The movement is an effect of how the monitor handles the HSYNC. This effect works well on Amstrad monitors, doesn't work on modern TFT screens and produces a black and white image on a MP-2 modulator because of the adjusted HSYNC timing.

Vertical scrolling can be made smoother by using R5 (Vertical Adjust). This works on all monitors.

More recent games (e.g. Prehistorik 2, Super Cauldron) use the rupture technique when doing vertical scroll to ensure the display is a constant number of scan lines in height, and so the refresh rate is always the same.

Older games adjust R5 and don't use rupture (e.g. LED Storm, Legend of Kage), the time for a frame therefore varies by up to 7 extra scan-lines. This means the VSYNC to the monitor also varies in position by up to 7 extra scan-lines, and the stability of the image is then dependent on how the monitor handles the VSYNC.

If the game uses a status panel, there are 2 ways to handle this.
# Redraw the panel when the screen is scrolled to compensate for it.
# Use rupture technique, the panel is in a different part of RAM and will not be affected by the scroll.

This following is an incomplete list of games using hardware scrolling. From this list it can be seen that hardware scrolling has been used from 1984 :

{| class="FCK__ShowTableBorders"
|-
| ''Title''
| ''Year''
| ''Vertical''
| ''Horizontal''
| ''R3''
| ''R5''
| ''Confirmed''
|-
| [[3D Stunt Rider]]
| 1985
| No
| Yes
| No
| No
| Yes
|-
| [[Action Force]]
| 1988
| No
| Yes
| No
| No
| Yes
|-
| [[The Amazing Shrinking Man|Amazing Shrinking Man (The)]]
| 1986
| Yes
| Yes
| No
| No
| Yes
|-
| [[Anarchy]]
| 1988
| No
| Yes
| No
| No
|-
| [[Axys: The Last Battle]]
| 1991
| Yes
| No
| No
| Yes
| Yes
|-
| [[BMX Kidz]]
| 1988
| No
| Yes
| No
| No
| Yes
|-
| [[Bob Morane Science Fiction]]
| 1987
| Yes
| Yes
| No
| No
|-
| [[Boulder Dash]]
| 1984
| Yes
| Yes
| No
| No
| Yes
|-
| [[Builderland]]
| 1991
| No
| Yes
| No
| No
|-
| [[Canadair]]
| 1987
| No
| Yes
| No
| No
| Yes
|-

| [[Cessna Over Moscow]]
| 1987
| No
| Yes
| No
| No
| Yes
|-

| [[Cyborgs]]
| 1991
| Yes
| Yes
| Yes
| Yes
| Yes
|-
| [[DJ Puff's Volcanic Eruption]]
| 1992
| Yes
| Yes
| No
| No
| No
|-
| [[Doctor Who and the Mines of Terror]]
| 1986
| Yes
| Yes
| No
| No
| Yes
|-
| [[Edge Grinder]]
| 2011
| No
| Yes
| Yes
| No
| Yes
|-
| [[Energy Warrior]]
| 1987
| No
| Yes
| No
| No
| Yes
|-
| [[FlySpy]]
| 1986
| Yes
| Yes
| No
| No
|-
| [[Fusion 2]]
| 1988
| No
| Yes
| No
| No
| Yes
|-
| [[Glen Hoddle Soccer]]
| 1985
| No
| Yes
| No
| No
| Yes
|-
| [[Gothic]]
| 1988
| Yes
| Yes
| No
| Yes
|-
| [[Ghosts 'n' Goblins]]
| 1986
| No
| Yes
| Yes
| No
| Yes
|-
| [[Ghouls 'n' Ghosts]]
| 1989
| No
| Yes
| No
| No
| Yes
|-
| [[Into The Eagle's Nest]]
| 1987
| Yes
| Yes
| No
| No
| Yes
|-
| [[Jinks]]
| 1988
| No
| Yes
| Yes
| No
| Yes
|-
| [[Killer Cobra]]
| 1987
| No
| Yes
| Yes
| No
| Yes
|-
| [[Led Storm]]
| 1988
| Yes
| No
| No
| Yes
| Yes
|-
| [[Legend of Kage]]
| 1986
| Yes
| Yes
| Yes
| Yes
| Yes
|-
| [[Leviathan]]
| 1987
| Diagonal
| scroll!
| No
| No
| Yes
|-
| [[Le 5eme Axe]]
| 1985
| Yes
| Yes
| No
| No
| Yes
|-
| [[Mission Genocide]]
| 1987
| Yes
| No
| No
| Yes
| Yes
|-
| [[Monty Python's Flying Circus]]
| 1990
| Yes
| Yes
| No
| No
| Yes
|-
| [[Octoplex]]
| 1989
| Yes
| Yes
| No
| Yes(?)
| Yes
|-
| [[Out of This World]]
| 1987
| No
| Yes
| Yes
| No
| Yes
|-
| [[Paraplane]]
| 1992
| Yes
| Yes
| No
| No
|-
| [[Plate-Forme]]
| 1988
| No
| Yes
| No
| No
| Yes
|-
| [[Prehistorik 2]]
| 1992
| Yes
| Yes
| Yes
| Yes
| Yes
|-
| [[Profanation]]
| 1987
| Yes
| Yes
| Yes
| Yes
| Yes
|-
| [[Prohibition]]
| 1987
| Yes
| Yes
| No
| No
| Yes
|-
| [[Rastan]]
| 1987
| Yes
| Yes
| No
| No
| Yes
|-
| [[Realm!]]
| 1987
| Yes
| Yes
| No
| No
|-
| [[Rick Dangerous 2]]
| 1990
| No
| Yes
| No
| No
|-
| [[Rig Attack]]
| 1985
| No
| Yes
| No
| No
| Yes
|-
| [[Rockford]]
| 1988
| Yes
| Yes
| No
| No
| Yes
|-
| [[Roland on the Ropes]]
| 1984
| Yes
| Yes
| No
| No
|-
| [[The Sentinel|Sentinel (The)]]
| 1987
| Yes
| Yes
| No
| No
| Yes
|-

| [[Star Sabre]]
| 2007
| No
| Yes
| No
| No
| Yes
|-
| [[The Return of the Jedi|Return of the Jedi (The)]]
| 1989
| Diagonal
| scroll!
| No
| No
| Yes
|-
| [[Thing on a Spring]]
| 1986
| No
| Yes
| Yes
| No
| Yes
|-
| [[Skate Ball]]
| 1989
| No
| Yes
| No
| No
| Yes
|-
| [[Skateboard Kidz]]
| 1988
| Yes
| No
| No
| Yes
| Yes
|-
| [[Skate Rock]]
| 1987
| No
| Yes
| No
| No
| Yes
|-
| [[Skate Wars]]
| 1990
| No
| Yes
| No
| Yes
| Yes
|-
| [[Sly Spy Secret Agent]]
| 1990
| Yes
| Yes
| No
| No
| Yes
|-
| [[Star Avenger]]
| 1984
| No
| Yes
| No
| No
|-
| [[Star Sabre]]
| 2007
| No
| Yes
| No
| Yes
| Yes
|-
| [[Street Machine]]
| 1986
| Yes
| Yes
| No
| No
| Yes
|-
| [[Striker in the Crypts of Trogan]]
| 1992
| Yes
| Yes
| No
| No
|-
| [[Super Cauldron]]
| 1992
| Yes
| Yes
| Yes
| Yes
| Yes
|-
| [[Titan]]
| 1988
| Yes
| Yes
| No
| No
|-
| [[T.L.L. - Tornado Low Level|Tornado Low Level]]
| 1985
| Yes
| Yes
| No
| No
| Yes
|-
| [[Top Level]]
|
| Yes
| No
| No
| No
|-

| [[Twin World]]
| 1990
| Yes
| No
| No
| No
| Yes
|-

| [[Ultima Ratio]]
| 1987
| Yes
| No
| No
| No
| Yes
|-
| [[Unitrax]]
| 1987
| Yes
| Yes
| No
| No
| Yes
|-
| [[Vector Ball]]
| 1988
| Diagonal
| scroll!
| No
| No
| Yes
|-
| [[Vikings (The)]]
| 1986
| Yes
| Yes
| No
| No
| Yes
|-
| [[Warhawk]]
| 1987
| Yes
| No
| No
| Yes
| Yes
|-
| [[Wonderboy]]
| 1987
| No
| Yes
| No
| No
| Yes
|-
| [[Xeno]]
| 1986
| No
| Yes
| No
| No
| Yes
|}

=== Rupture (or splitscreen) ===

A CRTC programming technique used to split the screen into more than one block vertically.

The sizes of each block are defined using CRTC register R4. Vsync is turned off in all but one block (by setting CRTC R7 to a value larger than R4).
The start address of each block can be changed using CRTC registers R12 and R13.

This allows each block to reference different ram or to hardware scroll one block while another is static.

This method requires careful timing for the CRTC register updates, it also needs testing on all CRTC because there are differences of when each will accept and use the values programmed. However, the result can be made to work on all with more simple ruptures. Care must also be taken to ensure the timings are setup for a 50Hz screen.

It is worth noting that some monitors are more tolerant to longer or shorter frames so the result may appear correctly on them and not on others.
In addition some games may have been programmed and tested on only 1 CRTC type so may not work on others.

Wonderboy sets R4 every frame to the same value - reason unknown. But it doesn't use Rupture, because if this code is removed it works fine.

This is a an incomplete list of games that use this technique, but according to this list the earliest games used this technique was 1987:

{| class="FCK__ShowTableBorders"
|-
| ''Title''
| ''Year''
| ''Confirmed''
|-
| [[007 The Living Daylights|007 The Living Daylights]]
| 1987
| Yes
|-
| [[Action Force|Action Force]]
| 1988
| Yes
|-
| [[Axys: The Last Battle|Axys]]
| 1991
| Yes
|-
| [[Dynamic Duo|Dynamic Duo]]
| 1988
|
|-
| [[DJ Puff's Volcanic Eruption]]
| 1992
| Yes
|-
| [[Energy Warrior|Energy Warrior]]
| 1987
| Yes
|-
| [[Enlightenment: Druid 2|Enlightenment: Druid 2]]
| 1988
|
|-
| [[European 5-A-Side]]
| 1988
|
|-
| [[F1 Tornado Simulator]]
| 1991
| No
|-
| [[Grell and Falla|Grell and Falla]]
| 1992
|
|-
| [[Mission Genocide|Mission Genocide]]
| 1987
| Yes
|-
| [[Octoplex|Octoplex]]
| 1989
| Yes
|-
| [[Para Academy]]
| 1990
| No
|-
| [[Prehistorik 2|Prehistorik 2]]
| 1992
| Yes
|-
| [[Q10 Tank Buster]]
| 1991
| Yes
|-
| [[Rastan]]
| 1987
| Yes
|-
| [[Rockford]]
| 1988
| Yes
|-
| [[Santa's Christmas Capers]]
| 1990
| Yes
|-
| [[Skate Ball|Skate Ball]]
| 1989
| Yes
|-
| [[Skatewars|Skatewars]]
| 1989
|
|-
| [[Skateboard Kidz|Skateboard Kidz]]
| 1988
| Yes
|-
| [[Snowstrike|Snowstrike]]
| 1990
|
|-
| [[Storm Warrior|Storm Warrior]]
| 1989
| Yes
|-
| [[Super Cauldron|Super Cauldron]]
| 1992
| Yes
|-
| [[Turrican|Turrican]]
| 1990
| Yes
|-

| [[Twin World (Ubi Soft)|Twin World (Ubi Soft)]]
| 1990
| Yes
|-
| [[Usagi Yojimbo|Usagi Yojimbo]]
| 1988
| Yes
|-
| [[Warhawk|Warhawk]]
| 1987
| Yes
|-
| [[Xyphoes Fantasy|Xyphoes Fantasy]]
| 1991
| Yes
|-
|}

==Firmware==

The following games are known to use firmware functions. This probably explains why they are poor. If the programmer had used the hardware directly they would have lots more cycles free which they could have used to make the game better.

This list is not exhaustive.

*[[Xevious]]

[[Category:Programming]]

Emulators

2022-10-25T09:33:21Z

Longshot: /* Windows */

= Operating Systems =

== Acorn RISC OS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[!CPC|!CPC]]
|
| Jul 28, 1996
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPC0728.ZIP]
|-
| [[!CPCemu|!CPCemu]]
| 1.21
| Mar 22, 2016
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.huggers-world.de/files/cpcemu121.zip]
|}

== AmigaOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[A-CPC|A-CPC]]
| 2.0
| Apr, 2002
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://cpctech.cpc-live.com/download/a-cpc.lha]
|-
| [[Ami-CPC|Ami-CPC]]
| 0.46
| Jan 21, 1998
| [[CPC old generation|CPC range]]
| Open source
| [http://deplanque.chez.com/ami-cpc.lha]
|-
| [[Arnold|Arnold]]
| 1.15
| Dec 17, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]]
| Open source
| [http://hirudov.com/amiga/Arnold.php]
|-
| [[CPE|CPE]]
|
| Feb 24, 1995
| [[CPC old generation|CPC range]]
| Open source
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/ACPE_NEW.LHA]
|-
| [[Emu-CPC|Emu-CPC]]
| 0.7
| Sep 15, 1996
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/EMUCPC07.LZX]
|-
| [[MESS|SDLMESS]]
| 0.146u4
| Aug 19, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://se.os4depot.net/index.php?function=showfile&file=emulation/computer/sdl_mess.lha]
|}

== AMSDOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pac-Man|Pac-Man]]
| 1.1
| Jun 5, 2014
| [[Pac-Man arcade|Pac-Man arcade]]
| Open source
| [http://www.cpcwiki.eu/forum/games/speed-up-patch-for-pac-man-emulator-for-cpc-by-syx-toto/msg81222/#msg81222]
|-
| [[Space Invaders|Space Invaders]]
| 1.0
| Jun 11, 2016
| [[Space Invaders arcade|Space Invaders arcade]]
| Freeware
| [http://www.cpcwiki.eu/forum/games/space-invaders-arcade-emulator-for-amstrad-cpc/]
|-
| [[ZXM|ZXM]]
|
| 1993
| [[ZX Spectrum|ZX Spectrum]]
| Freeware
| [ftp://ftp.nvg.ntnu.no/pub/cpc/misc/zxm.zip]
|}

== DOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnimedes|Arnimedes]]
| 0.8a
| Apr 15, 2000
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.arnimedes.de/]
|-
| [[CPCE|CPCE]]
| 1.94
| Jun 2, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cngsoft.no-ip.org/cpce/]
|-
| [[CPCemu|CPCemu]]
| 1.5
| Jul 7, 1998
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[NO$CPC|NO$CPC]]
| 1.8
| Nov 2, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://problemkaputt.de/cpc.htm]
|-
| [[CPCEMU (RWCPC)|RWCPC]]
|
| Mar 23, 1995
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/RWCPC.ZIP]
|-
| [[SIMCPC|SIMCPC]]
|
| 1990
| [[CPC old generation|CPC range]]
| Shareware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/SIMCPC.ZIP]
|}

== EXOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Software CPC Emulator|Software CPC Emulator]]
| 1.3
| Jan 11, 2013
| [[CPC old generation|CPC range]]
| Open source
| [http://www.ep128.hu/Ep_Util/Prg/Amstrad_CPC_Emulator_13.rar]
|}

== Haiku ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[ACE_(Emulator)|ACE]]
| 1.14.0
| Jun 20, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://www.cpcwiki.eu/forum/emulators/ace-for-haiku/] [http://ace.cpcscene.net/]
|-
| [[AdvanceMAME|AdvanceMAME]]
| 3.9-1
| Feb 3, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [https://depot.haiku-os.org/#!/pkg/advancemame_x86]
|}

== Java / JVM ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold Jnr|Arnold Jnr]]
|
| Aug 27, 2001
| [[CPC old generation|CPC range]]
| Open source
| [http://www.arnoldemu.freeserve.co.uk/]
|-
| [[CPCInAJar|CPCInAJar]]
|
| Mar 16, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/cpcinajar/]
|-
| [[JavaCPC|JavaCPC Desktop]]
| 2.9.7
| Sep 21, 2018
| [[CPC old generation|CPC range]], [[KC Compact]]
| Donationware
| [https://sourceforge.net/projects/javacpc/]
|-
| [[JavaCPC|JavaCPC Applet]]
|
| Jul 10, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware
| [http://java.cpc-live.com/] (dead link)
|-
| [[JavaGX4000|JavaGX4000]]
|
| Sep 7, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://sourceforge.net/projects/javagx4000/]
|-
| [[JEMU|JEMU]]
|
| Feb 19, 2007
| [[CPC old generation|CPC range]], [[BBC Micro]], [[VZ-300]], [[ZX Spectrum]], [[ZX80/81]]
| Open source
| [http://jemu.winape.net/]
|-
| [[JKCEMU|JKCEMU]]
| 0.9.7
| Mar 30, 2017
| [[KC Compact]] & other computers from East Germany
| Open source
| [http://www.jens-mueller.org/jkcemu/kccompact.html]
|-
| [[WebCPC|WebCPC]]
| r15
| Dec 31, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/webcpc/]
|}

== JavaScript / HTML5 ==

{| class="wikitable sortable" style="width:100%"
|-
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCBox|CPCBox]]
| beta
| Dec 28, 2013
| [[CPC old generation|CPC range]]
| Freeware
| [https://web.archive.org/web/20190702084943/http://www.cpcbox.com/] [https://bzhgames.xyz/index.php BZH Games]
|-
| [[CrocoDS|CrocoDS]]
|
| May 13, 2020
| [[CPC old generation|CPC range]]
| Freeware
| [http://crocods.org/web/]
|-
| [[JSMESS]]
| 0.153
| Oct 29, 2014
| [[CPC old generation|CPC range]] & lots of other computer systems
| Open source
| [http://jsmess.textfiles.com/]
|-
| [[Roland javascript emulator|Roland]]
|
| Sep 24, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://roland.retrolandia.net/]
|-
| [[Tiny Emus]]
|
| Dec 31, 2018
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[VIC-20]], [[Commodore 64]], [[Acorn Atom]], [[KC Compact]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]]
| Open source
| [https://floooh.github.io/tiny8bit/] [http://cpc.devilmarkus.de/ JavaCPC-Games]
|-
| [[Griffin CPC emulator|Xiragon]]
|
| Nov 28, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://xiragon.com/]
|-
| [[YAKC|Yet another KC emulator]]
|
| Apr 17, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Commodore 64]], [[Acorn Atom]], [[KC Compact]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]], [[HC900]]
| Open source
| [http://floooh.github.io/virtualkc/]
|}

== macOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold_(Emulator)|Arnold]]
| 1.7.9
| Mar 10, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]]
| Open source
| [https://www.bannister.org/software/arnold.htm]
|-
| [[Clock Signal|Clock Signal]]
|
| Aug 2, 2020
| [[CPC old generation|CPC range]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]], [[MSX|MSX 1]], [[ColecoVision]]
| Open source
| [https://github.com/TomHarte/CLK/releases]
|-
| [[CPCplusplus|CPC++]]
| 2.0.0
| Jan 14, 2003
| [[CPC old generation|CPC range]]
| Shareware
| [http://bricerive.free.fr/cpc/cpcpp.html]
|-
| [[CPCSharp|CPCSharp]]
| 1.0.0-beta1
| Apr 7, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/dolbz/CPCSharp/releases/]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[MacCPC|MacCPC]]
| 0.9.2
| Jan 22, 2010
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.wincpc.ch/index.php?topic=projects-maccpc]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[MESS|SDLMAME]]
| 0.201
| Aug 29, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://sdlmame.lngn.net/]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Donationware & Open source
| [https://github.com/chernandezba/zesarux]
|}

== MorphOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[ACE_(Emulator)|ACE]]
| 1.25
| September 8, 2022
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://ace.cpcscene.net/]
|-
| [[MESS|MESS]]
| 0.113
| Nov 1, 2007
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://fabportnawak.free.fr/mame/]
|}

== MSX2 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[EMU6CPC|EMU6CPC]]
|
| Dec 17, 2018
| [[CPC old generation|CPC range]]
| Freeware
| [http://romu6.blogspot.com/2018/12/emu6cpc-emulador-de-amstrad-cpc-6128.html]
|}

== Unix / Linux ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold_(Emulator)|Arnold]]
|
| Jan 20, 2016
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]]
| Open source
| [http://www.cpcwiki.eu/forum/emulators/arnold-wip/msg118124/]
|-
| [[CaPriCe|CaPriCe32]]
| 4.4.0
| Mar 26, 2017
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware & Open source
| [https://github.com/ColinPitrat/caprice32]
|-
| [[Caprice Reloaded]]
| r377
| Jul 13, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://aur.archlinux.org/packages.php?ID=38856]
|-
| [[Clock Signal|Clock Signal]]
|
| Aug 2, 2020
| [[CPC old generation|CPC range]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]], [[MSX|MSX 1]], [[ColecoVision]]
| Open source
| [https://github.com/TomHarte/CLK/releases]
|-
| [[CPCplusplus|CPC++]]
| 1.5.0
|
| [[CPC old generation|CPC range]]
| Shareware
| [http://bricerive.free.fr/cpc/cpcpp.html]
|-
| [[cpc4x|cpc4x]]
| 0.26
| Dec 11, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://www.ulrich-cordes.de/cpc/english/cpcemu.htm]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[ep128emu|ep128emu]]
| 2.0.11
| Jan 20, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
| [http://sourceforge.net/projects/ep128emu/]
|-
| [[MESS|MAME]]
| 0.227
| Dec 30, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://wiki.mamedev.org/index.php/SDL_Supported_Platforms]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[Roland Emulator|Roland]]
| 0.70
| Apr 20, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://www.rolandemu.de/index.html]
|-
| [[Ronald|Ronald]]
|
| Sep 5, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/mdm/ronald]
|-
| [[SugarBox|SugarBox]]
| 0.29
| Jan 22, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open-Source
| [http://sugarbox.free.fr/] [https://github.com/Tom1975/SugarboxV2]
|-
| [[XCPC|Xcpc]]
| 0.37.0
| May 2, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://www.xcpc-emulator.net/]
|-
| [[YACE|YACE]]
| Unreleased?
| Nov 12, 2014
| [[CPC old generation|CPC range]]
| Unreleased?
| [http://www.youtube.com/watch?v=uxQkljwc0i4]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.1
| Nov 26, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Open source
| [https://github.com/chernandezba/zesarux]
|}

== Windows ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[AMSpiriT|AMSpiriT]]
| 0.704b
| Oct 20, 2022
| [[CPC old generation|CPC range]]
| Freeware
| [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535]
|-
| [[Arnimedes|Arnimedes]]
| 1.02
| Jul 7, 2012
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.arnimedes.de/]
|-
| [[Arnold_(Emulator)|Arnold]]
| [http://www.cpcwiki.eu/imgs/d/dd/Arnoldwip_src.tar.bz2 WIP]
| May 13, 2017
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]]
| Open source
| [http://www.cpcwiki.eu/forum/emulators/arnold-wip/msg144749/#msg144749] [https://www.cpcwiki.eu/forum/emulators/another-version-of-arnold-emulator/ Aeliss fork]
|-
| [[CaPriCe|CaPriCe]]
| 4.2.0
| May 14, 2005
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/caprice32/]
|-
| [[CaPriCe|CaPriCe 32]]
| 4.5.0
| Dec 27, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware & Open source
| [https://github.com/ColinPitrat/caprice32]
|-
| [[Caprice Forever]]
| 20.10
| Jul 14, 2020
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
|-
| [[Caprice Reloaded]]
| r533
| Sep 25, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://code.google.com/p/cpcsdk/]
|-
| [[Caprice32-Aleste|Caprice32-Aleste]]
| 4.1.0
| Nov 14, 2007
| [[Aleste 520EX|Aleste 520EX]]
| Open source
| [http://aleste520.narod.ru/caprice.html]
|-
| [[CoPaCabana|CoPaCabana]]
| 0.74
| Apr 12, 2006
| [[CPC old generation|CPC range]]
| Freeware
| [http://copacabana.emuunlim.com/]
|-
| [[CPC-em|CPC-em]]
| 0.4
| Jul 7, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://cpc-em.emuunlim.com/]
|-
| [[CPC++|CPC++]]
| b700
| Mar 26, 2014
| [[CPC old generation|CPC range]]
| Freeware
| [http://cpcrulez.fr/emulateurs_download-WIN-CPC_plus_plus.htm]
|-
| [[CPC3D/CPC32]]
| 0.3
| Feb 8, 2003
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.angelfire.com/retro2/cpc3d/]
|-
| [[CPCE|CPCE]]
| 1.94
| Jun 2, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cngsoft.no-ip.org/cpce/]
|-
| [[CPCEC|CPCEC]]
| 20200622
| Jun 6, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://cngsoft.no-ip.org/cpcec.htm]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[CPCEmuPower|CPCEmuPower]]
| 2005
| May 31, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [https://www.cpcwiki.eu/forum/emulators/cpcepower-v2005/]
|-
| [[CPCSharp|CPCSharp]]
| 1.0.0-beta1
| Apr 7, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/dolbz/CPCSharp/releases/]
|-
| [[CPCwin|CPCwin]]
| 1.0
| Dec 4, 1997
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPCWIN10.ZIP]
|-
| [[CPE|CPE]]
| 5.2
| Apr 21, 1997
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPE52.ZIP]
|-
| [[CPvC|CPvC]]
|
| Oct 7, 2020
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/alybaek2/cpvc]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[ep128emu|ep128emu]]
| 2.0.11
| Jan 20, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
| [http://sourceforge.net/projects/ep128emu/]
|-
| [[MESS|MAME]]
| 0.201
| Aug 30, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://mamedev.org/release.html]
|-
| [[MTMW|MTMW]]
| 1.30B
| Jan 11, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Enterprise]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/MTMW130B.ZIP]
|-
| [[NO$CPC|NO$CPC]]
| 1.8
| Nov 2, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://problemkaputt.de/cpc.htm]
|-
| [[PC-CPC|PC-CPC]]
| 0.1at b29
| Nov 17, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cpcrulez.fr/emulateurs_download-WIN-PC-CPC.htm]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[Roland Emulator|Roland]]
| 0.70
| Apr 20, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://www.rolandemu.de/en/downloads.html]/[https://github.com/raldus/roland GitHub]
|-
| [[SugarBox|SugarBox]]
| 0.29
| Jan 22, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open-Source
| [http://sugarbox.free.fr/] [https://github.com/Tom1975/SugarboxV2]
|-
| [[vbCPC|vbCPC]]
| 1.06
| Apr 7, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.emu-france.com/news/9609-ordi-vbcpc-v1-0-6/]
|-
| [[VirtualCPC|Virtual CPC]]
| 1.1
| Aug 8, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://users.otenet.gr/~sulfonic/cpc/]
|-
| [[WinApe|WinAPE]]
| 2.0b2
| Jan 5, 2016
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware
| [http://www.winape.net/]
|-
| [[WinCPC|WinCPC]]
| 0.9.26
| Feb 1, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.wincpc.ch/index.php?topic=projects-wincpc]
|-
| [[XNACPC|XNACPC]]
| 1.0
| Nov 11, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
|-
| [[Yage|Yage]]
| 0.91
| Oct 24, 1998
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/YAGE091.ZIP]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Donationware & Open source
| [https://github.com/chernandezba/zesarux]
|}

== Emulation Core ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| libretro-cap32 (for RetroArch)
| 1.2.2
| Jul 19, 2015
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/libretro/libretro-cap32]
|-
| libretro-crocods (for RetroArch)
| 0.1
| Feb 28, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/libretro/libretro-crocods]
|-
| SugarLibRetro (for RetroArch)
| git
| -
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/Tom1975/SugarLibRetro] (wraps independent lib https://github.com/Tom1975/CPCCore)
|}

= Home Consoles =

== Microsoft XBOX ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold|ArnoldX]]
| v5
| Apr 20, 2010
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
|
| [http://forums.xbox-scene.com/index.php?showtopic=711667]
|-
| [[CoinOPS|CoinOPS]]
| 5
| Oct 18, 2012
| [[CPC old generation|CPC range]] & lots of other computer systems
|
| [http://coinopsproject.freeforums.org/viewtopic.php?f=0&t=1213]
|}

== Microsoft Xbox 360 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[XNACPC|XNACPC]]
| 1.0
| Nov 11, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
|}

== Nintendo Wii ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Wiituka|Wiituka]]
| 0.98.8
| May 15, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://wiituka.dantoine.org/]
|}

== Sega Dreamcast ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCast|CPCast]]
|
| May 6, 2006
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.dcemu.co.uk/vbulletin/showthread.php?t=24100]
|-
| [[DreamCPC|DreamCPC]]
| Alpha 3
| Oct 16, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://jm1200.free.fr/index.php?r=2]
|}

== Sony PS2 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[PCPC|PCPC]]
|
| Dec 22, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://ps2emu.dcemu.co.uk/pcpc.shtml]
|}

== Sony PS3 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice32|Caprice32]]
| 4.1.0 DBG
| Apr 9, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://psx-scene.com/forums/content/caprice32-4-1-0-dbg-emulator-ps3-2119/]
|}

= Handheld Consoles =

== Dingoo A320 / A330 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pituka|Pituka (Dingux)]]
| 0.8pre
| Aug 19, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://david.dantoine.org/proyecto/4/]
|-
| [[Caprice|Dingux-CAP32]]
| 1.1.2
| Oct 17, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/105-Amstrad/]
|}

== GamePark GP32 / GP2X / Wiz / Caanoo ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pituka|Pituka (GP32)]]
| 1d
| May 15, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://david.dantoine.org/proyecto/4/]
|-
| [[Caprice|CapriceGP2x]]
| 0.5
| Feb 22, 2006
| [[CPC old generation|CPC range]]
| Open source
| [http://wiki.gp2x.org/wiki/CapriceGP2x]
|-
| [[Caprice|GP2X-CAP32]]
| 1.5.1
| Aug 29, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/42-Amstrad/]
|-
| [[Caprice|Wiz-CAP32]]
| 1.1.0
| Aug 29, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/89-Amstrad/]
|-
| [[Caprice|Caanoo-CAP32]]
| 1.1.3
| Apr 24, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/165-Amstrad/]
|}

== GCW Zero ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|Dingux-CAP32]]
| 1.1.2
| May 25, 2014
| [[CPC old generation|CPC range]]
| Open source
| [http://boards.dingoonity.org/gcw-releases/caprice32-%28amstrad-cpc%29/]
|}

== JXD S5110 / S601 & Yinlips G18 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|JXD-CAP32]]
| 1.1.1
| Oct 27, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/206-Amstrad/]
|}

== Nintendo DS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[AmeDS|AmeDS]]
| 4.0
| Apr 25, 2010
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.portabledev.com/pages/ds/jeuxdev.-perso/ameds.php]
|-
| [[CrocoDS|CrocoDS]]
| 2.0
| Nov 9, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.kyuran.be/blog/2007/11/09/crocods-20-2/]
|}

== Odroid GO ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CapriceESP32|CapriceESP32]]
|
| Dec 3, 2020
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/grantrismo/CapriceESP32]
|}

== Pandora ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|Pandora-CAP32]]
| 1.1.0
| Jun 27, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/131-Amstrad/]
|}

== Sony PSP ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice32 PSP]]
| 4.2.0.2
| Nov 28, 2007
| [[CPC old generation|CPC range]]
| Open source
| [http://psp.akop.org/caprice32]
|-
| [[CPCPSP|CPCPSP]]
| 0.1
| Dec 24, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://dl.qj.net/psp/emulators/cpcpsp-v01.html]
|-
| [[PSPCAP32|PSPCAP32]]
| 1.5.1
| Aug 21, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/3-Amstrad/]
|}

= Smartphones / PDA / SoC =

== Android ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[andcpc]]
| 1.5.1
| Apr 4, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://code.google.com/p/andcpc/]
|-
| [[CPCDroid]]
| 1.5.1
| Mar 2, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://fmsdevel.wisecoding.es/blog/cpcdroid---2011-03-02]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[Droid-CPC]]
| 1.1.01
| Dec 15, 2016
| [[CPC old generation|CPC range]]
| Commercial
| [http://play.google.com/store/apps/details?id=com.kokak.droidcpc]
|}

== BlackBerry ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[BB-CPC|BB-CPC]]
| 1.0.1.3
| Jul 15, 2013
| [[CPC old generation|CPC range]]
| Commercial
| [http://appworld.blackberry.com/webstore/content/30963891/]
|}

== iOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CrocoDS]]
| 2.1
| Jun 21, 2013
| [[CPC old generation|CPC range]]
| Open source
| [http://github.com/redbug26/crocods]
|}

== Maemo ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCm]]
| 1.20-1
| Apr 27, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://maemo.org/downloads/product/Maemo5/cpcm/]
|}

== Palm OS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CaPriCe for Palm OS|CaPriCe for Palm OS]]
| 2.8
| Jun 28, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://frederic.coste.pagesperso-orange.fr/cpc/cpc_en.htm]
|-
| [[CoPaCabana|CoPaCabana]]
| 0.75
| Dec 4, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://copacabana.emuunlim.com/]
|}

== Pocket PC ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CaPriCe|PocketCaprice]]
| 0.9
| Aug 19, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.clubic.com/telecharger-fiche44888-pocketcaprice.html]
|}

== Raspberry Pi ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPC4Rpi|#CPC4Rpi]]
| 1.1
| Dec 19, 2013
| [[CPC old generation|CPC range]]
| Open source
| [https://www.raspberrypi.org/forums/viewtopic.php?f=78&t=63820]
|-
| [[CapriceRPI|CapriceRPI]]
| 1.3
| Feb 28, 2016
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/KaosOverride/CapriceRPI]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Open source
| [https://github.com/chernandezba/zesarux]
|}

== Symbian ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[S60-CPC|S60-CPC]]
| 0.74
| Feb 21, 2006
| [[CPC old generation|CPC range]]
| Open source
| [http://kokak.free.fr/s60cpc.htm]
|}

= Hardware =

*[[CPC TREX|CPC TREX]] TurboCPC core running on a terasIC T-Rex C1 FPGA board
*[[C-ONE|CPC-ONE]] TurboCPC core running on the C-One FPGA board
*[http://ralferoo.blogspot.fr/ CPC FPGA] CPC emulation running on a custom made FPGA board
*[[FPGAmstrad|FPGAmstrad]] CPC emulation running on a NEXYS2 FPGA board
*[http://github.com/mist-devel/mist-board/wiki MIST board] FPGA board implementing Amstrad CPC and various other 8-bit and 16-bit computers

= Emulation Tools =

*[[ConvImgCPC|ConvImgCPC]]
*[[CPCDiskXP|CPCDiskXP]]
*[[CPCGamesCD-CPCLoader|CPCGamesCD-CPCLoader]]
*[[CPCTapeXP|CPCTapeXP]]
*[[CPRTools|CPRTools]]
*[[Dsktools|Dsktools]]
*[[ManageDSK|ManageDSK]]
*[[WriteDSK|WriteDSK]]

= Emulator Detection =

*[[Emulator_IDs|Emulator IDs]]

[[Category:Emulator| ]]

Emulators

2022-10-25T09:32:32Z

Longshot: /* Windows */

= Operating Systems =

== Acorn RISC OS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[!CPC|!CPC]]
|
| Jul 28, 1996
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPC0728.ZIP]
|-
| [[!CPCemu|!CPCemu]]
| 1.21
| Mar 22, 2016
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.huggers-world.de/files/cpcemu121.zip]
|}

== AmigaOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[A-CPC|A-CPC]]
| 2.0
| Apr, 2002
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://cpctech.cpc-live.com/download/a-cpc.lha]
|-
| [[Ami-CPC|Ami-CPC]]
| 0.46
| Jan 21, 1998
| [[CPC old generation|CPC range]]
| Open source
| [http://deplanque.chez.com/ami-cpc.lha]
|-
| [[Arnold|Arnold]]
| 1.15
| Dec 17, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]]
| Open source
| [http://hirudov.com/amiga/Arnold.php]
|-
| [[CPE|CPE]]
|
| Feb 24, 1995
| [[CPC old generation|CPC range]]
| Open source
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/ACPE_NEW.LHA]
|-
| [[Emu-CPC|Emu-CPC]]
| 0.7
| Sep 15, 1996
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/EMUCPC07.LZX]
|-
| [[MESS|SDLMESS]]
| 0.146u4
| Aug 19, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://se.os4depot.net/index.php?function=showfile&file=emulation/computer/sdl_mess.lha]
|}

== AMSDOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pac-Man|Pac-Man]]
| 1.1
| Jun 5, 2014
| [[Pac-Man arcade|Pac-Man arcade]]
| Open source
| [http://www.cpcwiki.eu/forum/games/speed-up-patch-for-pac-man-emulator-for-cpc-by-syx-toto/msg81222/#msg81222]
|-
| [[Space Invaders|Space Invaders]]
| 1.0
| Jun 11, 2016
| [[Space Invaders arcade|Space Invaders arcade]]
| Freeware
| [http://www.cpcwiki.eu/forum/games/space-invaders-arcade-emulator-for-amstrad-cpc/]
|-
| [[ZXM|ZXM]]
|
| 1993
| [[ZX Spectrum|ZX Spectrum]]
| Freeware
| [ftp://ftp.nvg.ntnu.no/pub/cpc/misc/zxm.zip]
|}

== DOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnimedes|Arnimedes]]
| 0.8a
| Apr 15, 2000
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.arnimedes.de/]
|-
| [[CPCE|CPCE]]
| 1.94
| Jun 2, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cngsoft.no-ip.org/cpce/]
|-
| [[CPCemu|CPCemu]]
| 1.5
| Jul 7, 1998
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[NO$CPC|NO$CPC]]
| 1.8
| Nov 2, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://problemkaputt.de/cpc.htm]
|-
| [[CPCEMU (RWCPC)|RWCPC]]
|
| Mar 23, 1995
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/RWCPC.ZIP]
|-
| [[SIMCPC|SIMCPC]]
|
| 1990
| [[CPC old generation|CPC range]]
| Shareware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/SIMCPC.ZIP]
|}

== EXOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Software CPC Emulator|Software CPC Emulator]]
| 1.3
| Jan 11, 2013
| [[CPC old generation|CPC range]]
| Open source
| [http://www.ep128.hu/Ep_Util/Prg/Amstrad_CPC_Emulator_13.rar]
|}

== Haiku ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[ACE_(Emulator)|ACE]]
| 1.14.0
| Jun 20, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://www.cpcwiki.eu/forum/emulators/ace-for-haiku/] [http://ace.cpcscene.net/]
|-
| [[AdvanceMAME|AdvanceMAME]]
| 3.9-1
| Feb 3, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [https://depot.haiku-os.org/#!/pkg/advancemame_x86]
|}

== Java / JVM ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold Jnr|Arnold Jnr]]
|
| Aug 27, 2001
| [[CPC old generation|CPC range]]
| Open source
| [http://www.arnoldemu.freeserve.co.uk/]
|-
| [[CPCInAJar|CPCInAJar]]
|
| Mar 16, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/cpcinajar/]
|-
| [[JavaCPC|JavaCPC Desktop]]
| 2.9.7
| Sep 21, 2018
| [[CPC old generation|CPC range]], [[KC Compact]]
| Donationware
| [https://sourceforge.net/projects/javacpc/]
|-
| [[JavaCPC|JavaCPC Applet]]
|
| Jul 10, 2012
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware
| [http://java.cpc-live.com/] (dead link)
|-
| [[JavaGX4000|JavaGX4000]]
|
| Sep 7, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://sourceforge.net/projects/javagx4000/]
|-
| [[JEMU|JEMU]]
|
| Feb 19, 2007
| [[CPC old generation|CPC range]], [[BBC Micro]], [[VZ-300]], [[ZX Spectrum]], [[ZX80/81]]
| Open source
| [http://jemu.winape.net/]
|-
| [[JKCEMU|JKCEMU]]
| 0.9.7
| Mar 30, 2017
| [[KC Compact]] & other computers from East Germany
| Open source
| [http://www.jens-mueller.org/jkcemu/kccompact.html]
|-
| [[WebCPC|WebCPC]]
| r15
| Dec 31, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/webcpc/]
|}

== JavaScript / HTML5 ==

{| class="wikitable sortable" style="width:100%"
|-
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCBox|CPCBox]]
| beta
| Dec 28, 2013
| [[CPC old generation|CPC range]]
| Freeware
| [https://web.archive.org/web/20190702084943/http://www.cpcbox.com/] [https://bzhgames.xyz/index.php BZH Games]
|-
| [[CrocoDS|CrocoDS]]
|
| May 13, 2020
| [[CPC old generation|CPC range]]
| Freeware
| [http://crocods.org/web/]
|-
| [[JSMESS]]
| 0.153
| Oct 29, 2014
| [[CPC old generation|CPC range]] & lots of other computer systems
| Open source
| [http://jsmess.textfiles.com/]
|-
| [[Roland javascript emulator|Roland]]
|
| Sep 24, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://roland.retrolandia.net/]
|-
| [[Tiny Emus]]
|
| Dec 31, 2018
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[VIC-20]], [[Commodore 64]], [[Acorn Atom]], [[KC Compact]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]]
| Open source
| [https://floooh.github.io/tiny8bit/] [http://cpc.devilmarkus.de/ JavaCPC-Games]
|-
| [[Griffin CPC emulator|Xiragon]]
|
| Nov 28, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://xiragon.com/]
|-
| [[YAKC|Yet another KC emulator]]
|
| Apr 17, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Commodore 64]], [[Acorn Atom]], [[KC Compact]], [[KC 85]], [[KC 87]], [[Z9001]], [[Z1013]], [[HC900]]
| Open source
| [http://floooh.github.io/virtualkc/]
|}

== macOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold_(Emulator)|Arnold]]
| 1.7.9
| Mar 10, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]]
| Open source
| [https://www.bannister.org/software/arnold.htm]
|-
| [[Clock Signal|Clock Signal]]
|
| Aug 2, 2020
| [[CPC old generation|CPC range]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]], [[MSX|MSX 1]], [[ColecoVision]]
| Open source
| [https://github.com/TomHarte/CLK/releases]
|-
| [[CPCplusplus|CPC++]]
| 2.0.0
| Jan 14, 2003
| [[CPC old generation|CPC range]]
| Shareware
| [http://bricerive.free.fr/cpc/cpcpp.html]
|-
| [[CPCSharp|CPCSharp]]
| 1.0.0-beta1
| Apr 7, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/dolbz/CPCSharp/releases/]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[MacCPC|MacCPC]]
| 0.9.2
| Jan 22, 2010
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.wincpc.ch/index.php?topic=projects-maccpc]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[MESS|SDLMAME]]
| 0.201
| Aug 29, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://sdlmame.lngn.net/]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Donationware & Open source
| [https://github.com/chernandezba/zesarux]
|}

== MorphOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[ACE_(Emulator)|ACE]]
| 1.25
| September 8, 2022
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://ace.cpcscene.net/]
|-
| [[MESS|MESS]]
| 0.113
| Nov 1, 2007
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://fabportnawak.free.fr/mame/]
|}

== MSX2 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[EMU6CPC|EMU6CPC]]
|
| Dec 17, 2018
| [[CPC old generation|CPC range]]
| Freeware
| [http://romu6.blogspot.com/2018/12/emu6cpc-emulador-de-amstrad-cpc-6128.html]
|}

== Unix / Linux ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold_(Emulator)|Arnold]]
|
| Jan 20, 2016
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]]
| Open source
| [http://www.cpcwiki.eu/forum/emulators/arnold-wip/msg118124/]
|-
| [[CaPriCe|CaPriCe32]]
| 4.4.0
| Mar 26, 2017
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware & Open source
| [https://github.com/ColinPitrat/caprice32]
|-
| [[Caprice Reloaded]]
| r377
| Jul 13, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://aur.archlinux.org/packages.php?ID=38856]
|-
| [[Clock Signal|Clock Signal]]
|
| Aug 2, 2020
| [[CPC old generation|CPC range]], [[Acorn Electron]], [[Apple II]], [[Oric 1/Atmos]], [[VIC-20]], [[ZX80/81]], [[Atari 2600]], [[Atari ST]], [[Macintosh]], [[MSX|MSX 1]], [[ColecoVision]]
| Open source
| [https://github.com/TomHarte/CLK/releases]
|-
| [[CPCplusplus|CPC++]]
| 1.5.0
|
| [[CPC old generation|CPC range]]
| Shareware
| [http://bricerive.free.fr/cpc/cpcpp.html]
|-
| [[cpc4x|cpc4x]]
| 0.26
| Dec 11, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://www.ulrich-cordes.de/cpc/english/cpcemu.htm]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[ep128emu|ep128emu]]
| 2.0.11
| Jan 20, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
| [http://sourceforge.net/projects/ep128emu/]
|-
| [[MESS|MAME]]
| 0.227
| Dec 30, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://wiki.mamedev.org/index.php/SDL_Supported_Platforms]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[Roland Emulator|Roland]]
| 0.70
| Apr 20, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://www.rolandemu.de/index.html]
|-
| [[Ronald|Ronald]]
|
| Sep 5, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/mdm/ronald]
|-
| [[SugarBox|SugarBox]]
| 0.29
| Jan 22, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open-Source
| [http://sugarbox.free.fr/] [https://github.com/Tom1975/SugarboxV2]
|-
| [[XCPC|Xcpc]]
| 0.37.0
| May 2, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://www.xcpc-emulator.net/]
|-
| [[YACE|YACE]]
| Unreleased?
| Nov 12, 2014
| [[CPC old generation|CPC range]]
| Unreleased?
| [http://www.youtube.com/watch?v=uxQkljwc0i4]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.1
| Nov 26, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Open source
| [https://github.com/chernandezba/zesarux]
|}

== Windows ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[AMSpiriT|AMSpiriT]]
[https://www.cpcwiki.eu/forum/emulators/amspirit-a-new-cpc-emulator-for-windows/]
| 0.704b
| Oct 20, 2022
| [[CPC old generation|CPC range]]
| Freeware
| [https://forum.system-cfg.com/viewtopic.php?f=24&t=11535]
|-
| [[Arnimedes|Arnimedes]]
| 1.02
| Jul 7, 2012
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.arnimedes.de/]
|-
| [[Arnold_(Emulator)|Arnold]]
| [http://www.cpcwiki.eu/imgs/d/dd/Arnoldwip_src.tar.bz2 WIP]
| May 13, 2017
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]]
| Open source
| [http://www.cpcwiki.eu/forum/emulators/arnold-wip/msg144749/#msg144749] [https://www.cpcwiki.eu/forum/emulators/another-version-of-arnold-emulator/ Aeliss fork]
|-
| [[CaPriCe|CaPriCe]]
| 4.2.0
| May 14, 2005
| [[CPC old generation|CPC range]]
| Open source
| [http://sourceforge.net/projects/caprice32/]
|-
| [[CaPriCe|CaPriCe 32]]
| 4.5.0
| Dec 27, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware & Open source
| [https://github.com/ColinPitrat/caprice32]
|-
| [[Caprice Forever]]
| 20.10
| Jul 14, 2020
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-power.com/cpcarchives/index.php?page=articles&num=73]
|-
| [[Caprice Reloaded]]
| r533
| Sep 25, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://code.google.com/p/cpcsdk/]
|-
| [[Caprice32-Aleste|Caprice32-Aleste]]
| 4.1.0
| Nov 14, 2007
| [[Aleste 520EX|Aleste 520EX]]
| Open source
| [http://aleste520.narod.ru/caprice.html]
|-
| [[CoPaCabana|CoPaCabana]]
| 0.74
| Apr 12, 2006
| [[CPC old generation|CPC range]]
| Freeware
| [http://copacabana.emuunlim.com/]
|-
| [[CPC-em|CPC-em]]
| 0.4
| Jul 7, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://cpc-em.emuunlim.com/]
|-
| [[CPC++|CPC++]]
| b700
| Mar 26, 2014
| [[CPC old generation|CPC range]]
| Freeware
| [http://cpcrulez.fr/emulateurs_download-WIN-CPC_plus_plus.htm]
|-
| [[CPC3D/CPC32]]
| 0.3
| Feb 8, 2003
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.angelfire.com/retro2/cpc3d/]
|-
| [[CPCE|CPCE]]
| 1.94
| Jun 2, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cngsoft.no-ip.org/cpce/]
|-
| [[CPCEC|CPCEC]]
| 20200622
| Jun 6, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open source
| [http://cngsoft.no-ip.org/cpcec.htm]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[CPCEmuPower|CPCEmuPower]]
| 2005
| May 31, 2020
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [https://www.cpcwiki.eu/forum/emulators/cpcepower-v2005/]
|-
| [[CPCSharp|CPCSharp]]
| 1.0.0-beta1
| Apr 7, 2021
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/dolbz/CPCSharp/releases/]
|-
| [[CPCwin|CPCwin]]
| 1.0
| Dec 4, 1997
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPCWIN10.ZIP]
|-
| [[CPE|CPE]]
| 5.2
| Apr 21, 1997
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/CPE52.ZIP]
|-
| [[CPvC|CPvC]]
|
| Oct 7, 2020
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/alybaek2/cpvc]
|-
| [[DSP|DSP]]
| 0.18
| Dec 31, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Game Boy]], [[Nintendo NES]], [[Sega Master System]], [[ColecoVision]], [[Arcade]]
| Open source
| [https://github.com/leniad/dsp-emulator/]
|-
| [[ep128emu|ep128emu]]
| 2.0.11
| Jan 20, 2017
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[Enterprise]]
| Donationware & Open source
| [http://sourceforge.net/projects/ep128emu/]
|-
| [[MESS|MAME]]
| 0.201
| Aug 30, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[KC Compact]], [[Aleste 520EX]] & lots of other computer systems
| Open source
| [http://mamedev.org/release.html]
|-
| [[MTMW|MTMW]]
| 1.30B
| Jan 11, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Enterprise]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/MTMW130B.ZIP]
|-
| [[NO$CPC|NO$CPC]]
| 1.8
| Nov 2, 2000
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Freeware
| [http://problemkaputt.de/cpc.htm]
|-
| [[PC-CPC|PC-CPC]]
| 0.1at b29
| Nov 17, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://cpcrulez.fr/emulateurs_download-WIN-PC-CPC.htm]
|-
| [[Retro Virtual Machine|Retro Virtual Machine]]
| 2.0 BETA-1 R7
| Jul 10, 2019
| [[CPC old generation|CPC range]], [[ZX Spectrum]]
| Donationware
| [https://www.retrovirtualmachine.org]
|-
| [[Roland Emulator|Roland]]
| 0.70
| Apr 20, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://www.rolandemu.de/en/downloads.html]/[https://github.com/raldus/roland GitHub]
|-
| [[SugarBox|SugarBox]]
| 0.29
| Jan 22, 2018
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Open-Source
| [http://sugarbox.free.fr/] [https://github.com/Tom1975/SugarboxV2]
|-
| [[vbCPC|vbCPC]]
| 1.06
| Apr 7, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.emu-france.com/news/9609-ordi-vbcpc-v1-0-6/]
|-
| [[VirtualCPC|Virtual CPC]]
| 1.1
| Aug 8, 2011
| [[CPC old generation|CPC range]]
| Freeware
| [http://users.otenet.gr/~sulfonic/cpc/]
|-
| [[WinApe|WinAPE]]
| 2.0b2
| Jan 5, 2016
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
| Donationware
| [http://www.winape.net/]
|-
| [[WinCPC|WinCPC]]
| 0.9.26
| Feb 1, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.wincpc.ch/index.php?topic=projects-wincpc]
|-
| [[XNACPC|XNACPC]]
| 1.0
| Nov 11, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
|-
| [[Yage|Yage]]
| 0.91
| Oct 24, 1998
| [[CPC old generation|CPC range]]
| Freeware
| [ftp://ftp.lip6.fr/pub/amstrad/emulator/YAGE091.ZIP]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Donationware & Open source
| [https://github.com/chernandezba/zesarux]
|}

== Emulation Core ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| libretro-cap32 (for RetroArch)
| 1.2.2
| Jul 19, 2015
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/libretro/libretro-cap32]
|-
| libretro-crocods (for RetroArch)
| 0.1
| Feb 28, 2017
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/libretro/libretro-crocods]
|-
| SugarLibRetro (for RetroArch)
| git
| -
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/Tom1975/SugarLibRetro] (wraps independent lib https://github.com/Tom1975/CPCCore)
|}

= Home Consoles =

== Microsoft XBOX ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Arnold|ArnoldX]]
| v5
| Apr 20, 2010
| [[CPC old generation|CPC range]], [[Plus|Plus range]]
|
| [http://forums.xbox-scene.com/index.php?showtopic=711667]
|-
| [[CoinOPS|CoinOPS]]
| 5
| Oct 18, 2012
| [[CPC old generation|CPC range]] & lots of other computer systems
|
| [http://coinopsproject.freeforums.org/viewtopic.php?f=0&t=1213]
|}

== Microsoft Xbox 360 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[XNACPC|XNACPC]]
| 1.0
| Nov 11, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://www.gavpugh.com/2011/11/11/xnacpc-xbox-360-amstrad-cpc-emulator-released/]
|}

== Nintendo Wii ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Wiituka|Wiituka]]
| 0.98.8
| May 15, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://wiituka.dantoine.org/]
|}

== Sega Dreamcast ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCast|CPCast]]
|
| May 6, 2006
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.dcemu.co.uk/vbulletin/showthread.php?t=24100]
|-
| [[DreamCPC|DreamCPC]]
| Alpha 3
| Oct 16, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://jm1200.free.fr/index.php?r=2]
|}

== Sony PS2 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[PCPC|PCPC]]
|
| Dec 22, 2004
| [[CPC old generation|CPC range]]
| Open source
| [http://ps2emu.dcemu.co.uk/pcpc.shtml]
|}

== Sony PS3 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice32|Caprice32]]
| 4.1.0 DBG
| Apr 9, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://psx-scene.com/forums/content/caprice32-4-1-0-dbg-emulator-ps3-2119/]
|}

= Handheld Consoles =

== Dingoo A320 / A330 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pituka|Pituka (Dingux)]]
| 0.8pre
| Aug 19, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://david.dantoine.org/proyecto/4/]
|-
| [[Caprice|Dingux-CAP32]]
| 1.1.2
| Oct 17, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/105-Amstrad/]
|}

== GamePark GP32 / GP2X / Wiz / Caanoo ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Pituka|Pituka (GP32)]]
| 1d
| May 15, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://david.dantoine.org/proyecto/4/]
|-
| [[Caprice|CapriceGP2x]]
| 0.5
| Feb 22, 2006
| [[CPC old generation|CPC range]]
| Open source
| [http://wiki.gp2x.org/wiki/CapriceGP2x]
|-
| [[Caprice|GP2X-CAP32]]
| 1.5.1
| Aug 29, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/42-Amstrad/]
|-
| [[Caprice|Wiz-CAP32]]
| 1.1.0
| Aug 29, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/89-Amstrad/]
|-
| [[Caprice|Caanoo-CAP32]]
| 1.1.3
| Apr 24, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/165-Amstrad/]
|}

== GCW Zero ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|Dingux-CAP32]]
| 1.1.2
| May 25, 2014
| [[CPC old generation|CPC range]]
| Open source
| [http://boards.dingoonity.org/gcw-releases/caprice32-%28amstrad-cpc%29/]
|}

== JXD S5110 / S601 & Yinlips G18 ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|JXD-CAP32]]
| 1.1.1
| Oct 27, 2012
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/206-Amstrad/]
|}

== Nintendo DS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[AmeDS|AmeDS]]
| 4.0
| Apr 25, 2010
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.portabledev.com/pages/ds/jeuxdev.-perso/ameds.php]
|-
| [[CrocoDS|CrocoDS]]
| 2.0
| Nov 9, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.kyuran.be/blog/2007/11/09/crocods-20-2/]
|}

== Odroid GO ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CapriceESP32|CapriceESP32]]
|
| Dec 3, 2020
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/grantrismo/CapriceESP32]
|}

== Pandora ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice|Pandora-CAP32]]
| 1.1.0
| Jun 27, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/131-Amstrad/]
|}

== Sony PSP ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[Caprice32 PSP]]
| 4.2.0.2
| Nov 28, 2007
| [[CPC old generation|CPC range]]
| Open source
| [http://psp.akop.org/caprice32]
|-
| [[CPCPSP|CPCPSP]]
| 0.1
| Dec 24, 2005
| [[CPC old generation|CPC range]]
| Freeware
| [http://dl.qj.net/psp/emulators/cpcpsp-v01.html]
|-
| [[PSPCAP32|PSPCAP32]]
| 1.5.1
| Aug 21, 2009
| [[CPC old generation|CPC range]]
| Open source
| [http://zx81.zx81.free.fr/serendipity/index.php?/categories/3-Amstrad/]
|}

= Smartphones / PDA / SoC =

== Android ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[andcpc]]
| 1.5.1
| Apr 4, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://code.google.com/p/andcpc/]
|-
| [[CPCDroid]]
| 1.5.1
| Mar 2, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://fmsdevel.wisecoding.es/blog/cpcdroid---2011-03-02]
|-
| [[CPCemu|CPCemu]]
| 2.0
| Jan 7, 2021
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.cpc-emu.org/]
|-
| [[Droid-CPC]]
| 1.1.01
| Dec 15, 2016
| [[CPC old generation|CPC range]]
| Commercial
| [http://play.google.com/store/apps/details?id=com.kokak.droidcpc]
|}

== BlackBerry ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[BB-CPC|BB-CPC]]
| 1.0.1.3
| Jul 15, 2013
| [[CPC old generation|CPC range]]
| Commercial
| [http://appworld.blackberry.com/webstore/content/30963891/]
|}

== iOS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CrocoDS]]
| 2.1
| Jun 21, 2013
| [[CPC old generation|CPC range]]
| Open source
| [http://github.com/redbug26/crocods]
|}

== Maemo ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPCm]]
| 1.20-1
| Apr 27, 2010
| [[CPC old generation|CPC range]]
| Open source
| [http://maemo.org/downloads/product/Maemo5/cpcm/]
|}

== Palm OS ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CaPriCe for Palm OS|CaPriCe for Palm OS]]
| 2.8
| Jun 28, 2011
| [[CPC old generation|CPC range]]
| Open source
| [http://frederic.coste.pagesperso-orange.fr/cpc/cpc_en.htm]
|-
| [[CoPaCabana|CoPaCabana]]
| 0.75
| Dec 4, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://copacabana.emuunlim.com/]
|}

== Pocket PC ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CaPriCe|PocketCaprice]]
| 0.9
| Aug 19, 2007
| [[CPC old generation|CPC range]]
| Freeware
| [http://www.clubic.com/telecharger-fiche44888-pocketcaprice.html]
|}

== Raspberry Pi ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[CPC4Rpi|#CPC4Rpi]]
| 1.1
| Dec 19, 2013
| [[CPC old generation|CPC range]]
| Open source
| [https://www.raspberrypi.org/forums/viewtopic.php?f=78&t=63820]
|-
| [[CapriceRPI|CapriceRPI]]
| 1.3
| Feb 28, 2016
| [[CPC old generation|CPC range]]
| Open source
| [https://github.com/KaosOverride/CapriceRPI]
|-
| [[ZEsarUX|ZEsarUX]]
| 9.0
| Aug 19, 2020
| [[CPC old generation|CPC range]], [[ZX Spectrum]], [[ZX80/81]], [[Jupiter ACE]], [[Sam Coupe]], [[Sinclair QL]], [[MSX 1]], [[ColecoVision]], [[SG-1000]]
| Open source
| [https://github.com/chernandezba/zesarux]
|}

== Symbian ==

{| class="wikitable sortable" style="width:100%"
! Name
! Actual version
! Last release
! Emulated systems
! License
! Link
|-
| [[S60-CPC|S60-CPC]]
| 0.74
| Feb 21, 2006
| [[CPC old generation|CPC range]]
| Open source
| [http://kokak.free.fr/s60cpc.htm]
|}

= Hardware =

*[[CPC TREX|CPC TREX]] TurboCPC core running on a terasIC T-Rex C1 FPGA board
*[[C-ONE|CPC-ONE]] TurboCPC core running on the C-One FPGA board
*[http://ralferoo.blogspot.fr/ CPC FPGA] CPC emulation running on a custom made FPGA board
*[[FPGAmstrad|FPGAmstrad]] CPC emulation running on a NEXYS2 FPGA board
*[http://github.com/mist-devel/mist-board/wiki MIST board] FPGA board implementing Amstrad CPC and various other 8-bit and 16-bit computers

= Emulation Tools =

*[[ConvImgCPC|ConvImgCPC]]
*[[CPCDiskXP|CPCDiskXP]]
*[[CPCGamesCD-CPCLoader|CPCGamesCD-CPCLoader]]
*[[CPCTapeXP|CPCTapeXP]]
*[[CPRTools|CPRTools]]
*[[Dsktools|Dsktools]]
*[[ManageDSK|ManageDSK]]
*[[WriteDSK|WriteDSK]]

= Emulator Detection =

*[[Emulator_IDs|Emulator IDs]]

[[Category:Emulator| ]]

CRTC

2022-07-29T18:02:31Z

Longshot:

* ''This is an article about the "Cathode Ray Tube Controller" hardware unit of the Amstrad CPC. For the cpc scene member see [[ChaRleyTroniC]]''

The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.

NOTE: This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.

== Overview ==

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Part number''||''Manufacturer''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|-
|UM6845||UMC||0
|-
|UM6845R||UMC||1
|-
|MC6845||Motorola||2
|-
|AMS40489||Amstrad||3 (note 1)
|-
|40226||Amstrad||4 (note 2)
|}

'''NOTES'''

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way.

As far as I know, the type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.

4. As far as I know, the KC compact used HD6845R only.

== Timings and relating with Z80 instructions count ==

Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106
(To be extracted/edited to conform to wiki good practices).

==Programming==

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''I/O port address''||''Function''||''Read/Write''
|-
|&BCxx||Select 6845 register||Write only
|-
|&BDxx||Write 6845 register data||Write only
|-
|&BExx||(note 1)||Read only
|-
|&BFxx||(note 1)||Read only
|-
|}

'''NOTE'''

1. The function of these I/O ports is dependant on the CRTC type

2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.

==Addressing==

The following table defines the generated memory address from the CRTC and Gate-Array signals.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Memory Address Signal''||''Signal source''||''Signal name''
|-
|A15||6845||MA13
|-
|A14||6845||MA12
|-
|A13||6845||RA2
|-
|A12||6845||RA1
|-
|A11||6845||RA0
|-
|A10||6845||MA9
|-
|A9||6845||MA8
|-
|A8||6845||MA7
|-
|A7||6845||MA6
|-
|A6||6845||MA5
|-
|A5||6845||MA4
|-
|A4||6845||MA3
|-
|A3||6845||MA2
|-
|A2||6845||MA1
|-
|A1||6845||MA0
|-
|A0||Gate-Array||CCLK
|-
|}

CRTC generates the address, Gate-Array reads the data and converts it to pixels based on the current mode.

== DISPTMG ==

DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2 or 5.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

== HSYNC and VSYNC ==

On CPC, HSYNC and VSYNC from the CRTC are passed into the Gate-Array.

When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.

The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.

If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51.

On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.

The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.

Using CRTC1, VSYNC width value 0 means a value of 16.

== The 6845 Registers ==

The Internal registers of the 6845 are:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
|0||Horizontal Total||00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character == 1μs.
|-
|1||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|2||Horizontal Sync Position||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 on some CRTC), should always be more than 8; VSync width in scan-lines. (0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|4||Vertical Total||x0000000||38||Height of the screen, in characters.
|-
|5||Vertical Total Adjust||xxx00000||0||Measured in scanlines, can be used for smooth vertical scrolling on CPC.
|-
|6||Vertical Displayed||x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|7||Vertical Sync position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00||0||00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|9||Maximum Raster Address||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor not used on CPC. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|14||Cursor Address (High)||xx000000||0
|-
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only
|-
|17||Light Pen Address (Low)||00000000||||Read Only
|-
|}

registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.

Details about Reg. 12 and Reg. 13 specifically:

.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'

So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

== CRTC Differences ==

In this section I will attempt to identify all the differences between each CRTC.

The following tables list the functions that can be accessed for each type:

Type 0

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 1

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|}

Type 2

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

Type 3 and 4

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||0||Select internal 6845 register||Write Only
|-
|0||1||Write to selected internal 6845 register||Write Only
|-
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only
|-
|}

It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type:

{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1||2||3||4
|-
|0||Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|2||Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|3||Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|4||Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|5||Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|6||Vertical Displayed||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|7||Vertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|8||Interlace and Skew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|10||Cursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|11||Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|12||Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)
|-
|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|}

'''Notes'''

1. On type 0 and 1, if a Write Only register is read from, "0" is returned.

2. See the document "Extra CPC Plus Hardware Information" for more details.

3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.

== Horizontal and Vertical Sync (R3) ==

UM6845:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

UM6845R:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.

MC6845:

Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Pre-ASIC/ASIC:

Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

== UM6845R and R31 ==

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns 0x0ff.

R31 doesn't exist on types 0,2,3.

== UM6845R and R12/R13 ==

The UM6845R differs to other CRTC in respect of R12/R13.

When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.

Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.

In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.

== UM6845R status register ==

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.
This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

== Datasheets ==

* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi) (aka type 0)]]
* [[Media:Um6845.umc.pdf|UM6845 (UMC) (aka type 0)]]
* [[Media:Um6845r.umc.pdf|UM6845R (UMC) (aka type 1)]]
* [[Media:Mc6845.motorola.pdf|MC6845 (Motorola) (aka type 2)]]

* [[VHDL implementation of the 6845]]

== Clones ==
* [CM607P a Bulgarian clone made in Pravetz factory]
* [EF6845P by Thomson Semiconductors]

== Tools about CRTC ==

* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects - by [[Elmar Krieger]] ] (DSK for Emulators)

== Links ==

* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTCs on grimware]
* [http://logonsystem.fr/down/ACCC1.2-EN.pdf Amstrad Cpc Crtc Compendium] Latest (2022!!) document containing in-depth info about CRTC programming on CPC.

==Related pages==

*[[Gate Array]]

*[[ASIC]]

*[[Video modes]]

*[[Synchronising with the CRTC and display]] : technic and details on the relationship between Gate Array and CRTC.

[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Programming]] [[Category:Datasheet]] [[Category:Graphic]]

File:Booth2018 01137.jpg

2018-06-16T12:36:42Z

Longshot: Longshot uploaded a new version of File:Booth2018 01137.jpg

Legendaries [[Longshot]] and [[Overflow]] at [[Revision]] 2018, showing [[Logon System]] is somehat alive and well.

File:Booth2018 01137.jpg

2018-06-16T12:35:25Z

Longshot: Longshot uploaded a new version of File:Booth2018 01137.jpg

Legendaries [[Longshot]] and [[Overflow]] at [[Revision]] 2018, showing [[Logon System]] is somehat alive and well.

File:Booth2018 01137.jpg

2018-06-16T12:29:33Z

Longshot: Longshot uploaded a new version of File:Booth2018 01137.jpg

Legendaries [[Longshot]] and [[Overflow]] at [[Revision]] 2018, showing [[Logon System]] is somehat alive and well.

Logon System

2018-03-04T00:10:18Z

Longshot:

[[Image:LogonTeam1990.jpg|thumb|Logon System 1990 Amstrad Expo]]
[[Image:LogonSystem2006.jpg|thumb|Logon System. 22 Sept 2006]]
'''Logon System''' is a French demo group which is very famous due to really great demos and new techniques the coders at Logon use. While [[The Demo]] was for a very long time the best megademo ever released on the CPC, [[Overflow]]'s demo III was one of the most extreme hardware demo ever produced.

== Members ==
* [[Digit]]
* [[Eros]]
* [[Fred Crazy]]
* [[Longshot]]
* [[Overflow]]
* [[Pict]]
* [[Slash]]
* [[Brad]]
* [[Naminu]]
* [[Rubi]]

[[Category:Scene group]]

Logon System

2018-03-04T00:09:00Z

Longshot:

[[Image:LogonTeam1990.jpg|thumb|Logon System 1990 Amstrad Expo]]
[[Image:LogonSystem2006.jpg|thumb|Logon System. 22 Sept 2006]]
'''Logon System''' is a french demo group which is very famous due to really great demos and new techniques the coders at Logon used. While [[The Demo]] was for a very long time the best megademo ever released on the CPC, [[Overflow]]'s demo III was one of the most extreme hardware demo ever produced.

== Members ==
* [[Digit]]
* [[Eros]]
* [[Fred Crazy]]
* [[Longshot]]
* [[Overflow]]
* [[Pict]]
* [[Slash]]
* [[Brad]]
* [[Naminu]]
* [[Rubi]]

[[Category:Scene group]]

AFC Expo 1

2018-03-04T00:04:16Z

Longshot:

'''AFC meeting 1''' was the first meeting of [[AFC]] association
Meeting was organised the 9.10th May 1992 near Paris

== Participants ==
* [[ZALKO]]
* [[Gouss]]
* [[Chany]]
* [[TwoMag]]
* [[CJC]] (CCC)
* [[Steph]] (FREEWARE)
* [[LBC]](FANATIC)
* [[MOAH]] (ANEKHOU)
* [[Cobra]]
* [[UDOL]] (THE OTHER WORLD)
* [[Madram]] (THE OTHER WORLD)
* [[SYNDROME]]
* [[GREES]]
* [[MADE]] (DISC FULL)
* [[NEOFYT]]
* [[TOM&JERRY]]
* [[WILD AST SYSTEM]]
* [[ENO]] (AST SYSTEM)
* [[Cyril Houzé]] (KOD, SOS FANZINE)
* [[Cedric QUETIER]] (KOD)
* [[Fred Crazy]]
* [[Longshot]]
* [[Newsky]]
* [[Xor]]
* [[Niki]] (EUREKA)

== Photos ==
<gallery caption="Articles">
Image:AFC0101.jpg
Image:AFC0102.jpg
Image:AFC0103.jpg
</gallery>

[[Category:CPC events]]
[[Category:Stub]]

AFC Expo 1

2018-03-03T21:34:17Z

Longshot: /* Participants */

'''AFC meeting 1''' was the first meeting of [[AFC]] association
Meeting was organised the 9.10th May 1992 near Paris

== Participants ==
* [[Gouss]]
* [[Chany]]
* [[TwoMag]]
* [[CJC]] (CCC)
* [[Steph]] (FREEWARE)
* [[LBC]](FANATIC)
* [[MOAH]] (ANEKHOU)
* [[Cobra]]
* [[UDOL]] (THE OTHER WORLD)
* [[Madram]] (THE OTHER WORLD)
* [[SYNDROME]]
* [[GREES]]
* [[MADE]] (DISC FULL)
* [[NEOFYT]]
* [[TOM&JERRY]]
* [[WILD AST SYSTEM]]
* [[ENO]] (AST SYSTEM)
* [[Cyril Houzé]] (KOD, SOS FANZINE)
* [[Cedric QUETIER]] (KOD)
* [[Fred Crazy]]
* [[Longshot]]
* [[Newsky]]
* [[Xor]]
* [[Niki]] (EUREKA)

== Photos ==
<gallery caption="Articles">
Image:AFC0101.jpg
Image:AFC0102.jpg
Image:AFC0103.jpg
</gallery>

[[Category:CPC events]]
[[Category:Stub]]

AFC Expo 1

2018-03-03T21:32:17Z

Longshot: /* Participants */

'''AFC meeting 1''' was the first meeting of [[AFC]] association
Meeting was organised the 9.10th May 1992 near Paris

== Participants ==
* [[Gouss]]
* [[Chany]]
* [[TwoMag]]
* [[CJC]] (CCC)
* [[Steph]] (FREEWARE)
* [[LBC]](FANATIC)
* [[MOAH]] (ANEKHOU)
* [[Cobra]]
* [[UDOL]] (THE OTHER WORLD)
* [[MADRAM]] (THE OTHER WORLD)
* [[SYNDROME]]
* [[GREES]]
* [[MADE]] (DISC FULL)
* [[NEOFYT]]
* [[TOM&JERRY]]
* [[NEW SKY]]
* [[WILD AST SYSTEM]]
* [[ENO]] (AST SYSTEM)
* [[KOD]] (SOS FANZINE)
* [[Cedric QUETIER]] (KOD)
* [[Fred Crazy]]
* [[Longshot]]
* [[Madram]]
* [[Newsky]]
* [[Xor]]

... to complete

== Photos ==
<gallery caption="Articles">
Image:AFC0101.jpg
Image:AFC0102.jpg
Image:AFC0103.jpg
</gallery>

[[Category:CPC events]]
[[Category:Stub]]

Euromeeting 0

2018-03-03T21:24:57Z

Longshot:

14-16 April 1990

This meeting was organised by [[Logon System]] in the Stains's town, 10 km at north of Paris.
Lot of people were there and it was the first time that the french cpc scene meet the german one.

== Participants ==
* [[Cristal]]
* [[Digit]]
* [[Famous Cach]]
* [[Fred Crazy]]
* [[Longshot]]
* [[Naminu]]
* [[Pict]]
* [[Rubi]]
* [[Slash]]
* [[Syntax Error]]
* [[Thriller]]
* [[Xor]]

More...

[[Category:CPC events]]
[[Category:Stub]]

Technical documentation

2008-06-30T22:50:02Z

Longshot:

== BASIC / Firmware / CP/M ==

* [[Technical information about Locomotive BASIC]]

== Built-in connectors: pinout ==

* [[Connector:2nd disc drive (CPC664, CPC6128, CPC6128+)|2nd disc drive (CPC664, CPC6128, CPC6128+)]]
* [[Connector:Analogue joystick (CPC Plus only)|Analogue joystick (CPC Plus only)]]
* [[Connector:Aux socket (CPC Plus only)|Aux socket (CPC Plus only)]]
* [[Connector:Cassette recorder|Cassette recorder]]
* [[Connector:Digital joystick|Digital joystick]]
* [[Connector:Expansion port|Expansion port]]
* [[Connector:Floppy|Floppy]]
* [[Connector:Monitor|Monitor]]
* [[Connector:Printer port|Printer port]]
* [[Connector:Stereo sound|Stereo sound]]
* [[Connector:Tape|Tape]]

== Hardware extensions ==

* [[Programming:CPC Booster|CPC Booster]]
* [[Programming:SYMBiFACE II|SYMBiFACE II]]

== How to's ==

* [[Changing the drive belt]]
* [[A guide to running software on a real Amstrad CPC/CPC Plus computer|A Guide to running software on a real CPC!]]
* [[Modify PC floppy drives|Modify PC floppy drives to work on a CPC]]
* [[Transfering Alkatraz protected tapes and most games!]]
* [[Willem Programmer]] - how to program eproms using the Willem eprom programmer.
* [[Guide on how to connect a 3.5" drive to a CPC6128/664]]

== Internal components ==

* [[8255]] - PIO - I/O controller
* [[Arnold V specs|Arnold_V_specs]] - Arnold V (CPC+) Technical Specification
* [[AY-3-8912]] - Sound chip / keyboard controller
* [[Cassette data information]] - Information about the cassette storage system
* [[CRTC]] - Video chip
* [[Gate Array]] - Custom chip (frequency generation, colors, bank switching)
* [[I/O Port Summary]] - map of all known I/O ports of the CPC
* [[Power Supply for CPC and CPC plus]]
* [[Serial interface]] - how to use the DART and 8253 chips of an Amstrad-compatible serial interface

== Service Manuals ==

* [http://www.cpcwiki.eu/manuals/Amstrad%20CPC%20464%20Service%20Manual.en.rar Amstrad CPC 464 Service Manual]
* [http://www.cpcwiki.eu/manuals/Amstrad%20CPC%20664%20Service%20Manual.en.rar Amstrad CPC 664 Service Manual]
* [http://www.cpcwiki.eu/manuals/Amstrad%20CPC%206128%20Service%20Manual.en.rar Amstrad CPC 6128 Service Manual]
* [http://www.cpcwiki.eu/manuals/DDI-1%20FD-1%20Service%20Manual.en.rar Amstrad DDI-1 FD-1 Service Manual]
* [http://www.cpcwiki.eu/manuals/Amstrad%20PCW%208256-8512%20Service%20Manual.en.rar Amstrad PCW 8256-8512 Service Manual]
* [http://www.cpcwiki.eu/manuals/CPC464-6128-GT65-CTM644-MP3-CT11%20Amendment%20Service%20Manual.en.rar Amstrad CPC464-6128-GT65-CTM644-MP3-CT11 Amendment Service Manual]
* [http://logon.system.free.fr/down/Service%20Manual%20Amstrad%20Plus.zip Amstrad 464PLUS-6128PLUS-GX4000-MM12-CM14 Service Manual]

== Specifications ==

* [[Disc format|Disc formats]]
* [[List of file formats]]
* [[Format:SGX (SymbOS graphic files)|SGX (SymbOS graphic files)]]
* [[Format:VID (SymbOS video files)|VID (SymbOS video files)]]

[[Category:Hardware]] [[Category:Manual]]

Demogroups

2008-06-30T22:43:15Z

Longshot:

''For an overview of the CPC scene members, you can have a look at the''

* [[CPC scene members|List of CPC scene members]]
* [http://www.cpcwiki.eu/index.php/Category:CPC_scene_members Category of CPC scene members]

''You can also check the [http://www.cpcwiki.eu/index.php/Category:Demos Demos category] for productions/releases.''

 This is a list of the CPC scene '''demo groups''', which have been or are still active.

== France ==

* [[5KB]]
* [[Arkos]] ([http://www.arkos.cpcscene.com Arkos homepage])
* [[AST System]]
* [[BCAV]]
* [[Contrast]]
* [[Da Boxon Team]]
* [[Fefesse]]
* [[Futur's]] ([http://www.futurs.cpcscene.com Futur's homepage])
* [[GPA]] ([http://tj.gpa.free.fr Tom et Jerry's homepage])
* [[Hard'OS]] ([http://bdciron.cpcscene.com BDC Iron's homepage])
* [[Impact CPC]] ([http://impact.cpcscene.com Impact's forum])
* [[Kill or die]]
* [[Krad'os Crack'ers]]
* [[Logon System]] ([http://logon.system.free.fr Logon System's website])
* [[Malibu Crackers]]
* [[Mortel]]
* [[NPS]] (for Nul Part System) ([http://nulpartsystem.free.fr NPS homepage])
* [[Overlanders]]
* [[Paradox]]
* [[Rebels]]
* [[Revival]]
* [[Les Sucres en Morceaux]] ([http://scampin.chez-alice.fr/cpc Sucres en Morceaux homepage])
* [[Static]]
* [[The Addams Fanz]] ([http://tafcpc.free.fr TAF homepage])

== Germany ==

* [[ALC]]
* [[Armaxess]]
* [[BENG!]] (also international)
* [[Benediction]]
* [[Bollaware]]
* [[Cadjo Clan]]
* [[CBS]]
* [[CGS]]
* [[Commotion]]
* [[CRT]]
* [[Exodus]]
* [[Frankenteam]]
* [[FutureSoft]]
* [[GCS]]
* [[GOS]]
* [[HJT]]
* [[Inicron]]
* [[KKB]]
* [[Merlyn]]
* [[MOPS]]
* [[Necron]]
* [[PDW]]
* [[POW]]
* [[The Rejects]]
* [[SCUG]]
* [[SymbiosiS]]
* [[TCT]]
* [[TGS]]
* [[Wizcat]]

== Greece ==

* [[Dirty Minds]]
* [[Chaos]] [http://www.geocities.com/chaoscpc/ Chaos Homepage]

== Ireland ==

* [[The Firm]]

== Netherlands ==

* [[Dragonbreed Wetware]]

== Spain ==

* [[Zona Neutra]] ([http://www.zonan.org Zona Neutra website])
* [[ESP Soft]] ([http://www.amstrad.es/espsoft Esp Soft website])

== Switzerland ==

* [[UNiX]]

== United Kingdom ==

* [[Bitmap Vandals]]
* [[Conspiracy]]
* [[Discovery]]
* [[Donut System]]
* [[Lords of Justice]]
* [[STS]]
* [[Systeme D]]
* [[The Underground]]
* [[Wendos PDS/Wendos Interactive]]

and many, many more...

[[Category:Scene_group]]

Demogroups

2008-06-30T22:39:50Z

Longshot:

''For an overview of the CPC scene members, you can have a look at the''

* <a href="CPC scene members">List of CPC scene members</a>
* <a href="http://www.cpcwiki.eu/index.php/Category:CPC_scene_members">Category of CPC scene members</a>

''You can also check the <a href="http://www.cpcwiki.eu/index.php/Category:Demos">Demos category</a> for productions/releases.''

 This is a list of the CPC scene '''demo groups''', which have been or are still active.

== France ==

*
* [[5KB]] 
*
*
* [[
* Arkos]] (<a href="http://www.arkos.cpcscene.com">Arkos homepage</a>)
*
* [[
* AST System]]
*
* [[BCAV]]
*
* <a href="Contrast">Contrast</a>
* <a href="Da Boxon Team">Da Boxon Team</a>
* <a href="Fefesse">Fefesse</a>
* <a href="Futur's">Futur's</a> (<a href="http://www.futurs.cpcscene.com">Futur's homepage</a>)
* <a href="GPA">GPA</a> (<a href="http://tj.gpa.free.fr">Tom et Jerry's homepage</a>)
* <a href="Hard'OS">Hard'OS</a> (<a href="http://bdciron.cpcscene.com">BDC Iron's homepage</a>)
* <a href="Impact CPC">Impact CPC</a> (<a href="http://impact.cpcscene.com">Impact's forum</a>)
* <a href="Kill or die">Kill or die</a>
* <a href="Krad'os Crack'ers">Krad'os Crack'ers</a>
* <a href="Logon System">Logon System</a> (<a href="http://logon.system.free.fr">Logon System's homepage</a>)
* <a href="Malibu Crackers">Malibu Crackers</a>
* <a href="Mortel">Mortel</a>
* <a href="NPS">NPS</a> (for Nul Part System) (<a href="http://nulpartsystem.free.fr">NPS homepage</a>)
* <a href="Overlanders">Overlanders</a>
* <a href="Paradox">Paradox</a>
* <a href="Rebels">Rebels</a>
* <a href="Revival">Revival</a>
* <a href="Les Sucres en Morceaux">Les Sucres en Morceaux</a> (<a href="http://scampin.chez-alice.fr/cpc">Sucres en Morceaux homepage</a>)
* <a href="Static">Static</a>
* <a href="The Addams Fanz">The Addams Fanz</a> (<a href="http://tafcpc.free.fr">TAF homepage</a>)

== Germany ==

* <a href="ALC">ALC</a>
* <a href="Armaxess">Armaxess</a>
* <a href="BENG!">BENG!</a> (also international)
* <a href="Benediction">Benediction</a>
* <a href="Bollaware">Bollaware</a>
* <a href="Cadjo Clan">Cadjo Clan</a>
* <a href="CBS">CBS</a>
* <a href="CGS">CGS</a>
* <a href="Commotion">Commotion</a>
* <a href="CRT">CRT</a>
* <a href="Exodus">Exodus</a>
* <a href="Frankenteam">Frankenteam</a>
* <a href="FutureSoft">FutureSoft</a>
* <a href="GCS">GCS</a>
* <a href="GOS">GOS</a>
* <a href="HJT">HJT</a>
* <a href="Inicron">Inicron</a>
* <a href="KKB">KKB</a>
* <a href="Merlyn">Merlyn</a>
* <a href="MOPS">MOPS</a>
* <a href="Necron">Necron</a>
* <a href="PDW">PDW</a>
* <a href="POW">POW</a>
* <a href="The Rejects">The Rejects</a>
* <a href="SCUG">SCUG</a>
* <a href="SymbiosiS">SymbiosiS</a>
* <a href="TCT">TCT</a>
* <a href="TGS">TGS</a>
* <a href="Wizcat">Wizcat</a>

== Greece ==

* <a href="Dirty Minds">Dirty Minds</a>
* <a href="Chaos">Chaos</a> <a href="http://www.geocities.com/chaoscpc/">Chaos Homepage</a>

== Ireland ==

* <a href="The Firm">The Firm</a>

== Netherlands ==

* <a href="Dragonbreed Wetware">Dragonbreed Wetware</a>

== Spain ==

* <a href="Zona Neutra">Zona Neutra</a> (<a href="http://www.zonan.org">Zona Neutra website</a>)
* <a href="ESP Soft">ESP Soft</a> (<a href="http://www.amstrad.es/espsoft">Esp Soft website</a>)

== Switzerland ==

* <a href="UNiX">UNiX</a>

== United Kingdom ==

* <a href="Bitmap Vandals">Bitmap Vandals</a>
* <a href="Conspiracy">Conspiracy</a>
* <a href="Discovery">Discovery</a>
* <a href="Donut System">Donut System</a>
* <a href="Lords of Justice">Lords of Justice</a>
* <a href="STS">STS</a>
* <a href="Systeme D">Systeme D</a>
* <a href="The Underground">The Underground</a>
* <a href="Wendos PDS/Wendos Interactive">Wendos PDS/Wendos Interactive</a>

and many, many more...

<a href="Category:Scene_group">Category:Scene_group</a>

Demogroups

2008-06-30T22:28:06Z

Longshot:

For an overview of the CPC scene members, you can have a look at the

<ul><li> <a href="CPC scene members">List of CPC scene members</a>
</li><li> <a href="http://www.cpcwiki.eu/index.php/Category:CPC_scene_members">Category of CPC scene members</a>
</li></ul>
You can also check the <a href="http://www.cpcwiki.eu/index.php/Category:Demos">Demos category</a> for productions/releases.
 This is a list of the CPC scene demo groups, which have been or are still active.

<h2> France </h2>
<ul><li> <a href="5KB">5KB</a>
</li><li> <a href="Arkos">Arkos</a> (<a href="http://www.arkos.cpcscene.com">Arkos homepage</a>)
</li><li> <a href="AST System">AST System</a>
</li><li> <a href="BCAV">BCAV</a>
</li><li> <a href="Contrast">Contrast</a>
</li><li> <a href="Da Boxon Team">Da Boxon Team</a>
</li><li> <a href="Fefesse">Fefesse</a>
</li><li> <a href="Futur's">Futur's</a> (<a href="http://www.futurs.cpcscene.com">Futur's homepage</a>)
</li><li> <a href="GPA">GPA</a> (<a href="http://tj.gpa.free.fr">Tom et Jerry's homepage</a>)
</li><li> <a href="Hard'OS">Hard'OS</a> (<a href="http://bdciron.cpcscene.com">BDC Iron's homepage</a>)
</li><li> <a href="Impact CPC">Impact CPC</a> (<a href="http://impact.cpcscene.com">Impact's forum</a>)
</li><li> <a href="Kill or die">Kill or die</a>
</li><li> <a href="Krad'os Crack'ers">Krad'os Crack'ers</a>
</li><li> <a href="Logon System">Logon System</a> (<a href="http://logon.system.free.fr">Logon System's homepage</a>)
</li><li> <a href="Malibu Crackers">Malibu Crackers</a>
</li><li> <a href="Mortel">Mortel</a>
</li><li> <a href="NPS">NPS</a> (for Nul Part System) (<a href="http://nulpartsystem.free.fr">NPS homepage</a>)
</li><li> <a href="Overlanders">Overlanders</a>
</li><li> <a href="Paradox">Paradox</a>
</li><li> <a href="Rebels">Rebels</a>
</li><li> <a href="Revival">Revival</a>
</li><li> <a href="Les Sucres en Morceaux">Les Sucres en Morceaux</a> (<a href="http://scampin.chez-alice.fr/cpc">Sucres en Morceaux homepage</a>)
</li><li> <a href="Static">Static</a>
</li><li> <a href="The Addams Fanz">The Addams Fanz</a> (<a href="http://tafcpc.free.fr">TAF homepage</a>)
</li></ul>
<h2> Germany </h2>
<ul><li> <a href="ALC">ALC</a>
</li><li> <a href="Armaxess">Armaxess</a>
</li><li> <a href="BENG!">BENG!</a> (also international)
</li><li> <a href="Benediction">Benediction</a>
</li><li> <a href="Bollaware">Bollaware</a>
</li><li> <a href="Cadjo Clan">Cadjo Clan</a>
</li><li> <a href="CBS">CBS</a>
</li><li> <a href="CGS">CGS</a>
</li><li> <a href="Commotion">Commotion</a>
</li><li> <a href="CRT">CRT</a>
</li><li> <a href="Exodus">Exodus</a>
</li><li> <a href="Frankenteam">Frankenteam</a>
</li><li> <a href="FutureSoft">FutureSoft</a>
</li><li> <a href="GCS">GCS</a>
</li><li> <a href="GOS">GOS</a>
</li><li> <a href="HJT">HJT</a>
</li><li> <a href="Inicron">Inicron</a>
</li><li> <a href="KKB">KKB</a>
</li><li> <a href="Merlyn">Merlyn</a>
</li><li> <a href="MOPS">MOPS</a>
</li><li> <a href="Necron">Necron</a>
</li><li> <a href="PDW">PDW</a>
</li><li> <a href="POW">POW</a>
</li><li> <a href="The Rejects">The Rejects</a>
</li><li> <a href="SCUG">SCUG</a>
</li><li> <a href="SymbiosiS">SymbiosiS</a>
</li><li> <a href="TCT">TCT</a>
</li><li> <a href="TGS">TGS</a>
</li><li> <a href="Wizcat">Wizcat</a>
</li></ul>
<h2> Greece </h2>
<ul><li> <a href="Dirty Minds">Dirty Minds</a>
</li><li> <a href="Chaos">Chaos</a> <a href="http://www.geocities.com/chaoscpc/">Chaos Homepage</a>
</li></ul>
<h2> Ireland </h2>
<ul><li> <a href="The Firm">The Firm</a>
</li></ul>
<h2> Netherlands </h2>
<ul><li> <a href="Dragonbreed Wetware">Dragonbreed Wetware</a>
</li></ul>
<h2> Spain </h2>
<ul><li> <a href="Zona Neutra">Zona Neutra</a> (<a href="http://www.zonan.org">Zona Neutra website</a>)
</li><li> <a href="ESP Soft">ESP Soft</a> (<a href="http://www.amstrad.es/espsoft">Esp Soft website</a>)
</li></ul>
<h2> Switzerland </h2>
<ul><li> <a href="UNiX">UNiX</a>
</li></ul>
<h2> United Kingdom </h2>
<ul><li> <a href="Bitmap Vandals">Bitmap Vandals</a>
</li><li> <a href="Conspiracy">Conspiracy</a>
</li><li> <a href="Discovery">Discovery</a>
</li><li> <a href="Donut System">Donut System</a>
</li><li> <a href="Lords of Justice">Lords of Justice</a>
</li><li> <a href="STS">STS</a>
</li><li> <a href="Systeme D">Systeme D</a>
</li><li> <a href="The Underground">The Underground</a>
</li><li> <a href="Wendos PDS/Wendos Interactive">Wendos PDS/Wendos Interactive</a>
</li></ul>
and many, many more...
<a href="Category:Scene_group">Category:Scene_group</a>

Zebigboss

2008-02-07T17:40:34Z

Longshot:

'''Zebigboss''' (Jean-Philippe Parmentier) was a graphist of the [[Krad'os Crack'ers]] Cpc Demo team. It was a famous graphist and he was working both for many Amiga and Cpc demogroups.

== Releases ==

* [[The Demo]]
* [[S&KOH]]

== Groups ==

* [[Krad'os Crack'ers]]

[[Category:CPC_scene_members]]

Zebigboss

2008-02-07T17:38:46Z

Longshot:

'''Zebigboss''' (Jean-Philippe Parmentier) was a graphist of the [[Krad'os Crack'ers]] Cpc Demo team. It was a famous graphist and he was working both for many Amiga and Cpc demogroups.

== Releases ==

* [[The Demo]]
* [[S&Koh]]
== Groups ==

* [[Krad'os Crack'ers]]

[[Category:CPC_scene_members]]

Programming:Keyboard scanning

2007-11-27T09:07:02Z

Longshot:

== Hardware scancode table ==
{|{{Prettytable|width: 700px; font-size: 2em;}}
|'''Bit: Line''' || '''7''' || '''6''' || '''5''' || '''4''' || '''3''' || '''2''' || '''1''' || '''0'''
|-
|'''&40''' || F Dot || ENTER || F3 || F6 || F9 || CURDOWN || CURRIGHT || CURUP
|-
|'''&41''' || F0 || F2 || F1 || F5 || F8 || F7 || COPY || CURLEFT
|-
|'''&42''' || CONTROL || \ || SHIFT || F4 || ] || RETURN || [ || CLR
|-
|'''&43''' || . || / || : || ; || P || @ || - || ^
|-
|'''&44''' || , || M || K || L || I || O || 9 || 0
|-
|'''&45''' || SPACE || N || J || H || Y || U || 7 || 8
|-
|'''&46''' || V || B || F || G || T || R || 5 || 6
|-
|'''&47''' || X || C || D || S || W || E || 3 || 4
|-
|'''&48''' || Z || CAPSLOCK || A || TAB || Q || ESC || 2 || 1
|-
|'''&49''' || DEL || - || - || - || - || - || - || -
|}

== One line scanning routine ==

This is a routine which scans one line of the keyboard directly. It is approximately 8% faster then the firmware routine and doesn't enable interrupts.

'''Input:''' A = ''line (&40 - &49)''

'''Output:''' A = ''hardware keyboard value''

'''Destroyed:''' BC
<pre>LD A,kbdline ; from 0 to 9 with bdir/bc1=01
LD BC,#F782 ; PPI port A out /C out
OUT (C),C
LD BC,#F40E ; Select Ay reg 14 on ppi port A
OUT (C),C
LD BC,#F6CO ; This value is an AY index (R14)
OUT (C),C
OUT (C),0 ; Validate!!
LD BC,#F792 ; PPI port A in/C out
OUT (C),C
DEC B
OUT (C),A ; Send KbdLine on reg 14 AY through ppi port A
LD B,#F4 ; Read ppi port A
IN A,(C) ; e.g. AY R14 (AY port A)
LD BC,#F782 ; PPI port A out / C out
OUT (C),C
DEC B ; Reset PPI Write
OUT (C),0

Now check for the value from the table e.g. with''''bit x,A''''and a condition e.g.''''jp z,xxxx''''or''''call z,xxxx''''
</pre>
Please note:

* Bit = 0: Key is pressed
* Bit = 1: Key is not pressed

== Complete keyboard scanning routine ==

This routine scans the complete keyboard and writes all key status bits in a map.

<pre>
keymap ds 10 ;map with 10*8 = 80 key status bits (bit=0 key is pressed)

keyscan di ;1 ##%%## C P C VERSION ##%%##
ld hl,keymap ;3
ld bc,#f782 ;3
out (c),c ;4
ld bc,#f40e ;3
ld e,b ;1
out (c),c ;4
ld bc,#f6c0 ;3
ld d,b ;1
out (c),c ;4
ld c,0 ;2
out (c),c ;4
ld bc,#f792 ;3
out (c),c ;4
ld a,#40 ;2
ld c,#4a ;2 44
loop ld b,d ;1
out (c),a ;4 select line
ld b,e ;1
ini ;5 read bits and write into KEYMAP
inc a ;1
cp c ;1
jr c,loop ;2/3 9*16+1*15=159
ld bc,#f782 ;3
out (c),c ;4
ei ;1 8 =211 microseconds
ret
</pre>

[[Category:Programming]]

B-ASIC

2007-06-19T07:57:28Z

Longshot: Instructions for 3.4

'''B-Asic''' is a set of RSX commands allowing to use the Amstrad CPC Plus features from [[BASIC]]. It was written by [[Longshot]] of [[Logon System]].

== Introduction ==
'''B-ASIC''' is a set of RSX instructions to manage the extra features of the '''CPC +'''

RSX instruction signify that each instruction is prefixed by a special char : | on english keyboard and "ù" on french azerty keyboard

Since release 3.0 B-ASIC runs only on CPC range with 128 Kb memory

Main instructions can manage colours and sprites, providing an extra bank of '''128 sprites''' for a total of '''144 sprites''' (since version 3.4)

'''B-ASIC doesn't take any byte of the CPC locomotive Basic memory.'''
(The RSX definition and code for locomative basic are not declared in main memory )
The whole interruption system and RSX managment is modified when B-Asic start.

From a technical point of view, the code of the program BASIC using B-ASIC is copied in a bank, because one bank is always open for the system to store the BASIC code.
So, there are two video pages availables for the user.

A set of new powerful instructions will come in future versions.

== Historics ==
* V1.1 ??/04/1991 Published in Amstrad Cent pour Cent (A100%) magazine N°38 (may/june 1991) New instructions INKF, INKS, BORDERP, INKFRVB, INKSRVB, BORDERRVB
* V1.2 ??/05/1991 Published in A100% N°39 (july/aug 1991)New instructions SPRON,SPROFF,SPRZOOM,SPRXY,SPRTDEF,SPRTON,SPRTOFF, SPRSWAP,SPRPLOT,SPRCOPY,SPRTURNX,SPRTURNY,SPRFILL
* V1.3 ??/08/1991 Published in A100% N°40 (sept/oct 1991)- Corrected bug with MODE instruction with some roms- Corrected bug on prg > 16k- Update instructions SPRTDEF, SPRTON, SPRTOFF- New instructions SPRTORAM, RAMTOSPR, SPRSAVE, SPRLOAD- New instructions RETARDX, RETARDY, MASQUE, SPLIT
* V1.4 ??/??/1992 Published in A100% N°42 ()- B-Asic runs in banks (without RSX managment).
* V2.1 ??/??/1992 - New temporary version with RSX system deviation
* V3.1 ??/??/1992 - 2nd vidéo page. Corrected little bugs.- New instructions POKEASIC, POKEVR, DEFORGXY, DEFORGSPR - New instructions SPRCATCH, INKCOPY,SPRLINK, SPRUNLINK, ERALINK
* V3.2 25/02/2006 - Corrected a bug in table calculation (interrupt function)- Corrected a bug in locomotive firmware (ei before real end interrupt)
* V3.3 27/02/2006 - Corrected bug : Basic code copied in banque 5 at B-Asic boot (it was a problem for progr bigger than 16 kb) since 3.1- New instruction SPRWHERE
* V3.4 24/05/2007 - Corrected bug in SPRWHERE (variable setting between 4000 and 7FFF)- Update instruction SPRCOPY (now accepting sprites number from 0 to 143). Sprites 0 to 15 are real sprites. Now there are 128 sprites instead of 64 in previous version : 64 sprites FAST and 64 sprites SLOW (sprites access for sprites 80 to 143 are slowest than FAST sprites access). These additionnal sprites does not take more space than with 64 in the previous release.- New instruction DOKE,address, 16bitsvalue- Removing instructions RAMTOSPR and SPRTORAM, which are now unuseful. (replaced by SPRCOPY)- New instruction SPRTSTEP,n1,…,nx to play the sprite-way step by step (user action).- New instruction DEFKBDSPR to link one or two super-sprites with keyboard (or joystick) keys (automatic or user activable).- Update instruction CATCH : New name SPRCATCH- New instruction SPRCOLL to manage (automatically or user-activable) collisions for up to 8 super-sprites.- Some optimisations

== Starting B-Asic ==
To use B-Asic, it's very easy. You need only two things :
Get the file named '''B-ASIC.BIN'''
Insert as first line in your basic program the following line :

'''10 IF PEEK(&BC0E)<>&CD THEN OUT &7F00,&C1 :LOAD "B-ASIC.BIN ",&C000 :CALL &C000'''

== Instructions ==
----
=== Colours Instructions Set ===
----
'''INKF,pen,colour'''
* pen=[0..15] colour=[0..4095]
* Modify colour of a pen
* Example : INKF,0,2303
----
'''INKFRVB,pen,red,green,blue'''
* pen=[0..15] red=[0..15] green=[0..15] blue=[0..15]
* Modify colour for a pen using colour elementaries components
* Example : FOR I=0 TO 15:INKFRVB,0,I,0,0:NEXT I
----
'''BORDERP,colour'''
* colour=[0..4095]
* Modify border's colour.
* Example : BORDERP,543
----
'''BORDERRVB,red,green,blue'''
* red=[0..15] green=[0..15] blue=[0..15]
* Modify border colour using colour elementaries components
* Example : FOR I=0 TO 15:BORDERRVB,0,0,0,I:NEXT I
----
'''INKS,pen,colour'''
* pen=[1..15] colour=[0..4095]
* Modify colour of an hardware sprite pen
* Note : The pen 0 cannot be modified. It's the transparent colour.
* Example : INKS,1,3456
----
'''INKSRVB,pen,red,green,blue'''
* pen=[1..15] red=[0..15] green=[0..15] blue=[0..15]
* Modify colour for an hardware sprite pen using colour elementaries components
* Note : The pen 0 cannot be modified. It's the transparent colour.
* Example : FOR I=0 TO 15:INKFRVB,0,I,0,0:NEXT I
----
'''INKCOPY'''
* Copy the whole colour screen palette to sprite palette.
----
=== Sprites Instructions Set ===
----
'''SPROFF,SpriteNumber'''
* SpriteNumber=[0..15]
* Sprite display is disactivated for specified sprite.
* Example : SPROFF,3
----
'''SPRON,SpriteNumber'''
* SpriteNumber=[0..15]
* Sprite display is activated for specified sprite.
* Example : SPRON,3
----
'''SPRZOOM,SpriteNumber,XZoom,YZoom'''
* SpriteNumber=[0..15] XZoom=[0..3] YZoom=[0..3]
* Define sprite zoom for specified sprite.
* If XZoom or YZoom is zeroed, sprite is not displayed
* Zoom value of 1 is no magnify.
* Note : Sprite must be activated by SPRON instruction to be displayed on screen
* Example : SPRZOOM,2,2,1 define the sprite 2 magnification to 2x horiz. and 1x vertically
----
'''SPRXY,SpriteNumber,XPos,YPos'''
* SpriteNumber=[0..15] XPos=[-256..767] YZoom=[-256..255]
* Define sprite position on screen according a mode 2 definition
* Note : Sprite must be activated by SPRON instruction to be displayed on screen
* Example : SPRXY,2,100,80 define sprite 2 position at 100,80 coordinates
----
'''SPRTDEF,SpriteNumber,Address,DurationPer,WaitingPer'''
* SpriteNumber=[0..15] Address=[0..65535] DurationPer=[0..65535] WaitingPer=[0..65535]
* Periods are defined by period of 0,02 second (e.g. 50 = 1 second)
* Define a path for the specified sprite.
* The path is defined by screen positions, given by a set of x,y coordinates defined in memory.
* Each coordinate is defined on 2 bytes (4 bytes for a screen position) in the memory
* The coordinate must be stored on a little endian method, e.g. the less significant byte in first and the most significant byte in second position in memory.
* You can use the instruction DOKE to do that easily (example : |DOKE address, x : |DOKE address+2,y : address=address+4)
* The last x coordinate must take the value F0F0 (hexa) to indicate the path end definition (|DOKE address,&F0F0)
* DurationPer indicates the time while the sprite will run on the path (at the last position the path start again at the fist position).
* If DurationPer is zeroed, so the duration is infinite.
* WaitingPer indicate the start period which occurs when the path will be activated (see SPRTON and SPRTOFF instructions). Note : A same path can be used by one or more sprites. Example : SPRTDEF,3,&3000,0,100 to define for sprite 3 a path defined in &3000 with an infinite loop of the path after 2 seconds of start delay after SPRTON,3 instruction.
----
'''SPRTON,SprNb1,SprNb2,...,SprNbx'''
* SprNbx=[O..15]
* Start the path simultanously for the specified sprites.
* Note : An undefined path for the sprite may occur an erratic behaviour of the sprite started.
* Example : SPRTON,1,5,7 start the path for sprites 1, 5 and 7 simultaneously
----
'''SPRTOFF,SprNb1,SprNb2,...,SprNbx'''
* SprNbx=[0..15]
* Stop the path simultaneously for the specified sprites
* Example : SPRTOFF,1,7 stop the path for sprites 1 and 7 simultanously
----
'''SPRTSTEP,SprNb1,SprNb2,...,SprNbx'''
* SprNbx=[0..15]
* Execute the path step by step for the specified sprites.
* Note : An undefined path for the sprite may occur an erratic behaviour of the sprite started.
* Example : SPRTSTEP,1,5,7 plays one path step (defined with SPRTDEF) for sprites 1, 5 and 7 simultaneously
----
'''SPRSWAP,SpriteNumber1,SpriteNumber2'''
* SpriteNumberx=[0..15]
* Exchange the sprite content of two sprites.
* Note : If SpriteNumber1=SpriteNumber2 it results just a waste of time.
* Example : SPRSWAP,1,5 exchange the graphics data of sprites 1 and 5
----
'''SPRPLOT,SpriteNumber,XPos,YPos,SpritePen'''
* SpriteNumber=[0..15] XPos=[0..15] YPos=[0..15] SpritePen=[0..15]
* Plot a pixel in the specified sprite at specified coordinates
* Note : SpritePen=0 means the transparent pen for sprite
* Example : SPRPLOT,3,10,9,4 plot a pixel pen 4 at coordinates 10,9 of sprite 3
----
'''SPRCOPY,SpriteOrg,SpriteDst'''
* SpriteOrg=[0..143], SpriteDst=[0..143]
* Copy the content of SpriteOrg to SpriteDst.
Sprites number Definition
0 to 15 Real sprites
16 to 79 Ram Fast sprites
80 to 143 Ram Slow sprites
* Example : SPRCOPY,1,81 copy the content of sprite 1 (asic) to sprite 81 (ram slow)
----
'''SPRTURNX,SpriteNumber'''
* SpriteNumber=[0..15]
* Flip the sprite specified on horizontal axis
* Example : SPRTURNX,1
----
'''SPRTURNY,SpriteNumber'''
* SpriteNumber=[0..15]
* Flip the sprite specified on vertical axis
* Example : SPRTURNY,1
----
'''SPRFILL,SpriteNumber,SpritePen'''
* SpriteNumber=[0..15] SpritePen=[0..15]
* Fill the specified sprite with the specified pen
* Note : SpritePen=0 means the transparent pen for sprite
* Example : SPRFILL,1,12 fill the sprite 1 with pen 12
----
'''SPRCATCH,SpriteNumber,XPos,YPos'''
* SpriteNumber=[0..15] XPos=[0..143] YPos=[0..183]
* Get a sprite from mode 0 screen at specified coordinates (coordinates top/left).
* Note : This instruction runs only in graphic mode 0
* Example : CATCH,3,120,100 catch the pixels from 120,100 to 135,115 in sprite 3
----
'''SPRWHERE,SpriteNumber,@varx%,@vary%'''
* SpriteNumber=[0..15] varx=Name of x variable vary=Name of y variable
* Get the x,y coordinates of the specified sprite
* Important note : varx and vary must be defined first like integer (declaration in basic with '%') and
* they must be given to the instruction "by address" ('@' before the variable name). The * declaration must
* be respected to avoid unpredictibles results.
* Example : 10 VARX%=0: VARY%=0 : SPRWHERE,1,@VARX%,@VARY%: PRINT VARX%,VARY%
----
'''SPRSAVE,[SpriteNumber,] BlocNumber, Filename'''
* SpriteNumber=[0..15] BlocNumber=[0..4] Filename=Name of file in Amsdos standard
* Save a sprite or a set of 32 sprites (defined as one Block) to disk
* B-Asic can store 128 sprites definitions more than the usal sprites contained in asic ram.
* These 128 sprites are organised as 4 sets of 32 sprites named "Block". Each block contains 16 fast sprites and 16 slow sprites
Block & sprites number Fast Sprites Slow Sprites
1 - 0 to 15 16 to 31 80 to 95
2 - 0 to 15 32 to 47 96 to 111
3 - 0 to 15 48 to 63 112 to 127
4 - 0 to 15 64 to 79 128 to 143
* Bloc 0 is used for the 16 "real" asic sprites.
* If SpriteNumber is not precised in the instruction, so a complete block is saved
* If SpriteNumber is precised, only two sprites (fast and the slow sprite associated) for the block is saved
* Example : SPRSAVE,3,2,"SPR3BLK1.BIN" save the sprite fast and slow number 3 of the Bloc 2 (e.g. sprite 35 and sprite 99) in the file named "SPR3BLK1.BIN"
* Example : SPRSAVE,0,"SPRASIC.BIN" save the content of block 0 (e.g. 16 asic sprites)
----
'''SPRLOAD,[SpriteNumber,] BlocNumber, Filename'''
* SpriteNumber=[0..15] BlocNumber=[0..4] Filename=Name of file in Amsdos standard
* Load a sprite or a set of 32 sprites (defined as one Block) from disk
* B-Asic can store 128 sprites definitions more than the usal sprite contained in asic ram.
* These 128 sprites are organised as 4 sets of 32 sprites named "Block".
Block & sprites number Fast Sprites Slow Sprites
1 - 0 to 15 16 to 31 80 to 95
2 - 0 to 15 32 to 47 96 to 111
3 - 0 to 15 48 to 63 112 to 127
4 - 0 to 15 64 to 79 128 to 143
* Bloc 0 is used for the 16 "real" asic sprites.
* If SpriteNumber is not precised in the instruction, so a complete block is loaded
* If SpriteNumber is precised, only the specified sprite of the block is loaded
* Note : If the file specified has an invalid size, an error is displayed
* Example : SPRLOAD,3,2,"SPR3BLK1.BIN" load the fast and slow sprites 3 of the Bloc 2 (e.g. sprites 35 and 99) from the file "SPR3BLK1.BIN"
* Example : SPRLOAD,3,"RAAHHHHH.SPR" load the block 3 (e.g. sprites 48 to 63 and sprites 112 to 127) from file "RAAHHHHH.SPR"
----
'''SPRLINK,SpriteNumber1,SpriteNumber2,Xrel,Yrel'''
* SpriteNumberx=[0..15] XRel=[-256..767] YRel=[-256..255]
* Link a sprite (2) to another sprite (1) with a relative position.
* That means if sprite (1) is moved, then sprite (2) is moved too.
* So if sprite 1 is moved in X1,Y1 then the sprite 2 will be moved automatically in X1+Xrel,Y1+Yrel
* It's possible to link all the sprites in all combinations to create one or more "super sprites"
* Note : A sprite cannot be linked to itself.
* Example : SPRLINK,1,2,16,0 link sprite 2 to sprite 1 with a relative x position of 16 pixels
* Example : SPRLINK,2,5,0,16 link sprite 5 to sprite 2 with a relative y position of 16 pixels
* [ so move the sprite 1 signify to move sprite 2 and 5 ]
----
'''SPRUNLINK,SpriteNumber1,SpriteNumber2'''
* SpriteNumberx=[0..15]
* Unlink a sprite from anoter sprite.
* Example : SPRUNLINK,2,5 erase the link between sprite 2 and 5
----
'''ERALINK'''
* Erase all link
----
'''SPRCOLL,NumDef,SpriteNum1,DeltaX1,DeltaY1,SpriteNum2,DeltaX2,DeltaY2,@collision%, PixelPerfect'''
'''SPRCOLL, NoDef, 255'''
'''SPRCOLL'''
* Process the collision test between two sprites automatically or manually
* NumDef = [0..7] (8 collisions can be processed simultaneously) SpriteNum1=[0..15]
* DeltaXn=[0..255], DeltaYn=[0..255] : Number of pixels in mode 2 definition from sprite coordinate defining the zone to test collision. This method is useful to extend the collision to a super sprite or to restrict collision to only a part of a sprite or supersprite.
* PixelPerfect is not used actually
* @collision% : This variable take the value 1 when a collision is detected between 2 sprites. The user must set the value to 0 to reset the collision detection.

'''VERY IMPORTANT''' : The variable collision must be defined like an integer (déclaration by initialisation with %), and the variable must be given to function by address (e.g. @ ou à (on french keyboard) before the variable name).
Example : collision%=0 used in function like @collision%
When SPRCOLL is used with all parameters, the collision process is automatic, and so independant of locomotive basic program. But it's possible to control manually each collision test using the instruction without parameters (at this time, the automatic mode is disactivated). If the user wants to cancel a collision process, he must use the instruction with 2 parameters : SPRCOLL,NumDef,255 (This will help the cpu ;-))

'''WARNING about SPRCOLL:'''
SPRCOLL use a locomotive basic variable given by address. And this address is stored by B-Asic when SPRCOLL is called with all parameters. So the user needs ABSOLUTLY keep in mind the two following situation :
* When SPRCOLL is used in automatic mode (e.g B-Asic store automatically the collision test result at each frame), you must absolutly replace the instruction in manual mode (by using SPRCOLL without parameter) before to modify your basic program because the variable is stored and moved in the basic area.
* When you have just stopped your basic program, NEVER modify the program and do a GOTO through a SPRCOLL instruction used without parameters. (the SPRCOLL must be called before with all parameters to give to B-Asic the new address of the variable)
'''You must respect ABSOLUTLY these 2 rules to avoid a destruction of some part of your basic program. (I will solve the problem of first case later.''' I need to know when the locomotive basic interpreter is not running. Help appreciate)
----
'''DEFORGXY,SpriteNumber,XPos,YPos'''
* SpriteNumber=[0..15] XPos=[-256..767] YPos=[-256..255]
* Define absolute origin position of the specified sprite
* That means that real sprite position take care of this defined coordinates.
* Example : DEFORGXY,1,10,20:SPRXY,1,5,3 display sprite at 15,23
* Note : It's possible to define an origin position for a sprite following a path (see SPRTDEF)
* The default of origin at B-Asic reset is 0,0
----
'''DEFORGSPR,SpriteSlave,SpriteMaster'''
* SpriteSlave=[0..15] SpriteMaster=[0..15]
* Define the origin position of SpriteSlave with the position of SpriteMaster.
* Note : It's possible to define a sprite relative position for a sprite following a path (see SPRTDEF)
* It's possible to generate complex definitions of sprites movments.
* If a sprite 1 use a path 1 and a sprite 2 use a path 2, if the sprite 2 is the slave of sprite 1, then
* the path 2 will be relative to path 1.
* To erase the slavery of a sprite, use DEFORGXY instruction
----
'''DEFKBDSPR, NumDef, SpriteNumber, KeyUp, StepUp, KeyDown, StepDown, KeyLeft, StepLeft, KeyRight, StepRight'''
'''DEFKBDSPR,NumDef,255'''
'''DEFKBDSPR'''
* Associate the sprite coordinates to keyboard keys
* NumDef =[0..1] It's possible to define keys for 2 sprites / SpriteNumber=[0..15] Sprite number / Keyxxxxx=[Key number] (see table), Stepxxxx=value 0..255 : Step in mode 2 pixel to add or substract associated value to corresponding key.
* A key 0 indicate to do not test the key. When DEFKBDSPR is defined with all parameters, the sprite process is automatic, and so independent from basic program. It is possible to control manually the sprite movment by using the instruction without parameters (the automatic mode is disactivated).
* Note : If the user wants to cancel a definition, it's better to disactivate the sprite with DEFKBDSPR,NumDef,255 instead of defining all keys with 0 (The B-Asic will gain cpu-speed).
---
=== Others Instructions Set ===
----
'''POKEASIC,Address,val1,...,valx'''
* Address=[&4000..&7FFF] Valx=[&00..&FF]
* Poke one or more bytes in Asic I/O page
* Instruction reserved to experimented users.
----
'''POKEVR,Address,val1,...,valn'''
* Address=[&4000..&7FFF] Valx=[&00..&FF]
* Poke one or more bytes in second video page
* Instruction reserved to experimented users.
----
'''DOKE,Address,value16bits'''
* Address=[&4000..&7FFF] value16bits=[&0000..&FFFF]
* Double Poke in user memory
----
'''SCREENCOPY,direction '''
* direction=[0..1]
* 0 : Copy the main videoram to videoram 2
* 1 : Copy the videoram2 to main videoram

== Error Messages ==
'''Bad arguments number'''
* Bad number of arguments used in the instruction

'''Invalid Argument'''
* An invalid value is used in one or more arguments of the instruction

'''Invalid Filename'''
* A bad filename was used in a SPRSAVE or SPRLOAD instruction

'''Disc Error'''
* An I/O error has occured in a SPRSAVE or SPRLOAD instruction.
* Disc is missing, or the disk has a wrong or damaged format.

'''Not a Sprite file'''
* The size of the file specified in SPRLOAD is not correct.
* See if you do no use the SPRLOAD with a block instead of a single sprite (or the opposite)

'''Same Sprites Numbers'''
* An instruction SPRLINK or SPRUNLINK is attempted with 2 identical sprite numbers.

'''Bad Graphic Mode'''
* Instruction CATCH is not used in MODE 0

'''Invalid Moving List'''
* An invalid table is created for SPRTDEF
* (e.g. the first coordinate is the path end)

'''Link Table Full'''
* The link table is full.
* Normally this error cannot occur in a well built program.

'''Sprites not Linked'''
* Instruction SPRUNLINK is used with sprites not linked.

== Links ==
[http://logon.system.free.fr/html/lienscpc.htm Download B-Asic]

[[Category:Programming software]]
[[Category:CPC Plus]]

Talk:Programming:Hardware scrolling the screen horizontally byte-by-byte using the CRTC

2007-03-13T11:35:51Z

Longshot:

Hi. This method to reduce scroll speed is not really "smooth" because register 3 does not give a step with exactly one byte length. The only way to reduce scroll speed and keep a smooth effect is to use two videos data areas (offset switching). The inconvenient of switching is to need more memory (2x). By the way, it's the right way and the only method known on cpc old to code a slower hardware scroll (1/2 byte : 2 pixel mode 1, 1/4 byte : 1 pixel mode 1)
Great article on Interrupt Im0 on Cpc+...
--[[User:Longshot|Longshot]] 12:35, 13 March 2007 (CET)

Talk:Programming:Hardware scrolling the screen horizontally byte-by-byte using the CRTC

2007-03-13T11:34:50Z

Longshot: