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Amstrad Whole Memory Guide - General system arrangement

2017-11-14T23:01:10Z

Exofu: Fix

Chapter 1 in the book [[Amstrad Whole Memory Guide]].

== GENERAL SYSTEM ARRANGEMENT ==

Superficially, the CPC464 is a typical Z8Ø—based system, with an unusually economical arrangement of peripheral devices. By making full use of the capabilities of these devices, a performance level has been obtained which is higher than the limited chip count might suggest. One consequence of this is that the operating system is especially complex, a fact which is offset by the comparative ease of user access to the various functions. The word ‘comparative‘ 15 necessary, because knowledge of machine code is needed, which may be a difficulty for some users, but once they have come to terms with machine code a wide range of possibilities opens up.

Among other ingenuities, the way in which a minimum of 96K of memory has been packed into a 64K memory map is especially noteworthy, and this aspect of the system will be studied first.

=== The Memory Map ===

The whole of the 64K byte memory is occupied by RAM, to which any writes to memory will be directed. This makes sense, since there is r point in trying to write to ROM. Reads from addresses in the middle half of memory will also access RAM, there being no ROM in this area. For addresses in the top and bottom quarters of memory, however, both ROM and RAN are present, and it is possible to read from either at will. A BASIC peek will always access RAM, so a special bit of machine code is needed to obtain the contents of ROM.

The memory arrangement is complicated by the fact that the top quarter of RAM is dedicated to use as screen memory, and most be immediately accessible at regular intervals while data Is being passed to the display. For this purpose, two bytes are read every microsecond.

The processor is put into a wait state while the pairs of bytes are being transferred, the transfer being made directly from memory to the Video Gate Array, using an address generated by the CRT Controller chip. This means that the main processor can only make one memory access per microsecond, and although its clock runs at 4 MHz the actual processing speed is slightly reduced, a point to watch when calculating execution times.

The Video Gate Array handles the switching between ROM and RAM for this purpose, so it is natural that it is also used to control ROM selection in general. The instructions for switching between ROM and RAM are given by outputs to bits 2 and 3 of port 7FXX. A 1 disables, a 0 enables, while bit 2 applies to the lower ROM and bit 3 to the upper ROM. Incidentally, there is only one ROM component, some address fiddling dividing it into two 16K blocks as far as the System is concerned.

As in any bank-switching memory system, the key problem is the need to jump and switch banks simultaneously, or to appear to do so. The CPC464 achieves this by using routines held in central RAM. These are always accessible, whatever the ROM selection state. In addition to simple switching between ROM and RAM, these routines allow the selection of alternative upper ROMs, extending the available memory still further. In the extreme, it would nominally be possible to address a total of 4128K bytes of memory, but few systems are likely to approach that ultimate limit.

The complexities of the memory System can be evaded by putting machine code into the central half of the memory map, which contains only RAM, but this is neither essential nor always feasible.

=== The I/O Map ===

The selection of peripheral channels is largely determined by making one of the bits of the upper byte of the 16—bit I/O address low, which means that the older I/O instructions of the form IN A,(N) and OUT (N),A cannot be used, because they draw the upper byte from the contents of the A register. Instructions which set the I/O address from the contents of the BC register are mandatory, and there are strict limits regarding the contents of the B register, because no more than one of the six upper bits may be low in any given address. (Making more than one of these bits low in an input instruction invites physical damage, because two data sources may fight for control of the bus, while it is rarely sensible to send the same output to two different ports at the same time.)

The I/O addresses can be summed up as follows:

* If address bit A15 is low, the Video Gate Array is selected. This port is for output only. The address must be 7FXX.

* If address bit A14 is low, the CRT Controller is selected. Address bits A8 and A9 are used to select four different transfer modes:

{| class="wikitable"
|-
| BCXX || Output to Register Select
|-
| BDXX || Data Output
|-
| BEXX || Status Input
|-
| BFXX || Data Input
|}

* If address bit A13 is low, ROM select data is being output. The address must be DFXX.

* If address bit A12 is low, the printer channel is selected for output only. The address must be EFXX.

* If address bit A11 is low, the Parallel Peripheral Interface (PPI) is selected. Here again, bits A8 and A9 are used to select four sub—channels:

{| class="wikitable"
|-
| F4XX || Port A (I/O)
|-
| F5XX || Port B (I/O)
|-
| F6XX || Port C (I/O)
|-
| F7XX || Control (Output only)
|}

* If address bit A10 is low, an expansion channel is selected. In this case, bits A5 — A7 have special significance:
** A5 low selects a communication channel.
** A6 low selects a reserved function.
** A7 low selects the disc System.

* Address F8FF is a general reset for expansion channels.

The above allocations restrict the user to the following address ranges for any special I/O functions he may require:

F8E0—F8FE: F9E0—F9FF: FAE0—FAFF: FBE0—FBFF

=== Outer Peripherals ===

The devices mentioned above are the ‘inner peripherals‘, which are accessed directly from the main processor. Further devices, classed as the ‘Outer Peripherals‘, are accessed by the inner peripherals. They include the Programmable Sound Generator, accesed by the PPI; the keyboard, accessed by the PPI and the

Sound Generator; the Cassette Recorder, accessed by the PPI; the Loudspeaker, driven by the Sound Generator.

For further details of the hardware system, consult ‘[[The Ins & Outs of the Amstrad|The Ins and Outs of the Amstrad]]‘, which gives additional Information on the coding and action of these devices.

=== System States ===

At switch-on, a number of initialisation procedures are executed, and control then passes to upper ROM Ø. If there is no external ROM of this number, the internal BASIC interpreter takes charge as the ‘foreground‘ program.

Once a foreground program has been entered, it remains in charge until a return at entry level is executed, when a full reset is performed, and ROM is again put in charge. However, the foreground program can call on background programs for assistance, and these, in turn, can call other programs. There is thus — nominally — one foreground level, but there can be several background levels.

A ROM other than 0, or a program in RAM, can be selected as the foreground program. This can be done by a RUN”” command which reads a machine code program that has a defined Start address, or by a machine code routine. It may be more convenient to leave the BASIC interpreter nominally in charge and run a program CALLed from BASIC as if it was a foreground program. This has the advantage that a full reset is not inevitable in response to a return at entry level. Instead, the interpreter is re—entered.

Using BASIC in this way has other advantages. [[HIMEM]] can be checked and adjusted quite easy putting it below the area in which machine code is to reside, and other system variables can be set up. The BASIC program will use some RAM, particularly from Ø17 upwards, but this is likely to be a negligible drain on the large RAM area available.

One point to watch is that if extension systems are added, such as disc drive, speech facility, or the [[Maxam|MAXAM]] assembler in ROM form, HIMEM is lowered, because the extensions have claimed workspace for their own use. Some commercial programs are incompatible with a disc drive ‚ because they trespass on the disc workspace. Protected or not, they cannot be transferred to disc.

As a guide, HIMEM is AB7F in typical circumstances, but drops to A67B with disc drives connected, and may go even lower with [[AMSDOS]] active.

== Scanned pages ==

<gallery>
Image:AWMG page1.jpg|page 1
Image:AWMG page2.jpg|page 2
Image:AWMG page3.jpg|page 3
Image:AWMG page4.jpg|page 4
Image:AWMG page5.jpg|page 5
Image:AWMG page6.jpg|page 6
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - General system arrangement

2017-11-14T22:58:53Z

Exofu: Formatting

Chapter 1 in the book [[Amstrad Whole Memory Guide]].

== GENERAL SYSTEM ARRANGEMENT ==

Superficially, the CPC464 is a typical Z8Ø—based system, with an unusually economical arrangement of peripheral devices. By making full use of the capabilities of these devices, a performance level has been obtained which is higher than the limited chip count might suggest. One consequence of this is that the operating system is especially complex, a fact which is offset by the comparative ease of user access to the various functions. The word ‘comparative‘ 15 necessary, because knowledge of machine code is needed, which may be a difficulty for some users, but once they have come to terms with machine code a wide range of possibilities opens up.

Among other ingenuities, the way in which a minimum of 96K of memory has been packed into a 64K memory map is especially noteworthy, and this aspect of the system will be studied first.

=== The Memory Map ===

The whole of the 64K byte memory is occupied by RAM, to which any writes to memory will be directed. This makes sense, since there is r point in trying to write to ROM. Reads from addresses in the middle half of memory will also access RAM, there being no ROM in this area. For addresses in the top and bottom quarters of memory, however, both ROM and RAN are present, and it is possible to read from either at will. A BASIC peek will always access RAM, so a special bit of machine code is needed to obtain the contents of ROM.

The memory arrangement is complicated by the fact that the top quarter of RAM is dedicated to use as screen memory, and most be immediately accessible at regular intervals while data Is being passed to the display. For this purpose, two bytes are read every microsecond.

The processor is put into a wait state while the pairs of bytes are being transferred, the transfer being made directly from memory to the Video Gate Array, using an address generated by the CRT Controller chip. This means that the main processor can only make one memory access per microsecond, and although its clock runs at 4 MHz the actual processing speed is slightly reduced, a point to watch when calculating execution times.

The Video Gate Array handles the switching between ROM and RAM for this purpose, so it is natural that it is also used to control ROM selection in general. The instructions for switching between ROM and RAM are given by outputs to bits 2 and 3 of port 7FXX. A 1 disables, a 0 enables, while bit 2 applies to the lower ROM and bit 3 to the upper ROM. Incidentally, there is only one ROM component, some address fiddling dividing it into two 16K blocks as far as the System is concerned.

As in any bank-switching memory system, the key problem is the need to jump and switch banks simultaneously, or to appear to do so. The CPC464 achieves this by using routines held in central RAM. These are always accessible, whatever the ROM selection state. In addition to simple switching between ROM and RAM, these routines allow the selection of alternative upper ROMs, extending the available memory still further. In the extreme, it would nominally be possible to address a total of 4128K bytes of memory, but few systems are likely to approach that ultimate limit.

The complexities of the memory System can be evaded by putting machine code into the central half of the memory map, which contains only RAM, but this is neither essential nor always feasible.

=== The I/O Map ===

The selection of peripheral channels is largely determined by making one of the bits of the upper byte of the 16—bit I/O address low, which means that the older I/O instructions of the form IN A,(N) and OUT (N),A cannot be used, because they draw the upper byte from the contents of the A register. Instructions which set the I/O address from the contents of the BC register are mandatory, and there are strict limits regarding the contents of the B register, because no more than one of the six upper bits may be low in any given address. (Making more than one of these bits low in an input instruction invites physical damage, because two data sources may fight for control of the bus, while it is rarely sensible to send the same output to two different ports at the same time.)

The I/O addresses can be summed up as follows:

* If address bit A15 is low, the Video Gate Array is selected. This port is for output only. The address must be 7FXX.

* If address bit A14 is low, the CRT Controller is selected. Address bits A8 and A9 are used to select four different transfer modes:

{| class="wikitable"
|-
| BCXX || Output to Register Select
|-
| BDXX || Data Output
|-
| BEXX || Status Input
|-
| BFXX || Data Input
|}

* If address bit A13 is low, ROM select data is being output. The address must be DFXX.

* If address bit A12 is low, the printer channel is selected for output only. The address must be EFXX.

* If address bit A11 is low, the Parallel Peripheral Interface (PPI) is selected. Here again, bits A8 and A9 are used to select four sub—channels:

{| class="wikitable"
|-
| F4XX || Port A (I/O)
|-
| F5XX || Port B (I/O)
|-
| F6XX || Port C (I/O)
|-
| F7XX || Control (Output only) |
|}

* If address bit A10 is low, an expansion channel is selected. In this case, bits A5 — A7 have special significance:
** A5 low selects a communication channel.
** A6 low selects a reserved function.
** A7 low selects the disc System.

* Address F8FF is a general reset for expansion channels.

The above allocations restrict the user to the following address ranges for any special I/O functions he may require:

F8E0—F8FE: F9E0—F9FF: FAE0—FAFF: FBE0—FBFF

=== Outer Peripherals ===

The devices mentioned above are the ‘inner peripherals‘, which are accessed directly from the main processor. Further devices, classed as the ‘Outer Peripherals‘, are accessed by the inner peripherals. They include the Programmable Sound Generator, accesed by the PPI; the keyboard, accessed by the PPI and the

Sound Generator; the Cassette Recorder, accessed by the PPI; the Loudspeaker, driven by the Sound Generator.

For further details of the hardware system, consult ‘[[The Ins & Outs of the Amstrad|The Ins and Outs of the Amstrad]]‘, which gives additional Information on the coding and action of these devices.

=== System States ===

At switch-on, a number of initialisation procedures are executed, and control then passes to upper ROM Ø. If there is no external ROM of this number, the internal BASIC interpreter takes charge as the ‘foreground‘ program.

Once a foreground program has been entered, it remains in charge until a return at entry level is executed, when a full reset is performed, and ROM is again put in charge. However, the foreground program can call on background programs for assistance, and these, in turn, can call other programs. There is thus — nominally — one foreground level, but there can be several background levels.

A ROM other than 0, or a program in RAM, can be selected as the foreground program. This can be done by a RUN”” command which reads a machine code program that has a defined Start address, or by a machine code routine. It may be more convenient to leave the BASIC interpreter nominally in charge and run a program CALLed from BASIC as if it was a foreground program. This has the advantage that a full reset is not inevitable in response to a return at entry level. Instead, the interpreter is re—entered.

Using BASIC in this way has other advantages. [[HIMEM]] can be checked and adjusted quite easy putting it below the area in which machine code is to reside, and other system variables can be set up. The BASIC program will use some RAM, particularly from Ø17 upwards, but this is likely to be a negligible drain on the large RAM area available.

One point to watch is that if extension systems are added, such as disc drive, speech facility, or the [[Maxam|MAXAM]] assembler in ROM form, HIMEM is lowered, because the extensions have claimed workspace for their own use. Some commercial programs are incompatible with a disc drive ‚ because they trespass on the disc workspace. Protected or not, they cannot be transferred to disc.

As a guide, HIMEM is AB7F in typical circumstances, but drops to A67B with disc drives connected, and may go even lower with [[AMSDOS]] active.

== Scanned pages ==

<gallery>
Image:AWMG page1.jpg|page 1
Image:AWMG page2.jpg|page 2
Image:AWMG page3.jpg|page 3
Image:AWMG page4.jpg|page 4
Image:AWMG page5.jpg|page 5
Image:AWMG page6.jpg|page 6
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - General system arrangement

2017-11-14T22:45:44Z

Exofu: /* The I/O Map */

Chapter 1 in the book [[Amstrad Whole Memory Guide]].

== GENERAL SYSTEM ARRANGEMENT ==

Superficially, the CPC464 is a typical Z8Ø—based system, with an unusually economical arrangement of peripheral devices. By making full use of the capabilities of these devices, a performance level has been obtained which is higher than the limited chip count might suggest. One consequence of this is that the operating system is especially complex, a fact which is offset by the comparative ease of user access to the various functions. The word ‘comparative‘ 15 necessary, because knowledge of machine code is needed, which may be a difficulty for some users, but once they have come to terms with machine code a wide range of possibilities opens up.

Among other ingenuities, the way in which a minimum of 96K of memory has been packed into a 64K memory map is especially noteworthy, and this aspect of the system will be studied first.

=== The Memory Map ===

The whole of the 64K byte memory is occupied by RAM, to which any writes to memory will be directed. This makes sense, since there is r point in trying to write to ROM. Reads from addresses in the middle half of memory will also access RAM, there being no ROM in this area. For addresses in the top and bottom quarters of memory, however, both ROM and RAN are present, and it is possible to read from either at will. A BASIC peek will always access RAM, so a special bit of machine code is needed to obtain the contents of ROM.

The memory arrangement is complicated by the fact that the top quarter of RAM is dedicated to use as screen memory, and most be immediately accessible at regular intervals while data Is being passed to the display. For this purpose, two bytes are read every microsecond.

The processor is put into a wait state while the pairs of bytes are being transferred, the transfer being made directly from memory to the Video Gate Array, using an address generated by the CRT Controller chip. This means that the main processor can only make one memory access per microsecond, and although its clock runs at 4 MHz the actual processing speed is slightly reduced, a point to watch when calculating execution times.

The Video Gate Array handles the switching between ROM and RAM for this purpose, so it is natural that it is also used to control ROM selection in general. The instructions for switching between ROM and RAM are given by outputs to bits 2 and 3 of port 7FXX. A 1 disables, a 0 enables, while bit 2 applies to the lower ROM and bit 3 to the upper ROM. Incidentally, there is only one ROM component, some address fiddling dividing it into two 16K blocks as far as the System is concerned.

As in any bank-switching memory system, the key problem is the need to jump and switch banks simultaneously, or to appear to do so. The CPC464 achieves this by using routines held in central RAM. These are always accessible, whatever the ROM selection state. In addition to simple switching between ROM and RAM, these routines allow the selection of alternative upper ROMs, extending the available memory still further. In the extreme, it would nominally be possible to address a total of 4128K bytes of memory, but few systems are likely to approach that ultimate limit.

The complexities of the memory System can be evaded by putting machine code into the central half of the memory map, which contains only RAM, but this is neither essential nor always feasible.

=== The I/O Map ===

The selection of peripheral channels is largely determined by making one of the bits of the upper byte of the 16—bit I/O address low, which means that the older I/O instructions of the form IN A,(N) and OUT (N),A cannot be used, because they draw the upper byte from the contents of the A register. Instructions which set the I/O address from the contents of the BC register are mandatory, and there are strict limits regarding the contents of the B register, because no more than one of the six upper bits may be low in any given address. (Making more than one of these bits low in an input instruction invites physical damage, because two data sources may fight for control of the bus, while it is rarely sensible to send the same output to two different ports at the same time.)

The I/O addresses can be summed up as follows:

* If address bit A15 is low, the Video Gate Array is selected. This port is for output only. The address must be 7FXX.

* If address bit A14 is low, the CRT Controller is selected. Address bits A8 and A9 are used to select four different transfer modes:

BCXX Output to Register Select
BDXX Data Output
BEXX Status Input
BFXX Data Input

* If address bit A13 is low, ROM select data is being output. The address must be DFXX.

* If address bit A12 is low, the printer channel is selected for output only. The address must be EFXX.

* If address bit A11 is low, the Parallel Peripheral Interface (PPI) is selected. Here again, bits A8 and A9 are used to select four sub—channels:

F4XX Port A (I/O)
F5XX Port B (I/O)
F6XX Fort C (I/O)
F7XX Control (Output only)

* If address bit A10 is low, an expansion channel is selected. In this case, bits A5 — A7 have special significance:

A5 low selects a communication channel.
A6 low selects a reserved function.
A7 low selects the disc System.

* Address F8FF is a general reset for expansion channels.

The above allocations restrict the user to the following address ranges for any special I/O functions he may require:

F8E0—F8FE: F9E0—F9FF: FAE0—FAFF: FBE0—FBFF

=== Outer Peripherals ===

The devices mentioned above are the ‘inner peripherals‘, which are accessed directly from the main processor. Further devices, classed as the ‘Outer Peripherals‘, are accessed by the inner peripherals. They include the Programmable Sound Generator, accesed by the PPI; the keyboard, accessed by the PPI and the

Sound Generator; the Cassette Recorder, accessed by the PPI; the Loudspeaker, driven by the Sound Generator.

For further details of the hardware system, consult ‘[[The Ins & Outs of the Amstrad|The Ins and Outs of the Amstrad]]‘, which gives additional Information on the coding and action of these devices.

=== System States ===

At switch-on, a number of initialisation procedures are executed, and control then passes to upper ROM Ø. If there is no external ROM of this number, the internal BASIC interpreter takes charge as the ‘foreground‘ program.

Once a foreground program has been entered, it remains in charge until a return at entry level is executed, when a full reset is performed, and ROM is again put in charge. However, the foreground program can call on background programs for assistance, and these, in turn, can call other programs. There is thus — nominally — one foreground level, but there can be several background levels.

A ROM other than 0, or a program in RAM, can be selected as the foreground program. This can be done by a RUN”” command which reads a machine code program that has a defined Start address, or by a machine code routine. It may be more convenient to leave the BASIC interpreter nominally in charge and run a program CALLed from BASIC as if it was a foreground program. This has the advantage that a full reset is not inevitable in response to a return at entry level. Instead, the interpreter is re—entered.

Using BASIC in this way has other advantages. [[HIMEM]] can be checked and adjusted quite easy putting it below the area in which machine code is to reside, and other system variables can be set up. The BASIC program will use some RAM, particularly from Ø17 upwards, but this is likely to be a negligible drain on the large RAM area available.

One point to watch is that if extension systems are added, such as disc drive, speech facility, or the [[Maxam|MAXAM]] assembler in ROM form, HIMEM is lowered, because the extensions have claimed workspace for their own use. Some commercial programs are incompatible with a disc drive ‚ because they trespass on the disc workspace. Protected or not, they cannot be transferred to disc.

As a guide, HIMEM is AB7F in typical circumstances, but drops to A67B with disc drives connected, and may go even lower with [[AMSDOS]] active.

== Scanned pages ==

<gallery>
Image:AWMG page1.jpg|page 1
Image:AWMG page2.jpg|page 2
Image:AWMG page3.jpg|page 3
Image:AWMG page4.jpg|page 4
Image:AWMG page5.jpg|page 5
Image:AWMG page6.jpg|page 6
</gallery>

[[Category:CPC Firmware]]

PSG

2017-11-13T20:33:14Z

Exofu: /* 0Eh - External Dataregister Port A */

The Programmable Sound Generator (PSG) is able to output three separate sound channels (named Channel A, B and C). Each channel can be used to output tones and/or white noise.

== PSG Registers ==

The PSG has 16 read/writeable data registers, and a write-only index register. Both the index and data registers are accessed through PIO Port A, depending on the current setting of the BC1 and BDIR bits in [[8255|PPI]] Port C. The four possible combinations are:
0=inactive 2=write data
1=read data 3=write index
The procedure to write data to a specific register is as follows: Write the register number to [[8255|PPI]] Port A, set BC1/BDIR to Write Index - and back to Inactive. Now write the data to PIO Port A, set BC1/BDIR to Write Data - and back to Inactive.

* [[How to access the PSG via PPI]]

===00h - Channel A Tone Frequency Low (8bit)===
===01h - Channel A Tone Frequency High (4bit)===
===02h - Channel B Tone Frequency Low (8bit)===
===03h - Channel B Tone Frequency High (4bit)===
===04h - Channel C Tone Frequency Low (8bit)===
===05h - Channel C Tone Frequency High (4bit)===
The tone (square wave) frequency in Hertz is calculated as follows:
F = 4MHz / 64 / nn ;with nn in range 1..4095 (nn=0 acts as nn=1)
Possible frequencies are in range from 62500Hz (nn=1) down to approx. 15.26Hz (nn=4095).

===06h - Noise Frequency (5bit)===
The noise frequency in Hertz is calculated as follows:

F = 4MHz / 64 / nn ;with nn in range 1..31 (nn=0 acts as nn=1)

Noise can be output on all 3 channels, but there is only one noise generator (so all channels share the same noise frequency). The noise generator consists of 17bit shift register, and a 1bit noise level (0=LOW or 1=HIGH). These are updated at the selected frequency as follows:

noise_level = noise_level XOR shiftreg.bit0
newbit = shiftreg.bit0 XOR shiftreg.bit3
shiftreg = (shiftreg SHR 1) + (newbit SHL 16)

Note that level isn't set equal to bit0, instead, it toggles when bit0=1.

===07h - Mixer Control Register===
The control register enables or disables the sound channels. Each channel can output a Tone and/or Noise.

Bit 0 Channel A Tone (1=off, 0=on)
Bit 1 Channel B Tone (1=off, 0=on)
Bit 2 Channel C Tone (1=off, 0=on)
Bit 3 Channel A Noise (1=off, 0=on)
Bit 4 Channel B Noise (1=off, 0=on)
Bit 5 Channel C Noise (1=off, 0=on)
Bit 6 Port A Direction (1=output, 0=input) (should be always 0 for CPC)
Bit 7 Port B Direction (1=output, 0=input) (not used in CPC)

If both Tone and Noise are disabled on a channel, then a constant HIGH level is output (useful for digitized speech). If both Tone and Noise are enabled on the same channel, then the signals are ANDed (the signals aren't ADDed) (ie. HIGH is output only if both are HIGH).

===08h - Channel A Volume (0-0Fh=volume, 10h=use envelope instead)===
===09h - Channel B Volume (0-0Fh=volume, 10h=use envelope instead)===
===0Ah - Channel C Volume (0-0Fh=volume, 10h=use envelope instead)===
Defines the volume, 0=off, 15=max. If bit4=1, then the volume is taken from the envelope generator. The volume is non-linear. Below formula does comply with the PSG datasheet, and does more or less match the voltages measured on the CPCs speaker (the voltages on the CPCs stereo connector seem to be slightly different though).
amplitude = max / sqrt(2)^(15-nn)
eg. 15 --> max/1, 14 --> max/1.414, 13 --> max/2, etc.
The volume affects only HIGH levels. LOW levels are always NULL. Ie. sound output toggles between +VOL and NULL (not between +VOL and -VOL).

Digitized samples can be written to the volume registers (mind that volume is non-linear). When doing that, it's best to switch the channel to constant HIGH level (by disabling both Tone and Noise). Another method would be to set tone frequency to 000h or 001h (the resulting frequency is too high to be audible, so the HIGH/LOW levels sound like a constant HALF level).

=== 0Bh - Volume Envelope Frequency Low (8bit) ===
=== 0Ch - Volume Envelope Frequency High (8bit) ===
Envelope step frequency (tone or noise) calculated as follows:

F = 4MHz / 64 / nn ;with nn in range 1..65535 (nn=0 acts as nn=1)

Depending on the envelope shape, the volume is incremented from 0 to 15, or decremented from 15 to 0. In either case it takes 16 steps to complete, the completion time for 16 steps is therefore:

T = nn*1024 / 4MHz ;with nn in range 1..65535 (256us .. 16.7 seconds)

=== 0Dh - Volume Envelope Shape (4bit) ===
Writing to this register (re-)starts the envelope. Additionally, the written value specifies the envelope shape, the four bits have the following meaning:

Bit 0 Hold (1=stop envelope past first cycle)
Bit 1 Alternate (1=reverse direction at end of each cycle)
Bit 2 Attack (1=initial direction increase)
Bit 3 Continue (0=same as if Bit0=1 and Bit1=Bit2)

The possible combinations and resulting shapes are:

Binary Hex Shape
00XX 00h-03h \_________ (same as 09h)
01XX 04h-07h /_________ (same as 0Fh)
1000 08h \\\\\\\\\\
1001 09h \_________ (volume remains quiet)
1010 0Ah \/\/\/\/\/
1011 0Bh \""""""""" (volume remains high)
1100 0Ch //////////
1101 0Dh /""""""""" (volume remains high)
1110 0Eh /\/\/\/\/\
1111 0Fh /_________ (volume remains quiet)

When using the volume envelope generator, the volume is always increased from 00h to 0Fh (or vice versa), it is not possible to specify a starting/ending point (like from 00h to 07h).

=== 0Eh - External Dataregister Port A ===
This register receives data from the CPC keyboard (or joystick), for more information read the chapter about the [[Programming:Keyboard_scanning|CPC Keyboard Matrix]]. This register can be also used as output port by setting bit 6 of the PSG control register to 1 (that would allow to use the six data pins of the joystick connector to output data to external hardware).

=== 0Fh - External Dataregister Port B ===
This register is not used in CPC computers. In detail, a AY-3-8910 sound chip would have external connectors for this register, so that it could be used as a further IO port, but the CPC's sound chip (AY-3-8912, in 28 pin package) doesn't have such connectors, even though the register still does exist internally.
The [[Aleste 520EX]] (russian CPC clone) is a special case: does have a 8910 chip, with PSG Port B being used as 8bit printer port data.

== Mono and Stereo Output ==
When using the CPC's external stereo jack, channel A is output to the right, channel C is output left, and channel B is output to both left and right, in that case channel B is output through a bigger resistor to prevent that this channel appears loader than the others.

Otherwise (when using the built-in speaker), all three channels are mixed at the same intensity. This signal appears to be also sent to the Tape output line also, so a connected Data Recorder could be used to record CPC music also.

== Datasheet ==
* [[Media:Ay3-891x.pdf|AY-3-891x datasheet]]

== Links ==

[http://en.wikipedia.org/wiki/General_Instrument_AY-3-8910 Wikipedia on the PSG]

== Video ==

Introduction to the AY-3-8912

{{#ev:youtube|eSfoQKiXo5g|200}}

Amstrad CPC6128 playing [[MYM files]]

{{#ev:youtube|PTslbiAbb5A|200}}

[[Category:Hardware]]
[[Category:Music and sound| ]]
[[Category:Video contents]][[Category:CPC Internal Components]]

PSG

2017-11-13T18:28:53Z

Exofu: Fix typo

The Programmable Sound Generator (PSG) is able to output three separate sound channels (named Channel A, B and C). Each channel can be used to output tones and/or white noise.

== PSG Registers ==

The PSG has 16 read/writeable data registers, and a write-only index register. Both the index and data registers are accessed through PIO Port A, depending on the current setting of the BC1 and BDIR bits in [[8255|PPI]] Port C. The four possible combinations are:
0=inactive 2=write data
1=read data 3=write index
The procedure to write data to a specific register is as follows: Write the register number to [[8255|PPI]] Port A, set BC1/BDIR to Write Index - and back to Inactive. Now write the data to PIO Port A, set BC1/BDIR to Write Data - and back to Inactive.

* [[How to access the PSG via PPI]]

===00h - Channel A Tone Frequency Low (8bit)===
===01h - Channel A Tone Frequency High (4bit)===
===02h - Channel B Tone Frequency Low (8bit)===
===03h - Channel B Tone Frequency High (4bit)===
===04h - Channel C Tone Frequency Low (8bit)===
===05h - Channel C Tone Frequency High (4bit)===
The tone (square wave) frequency in Hertz is calculated as follows:
F = 4MHz / 64 / nn ;with nn in range 1..4095 (nn=0 acts as nn=1)
Possible frequencies are in range from 62500Hz (nn=1) down to approx. 15.26Hz (nn=4095).

===06h - Noise Frequency (5bit)===
The noise frequency in Hertz is calculated as follows:

F = 4MHz / 64 / nn ;with nn in range 1..31 (nn=0 acts as nn=1)

Noise can be output on all 3 channels, but there is only one noise generator (so all channels share the same noise frequency). The noise generator consists of 17bit shift register, and a 1bit noise level (0=LOW or 1=HIGH). These are updated at the selected frequency as follows:

noise_level = noise_level XOR shiftreg.bit0
newbit = shiftreg.bit0 XOR shiftreg.bit3
shiftreg = (shiftreg SHR 1) + (newbit SHL 16)

Note that level isn't set equal to bit0, instead, it toggles when bit0=1.

===07h - Mixer Control Register===
The control register enables or disables the sound channels. Each channel can output a Tone and/or Noise.

Bit 0 Channel A Tone (1=off, 0=on)
Bit 1 Channel B Tone (1=off, 0=on)
Bit 2 Channel C Tone (1=off, 0=on)
Bit 3 Channel A Noise (1=off, 0=on)
Bit 4 Channel B Noise (1=off, 0=on)
Bit 5 Channel C Noise (1=off, 0=on)
Bit 6 Port A Direction (1=output, 0=input) (should be always 0 for CPC)
Bit 7 Port B Direction (1=output, 0=input) (not used in CPC)

If both Tone and Noise are disabled on a channel, then a constant HIGH level is output (useful for digitized speech). If both Tone and Noise are enabled on the same channel, then the signals are ANDed (the signals aren't ADDed) (ie. HIGH is output only if both are HIGH).

===08h - Channel A Volume (0-0Fh=volume, 10h=use envelope instead)===
===09h - Channel B Volume (0-0Fh=volume, 10h=use envelope instead)===
===0Ah - Channel C Volume (0-0Fh=volume, 10h=use envelope instead)===
Defines the volume, 0=off, 15=max. If bit4=1, then the volume is taken from the envelope generator. The volume is non-linear. Below formula does comply with the PSG datasheet, and does more or less match the voltages measured on the CPCs speaker (the voltages on the CPCs stereo connector seem to be slightly different though).
amplitude = max / sqrt(2)^(15-nn)
eg. 15 --> max/1, 14 --> max/1.414, 13 --> max/2, etc.
The volume affects only HIGH levels. LOW levels are always NULL. Ie. sound output toggles between +VOL and NULL (not between +VOL and -VOL).

Digitized samples can be written to the volume registers (mind that volume is non-linear). When doing that, it's best to switch the channel to constant HIGH level (by disabling both Tone and Noise). Another method would be to set tone frequency to 000h or 001h (the resulting frequency is too high to be audible, so the HIGH/LOW levels sound like a constant HALF level).

=== 0Bh - Volume Envelope Frequency Low (8bit) ===
=== 0Ch - Volume Envelope Frequency High (8bit) ===
Envelope step frequency (tone or noise) calculated as follows:

F = 4MHz / 64 / nn ;with nn in range 1..65535 (nn=0 acts as nn=1)

Depending on the envelope shape, the volume is incremented from 0 to 15, or decremented from 15 to 0. In either case it takes 16 steps to complete, the completion time for 16 steps is therefore:

T = nn*1024 / 4MHz ;with nn in range 1..65535 (256us .. 16.7 seconds)

=== 0Dh - Volume Envelope Shape (4bit) ===
Writing to this register (re-)starts the envelope. Additionally, the written value specifies the envelope shape, the four bits have the following meaning:

Bit 0 Hold (1=stop envelope past first cycle)
Bit 1 Alternate (1=reverse direction at end of each cycle)
Bit 2 Attack (1=initial direction increase)
Bit 3 Continue (0=same as if Bit0=1 and Bit1=Bit2)

The possible combinations and resulting shapes are:

Binary Hex Shape
00XX 00h-03h \_________ (same as 09h)
01XX 04h-07h /_________ (same as 0Fh)
1000 08h \\\\\\\\\\
1001 09h \_________ (volume remains quiet)
1010 0Ah \/\/\/\/\/
1011 0Bh \""""""""" (volume remains high)
1100 0Ch //////////
1101 0Dh /""""""""" (volume remains high)
1110 0Eh /\/\/\/\/\
1111 0Fh /_________ (volume remains quiet)

When using the volume envelope generator, the volume is always increased from 00h to 0Fh (or vice versa), it is not possible to specify a starting/ending point (like from 00h to 07h).

=== 0Eh - External Dataregister Port A ===
This register receives data from the CPC keyboard (or joystick), for more information read the chapter about the CPC Keyboard Matrix. This register can be also used as output port by setting bit 6 of the PSG control register to 1 (that would allow to use the six data pins of the joystick connector to output data to external hardware).

=== 0Fh - External Dataregister Port B ===
This register is not used in CPC computers. In detail, a AY-3-8910 sound chip would have external connectors for this register, so that it could be used as a further IO port, but the CPC's sound chip (AY-3-8912, in 28 pin package) doesn't have such connectors, even though the register still does exist internally.
The [[Aleste 520EX]] (russian CPC clone) is a special case: does have a 8910 chip, with PSG Port B being used as 8bit printer port data.

== Mono and Stereo Output ==
When using the CPC's external stereo jack, channel A is output to the right, channel C is output left, and channel B is output to both left and right, in that case channel B is output through a bigger resistor to prevent that this channel appears loader than the others.

Otherwise (when using the built-in speaker), all three channels are mixed at the same intensity. This signal appears to be also sent to the Tape output line also, so a connected Data Recorder could be used to record CPC music also.

== Datasheet ==
* [[Media:Ay3-891x.pdf|AY-3-891x datasheet]]

== Links ==

[http://en.wikipedia.org/wiki/General_Instrument_AY-3-8910 Wikipedia on the PSG]

== Video ==

Introduction to the AY-3-8912

{{#ev:youtube|eSfoQKiXo5g|200}}

Amstrad CPC6128 playing [[MYM files]]

{{#ev:youtube|PTslbiAbb5A|200}}

[[Category:Hardware]]
[[Category:Music and sound| ]]
[[Category:Video contents]][[Category:CPC Internal Components]]