CPCWiki - THE Amstrad CPC encyclopedia! - User contributions [en]

Comparing C64 to CPC

2017-03-09T06:13:11Z

Dingo: /* Comparing Amstrad Plus and C64 */

== Comparing CPC and C64 ==

* The C64 was released in 1982, the CPC released in 1984.

* The C64 was designed to be connected to a television (PAL: 50Hz, NTSC: 60Hz). The CPC was designed to be connected to an Amstrad GT65 green screen or CTM640/644 colour monitor.

* The C64 has a dedicated separate tape player. The CPC464 has a dedicated tape player built in, or for CPC664 and CPC6128 any tape player could be used with a suitable lead.

* The C64 has a palette of 16 colours. The Amstrad has a palette of 27 colours.

* The C64 has a 1.0MHz 6510 CPU (a 6502 based CPU design). The CPC has a 4.0Mhz [[Z80]] CPU.

* The C64 has a programmable raster interrupt. You can define the line at which the interrupt will be triggered and you can do this multiple times during a frame. The CPC has 6 "raster" interrupts at fixed positions through the 50Hz frame.

* The C64 has 50Hz and 60Hz variants (for regions where PAL and NTSC are used). The CPC is 50Hz only.

* The C64's color RAM, SID, VIC and other hardware can be made visible within the 6510's memory space. Access to them is done using normal memory read/write operations. All access to the CPC's hardware is done using the Z80's special I/O instructions (IN/OUT).

* The C64 has two resolutions: high and multi-colour. The pixel sizes are compareable to Amstrad's mode 1 and mode 0. The Amstrad has 3 display resolutions: low, medium and high. The high resolution on the CPC is higher than the C64's.

* The C64 has character and bitmap based modes. The CPC modes are all bitmapped.

* The C64 has pixel-by-pixel hardware scrolling in both the horizontal and vertical. The CPC has hardware scrolling. Using R5 of the CRTC and Rupture demo technique pixel-by-pixel scrolling in the vertical direction can be achieved. Using R3 of the CRTC 1 byte at a time in the horizontal is possible (which equates to 2 pixels in mode 0, 4 in mode 1, and 8 in mode 2).

* The C64 has the SID [[ASIC]] sound chip. The CPC has the [[AY-3-8912]] [[COTS]] sound chip.

* The C64 has the VIC [[ASIC]] video chip. The CPC has the [[COTS]] [[6845 CRTC]] and an [[ASIC]] Gate-Array.

* The C64 tape loading is done through interrupts so is not intensive on the CPU. The CPC tape loading is very intensive on the CPU.

* The C64 communicates with the disc drive through a wired serial connection. This means loading from disc is slow unless a special loader is used. The CPC's disc interface uses a [[COTS]] [[NEC765]] disc controller and uses byte-by-byte data transfer so is much quicker.

* The C64 can easily play music while loading from tape or disc and do other graphical effects at the same time. The CPC can play music during tape or disc loading but it's more processor intensive and is restricted to no other effects when this is done.

* The CPC can do overscan and any pixels can be shown here, the C64 can do it but it's more processor intensive and only sprites can be displayed in this area. (The C64 can open the lower and upper border with much less processor time, it takes much more time to open the side borders).

==Palette comparison==

Amstrad has a palette of 27 colours formed by mixing 0, "half" or "full" of R,G,B. The colours are vibrant.
The Amstrad's palette however is lacking in browns and greys. The colours themselves are consistent between machines.

The C64 has a palette of 16 colours. The colours were chosen by the designers. It has a couple of greys and some browns.
The colours appear different on NTSC and PAL due to the way these transmit their colour signals, and in addition the colour is not always the same between machines.

Both have a good range of colours that can produce great pictures.

==Comparison of the SID and AY-3-8912==

SID:

* 3 tone channels
* 4 waveform types (sawtooth, triangle, pulse, noise), selectable per channel
* Ring-Modulation
* Programmable filter
* Programmable hardware envelopes on any channel

AY:

* 3 tone channels (square waveforms only)
* 1 noise channel
* 1 hardware envelope (with programmable waveform)
* the volume for each channel can be set or controlled by the hardware envelope.
* The mixer can be used to enable/disable tone output for each channel, enable noise or hardware envelope on a channel.
The SID sound chip is more powerful than the AY sound chip.

== Comparing Amstrad Plus and C64 ==

* The C64 was released in 1982, the Plus released in 1990.

* The C64 has a palette of 16 colours. The Plus has a palette of 4096 colours.

* The C64 has a 1.0MHz 6510 CPU (a 6502 based CPU with I/O ports based at location &0000 and &0001). The Plus has a 4.0Mhz Z80 CPU.

* Both the C64 and Plus have pixel-by-pixel hardware scrolling both in the horizontal and vertical.

* Both the C64 and Plus have programmable raster interrupts. e.g. you can set whichline of the display an interrupt can occur on.

* Both have [[ASIC]] video chips: the C64 has the VIC video chip. The Plus has the AMS40489 ASIC.

== Sprite Comparisons ==

C64:
* The C64 has 8 hardware sprites.
* Each sprite can be one of two resolutions: high resolution or multicolour.
* The sprites use the same palette as the main screen. You can define 1 unique colour for each sprite. In multicolour mode 2 colours are shared between each sprite.
* The priority of sprite-to-sprite is fixed. Sprite 0 has a higher priority than sprite 8.
* The pixel size in high resolution is comparable to CPC's mode 1. Each pixel can be either transparent OR a colour unique for each sprite. The pixel size in multicolour is comparable to CPC's mode 0 and each pixel can be transparent or 1 of the other 3 colours.
* Each sprite can be magnified in height.
* Sprite data is fetched from main RAM.

Amstrad CPC:

* Amstrad CPC doesn't have hardware sprites. All sprites must be drawn and erased using the CPU. It is therefore slower to draw sprites on the CPC.

Amstrad Plus:

(Plus features must be enabled first before sprites can be used)

* The Plus has 16 hardware sprites.
* The sprites have their own seperate palette of 16 colours chosen out of 4096 colours.
* The priority of sprite-to-sprite is fixed.
* Each sprite can be unmagnified (mode 2 resolution), x2 (mode 1 resolution) or x4 (mode 0 resolution). They can also be magnified in height.
* Sprite data is stored in on-board ASIC RAM.

COTS

2017-03-09T06:08:50Z

Dingo:

'''[[COTS]]''' stands for '''Commercial Off-The-Shelf''' and means any component that is freely available and/or well-documented.

== IC ==
Especially in Integrated Circuit (IC) chips, it is the contrary to [[ASIC]], "Application-Specific IC" that are custom-built. [[COTS]] components normally are mass-produced in higher numbers and, therefore, cost-effective.

As supply chains for chip manufacture were all out-sourced to South East Asia, where Red China uses massive government subsidies and workers live in barracks, many former chip manufacturers in the EU/USA went out of business as customers (like "Apple") discontinued their domestic-built manufacture and relocated to Red China. This makes costs for creating ASIC chips much more prohibitive, reserving it to the biggest companies; many chip designers (ARM Assoc., ex-Acorn) now are "No-Fab", meaning they just sell the designs and specifications to other companies.

[[CPLD]] and [[FPGA]] re-programmable chips have alleviated this, so designers can use IPs or "Softcores", Instruction set Processors, to attain ASIC capabilities; as reprogrammable chips now are available to the hobbyist market, discontinued chips can be simulated by those chips.

== CPC ==
The Amstrad CPC does not make heavy use of ASICs; the [[MSX]] series, however, holds the pole-position as it is exclusively constructed using [[COTS]] component so many manufacturers could build them. Commodore, instead, acquired MOS technologies and relied heavily on ASIC chips for all their product lines apart from the IBM PC/XT/AT-compatibles.

The CPC uses those [[COTS]] chips:
* Zilog [[Z80]] CPU
* General Instruments [[AY-3-8912]] [[PSG]], also built by Yamaha as the [[Ym2149]], as sound chip (also used in the [[MSX]] platform)
* Motorola [[6845 CRTC]]; however, the different manufactures use by Amstrad cause incompatibilities, and it was combined to a Gate Array [[ASIC]]. In later generations (cost-down CPC and CPD+), this chip was integrated into an Amstrad ASIC.
* NEC [[765 FDC]] as Floppy controller
* NEC [[8255 PPI chip]] as Programmable Peripheral Interface (PIO)

COTS

2017-03-09T06:08:10Z

Dingo: Created page with "'''COTS''' stands for '''Commercial Off-The-Shelf''' and means any component that is freely available and/or well-documented. == IC == Especially in Integrated Circui..."

'''[[COTS]]''' stands for '''[[Commercial Off-The-Shelf]]''' and means any component that is freely available and/or well-documented.

== IC ==
Especially in Integrated Circuit (IC) chips, it is the contrary to [[ASIC]], "Application-Specific IC" that are custom-built. [[COTS]] components normally are mass-produced in higher numbers and, therefore, cost-effective.

As supply chains for chip manufacture were all out-sourced to South East Asia, where Red China uses massive government subsidies and workers live in barracks, many former chip manufacturers in the EU/USA went out of business as customers (like "Apple") discontinued their domestic-built manufacture and relocated to Red China. This makes costs for creating ASIC chips much more prohibitive, reserving it to the biggest companies; many chip designers (ARM Assoc., ex-Acorn) now are "No-Fab", meaning they just sell the designs and specifications to other companies.

[[CPLD]] and [[FPGA]] re-programmable chips have alleviated this, so designers can use IPs or "Softcores", Instruction set Processors, to attain ASIC capabilities; as reprogrammable chips now are available to the hobbyist market, discontinued chips can be simulated by those chips.

== CPC ==
The Amstrad CPC does not make heavy use of ASICs; the [[MSX]] series, however, holds the pole-position as it is exclusively constructed using [[COTS]] component so many manufacturers could build them. Commodore, instead, acquired MOS technologies and relied heavily on ASIC chips for all their product lines apart from the IBM PC/XT/AT-compatibles.

The CPC uses those [[COTS]] chips:
* Zilog [[Z80]] CPU
* General Instruments [[AY-3-8912]] [[PSG]], also built by Yamaha as the [[Ym2149]], as sound chip (also used in the [[MSX]] platform)
* Motorola [[6845 CRTC]]; however, the different manufactures use by Amstrad cause incompatibilities, and it was combined to a Gate Array [[ASIC]]. In later generations (cost-down CPC and CPD+), this chip was integrated into an Amstrad ASIC.
* NEC [[765 FDC]] as Floppy controller
* NEC [[8255 PPI chip]] as Programmable Peripheral Interface (PIO)

6845 CRTC

2017-03-09T05:43:15Z

Dingo: Redirected page to CRTC

#REDIRECT [[CRTC]]

Comparing C64 to CPC

2017-03-09T05:20:18Z

Dingo:

== Comparing CPC and C64 ==

* The C64 was released in 1982, the CPC released in 1984.

* The C64 was designed to be connected to a television (PAL: 50Hz, NTSC: 60Hz). The CPC was designed to be connected to an Amstrad GT65 green screen or CTM640/644 colour monitor.

* The C64 has a dedicated separate tape player. The CPC464 has a dedicated tape player built in, or for CPC664 and CPC6128 any tape player could be used with a suitable lead.

* The C64 has a palette of 16 colours. The Amstrad has a palette of 27 colours.

* The C64 has a 1.0MHz 6510 CPU (a 6502 based CPU design). The CPC has a 4.0Mhz [[Z80]] CPU.

* The C64 has a programmable raster interrupt. You can define the line at which the interrupt will be triggered and you can do this multiple times during a frame. The CPC has 6 "raster" interrupts at fixed positions through the 50Hz frame.

* The C64 has 50Hz and 60Hz variants (for regions where PAL and NTSC are used). The CPC is 50Hz only.

* The C64's color RAM, SID, VIC and other hardware can be made visible within the 6510's memory space. Access to them is done using normal memory read/write operations. All access to the CPC's hardware is done using the Z80's special I/O instructions (IN/OUT).

* The C64 has two resolutions: high and multi-colour. The pixel sizes are compareable to Amstrad's mode 1 and mode 0. The Amstrad has 3 display resolutions: low, medium and high. The high resolution on the CPC is higher than the C64's.

* The C64 has character and bitmap based modes. The CPC modes are all bitmapped.

* The C64 has pixel-by-pixel hardware scrolling in both the horizontal and vertical. The CPC has hardware scrolling. Using R5 of the CRTC and Rupture demo technique pixel-by-pixel scrolling in the vertical direction can be achieved. Using R3 of the CRTC 1 byte at a time in the horizontal is possible (which equates to 2 pixels in mode 0, 4 in mode 1, and 8 in mode 2).

* The C64 has the SID [[ASIC]] sound chip. The CPC has the [[AY-3-8912]] [[COTS]] sound chip.

* The C64 has the VIC [[ASIC]] video chip. The CPC has the [[COTS]] [[6845 CRTC]] and an [[ASIC]] Gate-Array.

* The C64 tape loading is done through interrupts so is not intensive on the CPU. The CPC tape loading is very intensive on the CPU.

* The C64 communicates with the disc drive through a wired serial connection. This means loading from disc is slow unless a special loader is used. The CPC's disc interface uses a [[COTS]] [[NEC765]] disc controller and uses byte-by-byte data transfer so is much quicker.

* The C64 can easily play music while loading from tape or disc and do other graphical effects at the same time. The CPC can play music during tape or disc loading but it's more processor intensive and is restricted to no other effects when this is done.

* The CPC can do overscan and any pixels can be shown here, the C64 can do it but it's more processor intensive and only sprites can be displayed in this area. (The C64 can open the lower and upper border with much less processor time, it takes much more time to open the side borders).

==Palette comparison==

Amstrad has a palette of 27 colours formed by mixing 0, "half" or "full" of R,G,B. The colours are vibrant.
The Amstrad's palette however is lacking in browns and greys. The colours themselves are consistent between machines.

The C64 has a palette of 16 colours. The colours were chosen by the designers. It has a couple of greys and some browns.
The colours appear different on NTSC and PAL due to the way these transmit their colour signals, and in addition the colour is not always the same between machines.

Both have a good range of colours that can produce great pictures.

==Comparison of the SID and AY-3-8912==

SID:

* 3 tone channels
* 4 waveform types (sawtooth, triangle, pulse, noise), selectable per channel
* Ring-Modulation
* Programmable filter
* Programmable hardware envelopes on any channel

AY:

* 3 tone channels (square waveforms only)
* 1 noise channel
* 1 hardware envelope (with programmable waveform)
* the volume for each channel can be set or controlled by the hardware envelope.
* The mixer can be used to enable/disable tone output for each channel, enable noise or hardware envelope on a channel.
The SID sound chip is more powerful than the AY sound chip.

== Comparing Amstrad Plus and C64 ==

* The C64 was released in 1982, the Plus released in 1990.

* The C64 has a palette of 16 colours. The Plus has a palette of 4096 colours.

* The C64 has a 1.0MHz 6510 CPU (a 6502 based CPU with I/O ports based at location &0000 and &0001). The Plus has a 4.0Mhz Z80 CPU.

* Both the C64 and Plus have pixel-by-pixel hardware scrolling both in the horizontal and vertical.

* Both the C64 and Plus have programmable raster interrupts. e.g. you can set whichline of the display an interrupt can occur on.

* Both have [[ASIC]] video chips: the C64 has the VIC video chip. The Plus has the ASIC.

== Sprite Comparisons ==

C64:
* The C64 has 8 hardware sprites.
* Each sprite can be one of two resolutions: high resolution or multicolour.
* The sprites use the same palette as the main screen. You can define 1 unique colour for each sprite. In multicolour mode 2 colours are shared between each sprite.
* The priority of sprite-to-sprite is fixed. Sprite 0 has a higher priority than sprite 8.
* The pixel size in high resolution is comparable to CPC's mode 1. Each pixel can be either transparent OR a colour unique for each sprite. The pixel size in multicolour is comparable to CPC's mode 0 and each pixel can be transparent or 1 of the other 3 colours.
* Each sprite can be magnified in height.
* Sprite data is fetched from main RAM.

Amstrad CPC:

* Amstrad CPC doesn't have hardware sprites. All sprites must be drawn and erased using the CPU. It is therefore slower to draw sprites on the CPC.

Amstrad Plus:

(Plus features must be enabled first before sprites can be used)

* The Plus has 16 hardware sprites.
* The sprites have their own seperate palette of 16 colours chosen out of 4096 colours.
* The priority of sprite-to-sprite is fixed.
* Each sprite can be unmagnified (mode 2 resolution), x2 (mode 1 resolution) or x4 (mode 0 resolution). They can also be magnified in height.
* Sprite data is stored in on-board ASIC RAM.

ASIC

2017-03-09T04:47:07Z

Dingo:

'''Application-Specific Integrated Circuit''' (ASIC)

An '''ASIC''' is an especially manufactured custom chip designed to fulfill special functions.

The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available ([[COTS]]), but has to be ordered as a genuine part, prices dictated by the seller.

After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like [[CPLD]] or [[FPGA]], they essentially became unavailable. [[Commodore_64#ICs|Commodore]] used a plethora of ASICs in their machines (VIC, SID, PAULA,......); [[MSX]] or the [[IBM PC]]/XT/AT were the opposite in using only [[COTS]] components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).

==Amstrad Custom chips==

The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).

Latter [[CPC]] cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the [[CRTC]].

The Amstrad [[Plus]] included a "second heart" simply referred as the ASIC.

CPC+ ASIC's part number is 40489

==Emulated chips==

CPC+ ASIC emulates the following chips :

* [[CRTC]] 6845
* [[Gate Array]]
* [[PAL16L8|PAL]] (128K RAM paging)
* [[8255 PPI]]
* Printer Port Data and Strobe
* Floppy Motor enable [[flip-flop]], Floppy Address decoding (FDC chip Select)

==New features==

This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".

*Hardware Sprites.
*Soft scrolling (in complement with register 12&13 of the CRTC)
*Screen splitting
*Programmable and vectorised interrupts
*DMA sound channels
*Specific ROM switching

== Known Flaws==

The Amstrad Plus ASIC improved a lot of the old CPC's capability.
Yet this was a bit flawed.

*Despite removing some tasks from the CPU ([[Z80]]), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.

*PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.

*Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high word for vector table. ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC generates sometimes a bad values and the raster interrupt routine is called instead of DMA0 routine. The reasons of this bug are not known.

*There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.

*Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.

*Original CPC colors emulation is not correct.

==Internal Links==

*[[Arnold V specs]]
*[[Arnold V Specs Revised]]
*[[Programming:Unlocking ASIC]]
*[[B-ASIC]]

*[[CRTC]]
*[[Gate Array]]

==External Links==

*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia]
General information on ASICs.

*[http://www.cpctech.org.uk/docs/arn5new.html Asic and Plus features at Unofficial CPC ressources 1.4]
*[http://www.cpctech.org.uk/docs/arnold5a.html Asic and Plus features at Unofficial CPC ressources 1.5]
*[http://www.cpctech.org.uk/docs/cpcplus.html Extra Plus Hardware Information]

[[Category:CPC Plus|*]][[Category:Electronic Component]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]]
[[Category:Stub]][[Category:CPC Internal Components]]

Commodore 64

2017-03-09T04:42:47Z

Dingo: /* The C64 family */

[[Image:Commodore64.jpg|320px|right]]
''This entry is copied from english Wikipedia''

The '''Commodore 64''' is an 8-bit home computer introduced by Commodore International in January 1982. Volume production started in the spring of 1982, with machines being released on to the market in August at a price of US $595.Preceded by the Commodore VIC-20 and Commodore MAX Machine, the C64 features 64KB (65,536 bytes) of memory with sound and graphics performance that were superior to IBM-compatible computers of that time. It is commonly known as the '''C64''' or '''C=64''' (after the graphic logo on the case) and occasionally as the '''CBM 64''' (for '''C'''ommodore '''B'''usiness '''M'''achines), or '''VIC-64'''. It has also been affectionately nicknamed the "breadbox" and "bullnose" due to the shape and color of the first version of its casing.

During the C64's lifetime, sales totaled between 12.5 and 17 million units, making it the best-selling single personal computer model of all time. For a substantial period of time (1983–1986), the C64 dominated the market with between 30% and 40% share and 2 million units sold per year, outselling the IBM PC clones, Apple Inc. computers, and Atari 8-bit family computers. Sam Tramiel, a former Atari president and the son of Commodore's founder, said in a 1989 interview "When I was at Commodore we were building 400,000 C64s a month for a couple of years."

Part of its success was because it was sold in retail stores instead of electronics stores. Commodore produced many of its parts in-house to control supplies and cost. It is sometimes compared to the Ford Model-T automobile for its role in bringing a new technology to middle-class households via creative mass-production.

Approximately 10,000 commercial software titles were made for the Commodore 64 including development tools, office productivity applications, and games. Various C64 emulators allow anyone with a modern computer, or a compatible game console, to run these programs today. The machine is also credited with popularizing the computer demoscene|demo scene. The C64 is still used today by some computer hobbyists

[[Image:C64 startup animiert.gif|260px|left|thumb|The Commodore 64 startup screen]]

In Europe, the primary competitors to the C64 were the British-built [[ZX Spectrum|Sinclair ZX Spectrum]], BBC Micro computer and the [[CPC|Amstrad CPC 464]]. In the UK, the Spectrum had been released a few months ahead of the C64, and was selling for less than half the price. The Spectrum quickly became the market leader and Commodore had an uphill struggle against the Spectrum as it could not rely on undercutting the competition. The C64 debuted at £399 in early 1983, while the Spectrum cost £175. The C64 would later rival the Spectrum in popularity in the latter half of the 1980s, eventually outliving the Spectrum, which was discontinued in December 1990.

Despite a few attempts by Commodore to discontinue the C64 in favor of other, higher priced machines, constant demand made its discontinuation a hard task. By 1988, Commodore was selling 1.5 million C64s worldwide. Although demand for the C64 dropped off in the US by 1990, it continued to be popular in the UK and other European countries. In the end, economics, not obsolescence, sealed the C64's fate. In March 1994, at CeBIT in Hanover|Hanover, Germany, Commodore announced that the C64 would be finally discontinued in 1995. Commodore stated that the C64's 1541 |disk drive was more expensive to manufacture than the C64 itself. Although Commodore had planned to discontinue the C64 by 1995, the company filed for bankruptcy a month later, in April 1994.

===The C64 family===
[[Image:CommodoreMAX isolated.png|250px|Commodore MAX Machine (1982)|thumb]]
[[Image:Sx-64 build crop.jpg|150px|250px|Commodore SX-64 (1984)|thumb]]
[[Image:Commodore64GamesSystem.png|250px|Commodore 64 Games System "C64GS" (1990)|thumb]]

1982: Commodore released the Commodore MAX Machine in Japan. It is called the Ultimax in the US, and VC-10 in Germany. The MAX was intended to be a game console with limited computing capability, and was based on a very cut-down version of the hardware family later used in the C64. The MAX was discontinued months after its introduction, because of poor sales in Japan.

1983 saw Commodore attempt to compete with the Apple II's hold on the U.S. education market with the [[Educator 64]], essentially a C64 and monochrome monitor in a PET case. Schools preferred the all-in-one metal construction of the PET over the standard C64's separate components, which could be easily damaged, vandalized or stolen.

In 1984, Commodore released the SX-64, a portable version of the C64. The SX-64 has the distinction of being the first ''full-color'' portable computer. The base unit featured a CRT and an integrated 1541 floppy disk drive. The SX-64 did not have a cassette connector.

Commodore, specifically two designers; Fred Bowen and Bil Herd, were determined to avoid the problems of the Plus/4, making sure that the eventual successors to the C64—the Commodore 128 and 128D computers (1985)—were as good as, and fully compatible with the original, as well as offering a host of improvements (such as a structured BASIC with graphics and sound commands, 80-column display capability, and full CP/M compatibility). The decision to make the Commodore 128 compatible with the C64 was made quietly by Bowen and Herd , software and hardware designers respectively, without the knowledge or approval by the management in the post Jack Tramiel era. The designers were careful not to reveal their decision until the project was too far along to be challenged or changed and still make the impending Consumer Electronics Show (CES) show in Las Vegas. Upon learning that the C128 was designed to be compatible with the C64, Commodore’s marketing department independently announced that the C128 would be 100% compatible with the C64, thereby raising the bar for C64 support.

[[Image:C64c system.jpg|thumb|left|Commodore 64C with 1541-II floppy disk drive and 1084S monitor displaying television-compatible S-video]]

In 1986, Commodore released the Commodore 64C (C64C) computer, which was functionally identical to the original, but whose exterior design was remodeled in the sleeker style of the Commodore 128 and other contemporary design trends. The modifications to the C64 line were more than skin deep in the C64C with new versions of the SID, VIC and I/O chips being deployed—with the core voltage reduced from 12 V to 9 V. In the United States, the C64C was often bundled with the third-party GEOS GUI-based operating system. The Commodore 1541 disk drive received a matching face-lift resulting in the 1541c. Later a smaller, sleeker 1541-II model was introduced along with the 800KB 3.5-inch capable 1581.

In 1990, the C64 was re-released in the form of a game console, called the C64 Games System (C64GS). A simple modification to the C64C's motherboard was made to orient the cartridge connector to a vertical position. This allowed cartridges to be inserted from above. A modified ROM replaced the BASIC interpreter with a boot screen to inform the user to insert a cartridge. It was designed to rival the Nintendo Entertainment System and the Sega Master System but it suffered from very low sales compared to its rivals and it was another commercial failure for Commodore, and it was never released outside of Europe.

In 1990, an advanced successor to the C64, the Commodore 65 (also known as the "C64DX"), was prototyped, but the project was canceled by Commodore's chairman Irving Gould in 1991. The C65's specifications were very good for an 8-bit computer. For example, it could display 256 colors on screen, while OCS based Amigas could only display 64 in HalfBrite mode (32 colors and half-bright transformations); the HAM mode on the Amiga allowed all 4096 colors of the 12 bit color system, but it was awkward to use and had restrictions on color combinations between adjacent pixels. Although no specific reason was given for the C65's cancellation, it would have competed in the marketplace with Commodore's lower end Amigas and the CDTV.

==Software==
[[Image:C64 IKPlus.png|thumb|Screenshot of ''International Karate +'']]

At the time of its introduction, the C64's graphics and sound capabilities were rivaled only by the Atari 8-bit family. This was at a time when most IBM PCs and compatibles had text-only display adapter cards, monochrome monitors, and sound consisting of squeaks and beeps from the built-in tiny, low-quality speaker.

The C64 is often credited with starting the computer subculture known as the demoscene. The C64 lost its top position among demo coders when the 16-bit Commodore Amiga and Atari ST were released in 1985, however it still remained a very popular platform for demo coding up to the early 90s

It is still being actively used as a demo machine , especially for music (its sound chi] even being used in special sound cards for PCs, and the Elektron SidStation synthesizer). Unfortunately, the differences between PAL and NTSC C64s caused compatibility problems between U.S./Canadian C64s and those from most other countries. The vast majority of demos run only on PAL machines.

Even though it was released in 1982, the C64 was still a strong competitor to the later consoles Nintendo Entertainment System and Sega Master System] thanks to its by-then established software base.

During the 1980s, the Commodore 64 was used to run numerous Bulletin Board Systems using software packages such as Bizarre 64, Blue Board and Color 64, often with sysop-made modifications. These boards often were used to distribute cracked software.

===BASIC===
[[Image:Simons Basic Splash Screen.gif|thumb|right|The Simons' BASIC start-up screen. Note the altered background and text colours (vs the ordinary C64 blue tones), and the 8KB reduction of available BASIC program memory due to the address space used by the cartridge.]]

As was common for machines of the time, the C64 incorporated a ROM based version of the BASIC programming language. Commodore BASIC 2.0 was used instead of the more advanced BASIC 4.0 from the PET series, since its users were not expected to need the disk-oriented enhancements of BASIC 4.0. "The choice of BASIC 2.0 instead of 4.0 was made with some soul-searching, not just at random. The typical user of a C64 is not expected to need the direct disk commands as much as other extensions, and the amount of memory to be committed to BASIC was to be limited. We chose to leave expansion space for color and sound extensions instead of the disk features. As a result, you will have to handle the disk in the more cumbersome manner of the 'old days'."

The version of BASIC was limited and did not include commands for sound or graphics manipulation, instead users had to use the "POKE" command to access the graphics and sound chip registers directly. In order to provide extended commands including graphics and sound Commodore produced two different cartridge-based extension to BASIC 2.0 — Simons' BASIC and Super Expander 64.

===Alternative operating systems===
A number of third party operating systems have been developed for the C64.
[[Image:GeOS Commodore 64.gif|thumb|GEOS for the Commodore 64]]

As well as the original GEOS, two third-party GEOS-compatible operating systems have been written: Wheels and GEOS megapatch. Both of these require hardware upgrades to the original C64.

Several other operating systems are or have been available, including WiNGS OS, the Unix-like LUnix, operated from a command-line, and the embedded systems OS Contiki, with full GUI. Other less well known OSes include ACE, Asterix, DOS/65 and GeckOS.

A version of CP/M was released, but this required the addition of an external Z80 processor to the expansion bus, so is not considered a true C64 OS. Furthermore, the Z80 processor was underclocked to be compatible with the C64's memory bus, so performance was poor compared to other CP/M implementations. C64 CP/M and C128 CP/M both suffered a lack of software: although most commercial CP/M software would technically run on these systems, software media was incompatible between platforms. The low usage of CP/M on Commodores meant that software houses saw no need to invest in mastering versions for the Commodore filesystem. The Commodore 1571 disk drive was made compatible with a wide variety of disk formats to eliminate this weakness.

===Networking software===
[[Image:Qlink-mainmenu.png|thumb|Quantum Link main menu]]

Quantum Link (or Q-Link) was a U.S. and Canadian online service for Commodore 64 and 128 personal computers that operated from November 5, 1985 to November 1, 1994. It was operated by Quantum Computer Services of Vienna, Virginia, which in October 1991 changed its name to America Online, and continues to operate its AOL service for the IBM PC and Apple Macintosh today. Q-Link was a modified version of the PlayNET system, which Control Video Corporation (CVC, later renamed Quantum Computer Services) licensed.

The Quantum Link networking service became America Online which became AOL-Time Warner which was then contracted to AOL.

==Hardware==

===CPU and memory===

The C64 uses an 8-bit MOS Technology 6510 microprocessor. This is a close derivative of the 6502 with an added 6-bit internal I/O port that in the C64 is used for two purposes: to bank-switch the machine's ROM in and out of the processor's address space, and to operate the datasette tape recorder.

The C64 has 64B of RAM, of which 38kB are available to built-in Commodore BASIC 2.0.

===Graphics===
[[Image:Mayhem in monsterland mini.gif|right|frame|In-game sprite of Mayhem in Monsterland]]

The graphics chip, VIC-II, features 16 colors, eight hardware sprites per scanline (enabling up to 112 sprites per PAL screen), scrolling capabilities, and two bitmap graphics modes. The standard text mode features 40 columns, like most Commodore PET models; the built in character encoding is not standard ASCII but PETSCII, an extended form of ASCII-1963.

Most screen shots show borders around the screen, which is a feature of the VIC-II chip. By utilising interrupts to reset various hardware registers on precise timings it was possible to place graphics within the borders and thus utilise the full screen.

===Sound===

The sound chip, SID, has three channels, each with its own ADSR envelope generator, ring modulation and filter capabilities. It was designed by Bob Yannes, who would later co-found synthesizer company Ensoniq. Yannes criticized other contemporary computer sound chips as "primitive, obviously... designed by people who knew nothing about music". Often the game music became a hit of its own among C64 users. Well-known composers and programmers of game music on the C64 are Rob Hubbard, David Whittaker, Chris Hulsbeck, Ben Daglish, Martin Galway among many others. Due to the chip's limitation to three channels, chords are played as arpeggios typically, coining the C64's characteristic lively sound. It was also possible to continuously update the master volume with sampled data to enable the playback of 4-bit digitized audio. As of 2008 it even became possible to play 4 channel 8 bit audio samples, 2 SID channels and still use filtering.

There are two versions of the SID chip, the 6581 and the 8580. The MOS Technology 6581 was used in all of the original "breadbox" C64s, the early versions of the C64C and the Commodore 128. The 6581 was replaced with the MOS Technology 8580 in 1987. The 6581 sound quality is a little more crisp, and many Commodore 64 fans prefer its sound. The main difference between the 6581 and the 8580 is the supply voltage. The 6581 uses a 12 volt supply, the 8580, a nine volt supply. A modification can be made to use the 6581 in a C64C board (which uses the nine volt chip).

The SID chip has a distinctive sound which retained a following of devotees to such a degree, that a number of audio enthusiasts and companies have designed SID-based products as add-ons for the C64, x86 PCs and standalone or MIDI music devices such as the Elektron SidStation. These devices use chips taken from excess stock, or removed from used computers.

In 2007, Timbaland's extensive use of the SidStation led to the 2007 Timbaland plagiarism controversy around his tracks ''Block Party'' and ''Do It'' (written for Nelly Furtado).

===Hardware revisions===
Cost reduction was the driving force behind the C64's motherboard revisions. Reducing manufacturing costs was vitally important to Commodore's survival during the price war and leaner years of the 16-bit era. The C64's original (NMOS based) motherboard would go through two major redesigns, (and numerous sub-revisions) exchanging positions of the VIC-II, SID and PLA chips. Initially, a large portion of the cost was eliminated by reducing the number of discrete components, such as diodes and resistors, which enabled the use of a smaller printed circuit board.

[[Image:C64motherboard.jpg|thumb|right|350px|An early C64 motherboard (Rev A PAL 1982).]]
[[Image:C64Cmotherboard.jpg|thumb|right|350px|A C64C motherboard ("C64E" Rev B PAL 1992).]]

====ICs====
The VIC-II was manufactured with 5 micrometre] NMOS technology and was clocked at either 17.73447MHz (PAL) or 14.31818MHz (NTSC). Internally, the clock was divided down to generate the dot clock (about 8MHz) and the two-phase system clocks (about 1MHz; the exact pixel and system clock speeds are slightly different between NTSC and PAL machines). At such high clock rates, the chip generated a lot of heat, forcing MOS Technology to use a ceramic [[Dual in-line package|DIL package]] (called a "CERDIP"). The ceramic package was more expensive, but it dissipated heat more effectively than plastic.

After a redesign in 1983, the VIC-II was encased in a plastic Dual Inline Package, which reduced costs substantially, but it did not totally eliminate the heat problem. Without a ceramic package, the VIC-II required the use of a heat sink. To avoid extra cost, the metal RF shielding doubled as the heat sink for the VIC, although not all units shipped with this type of shielding. Most C64s in Europe shipped with a cardboard RF shield, coated with a layer of metal foil. The effectiveness of the cardboard was highly questionable, and worse still it acted as an insulator, blocking airflow which trapped heat generated by the SID, VIC, and PLA chips.

The SID was manufactured using NMOS at 7 and in some areas 6 micrometers. The prototype SID and some very early production models featured a ceramic Dual Inline Package, but unlike the VIC-II, these are extremely rare as the SID was encased in plastic when production started in early 1982.

====Motherboard====
In 1986, Commodore released the last revision to the classic C64 motherboard. It was otherwise identical to the 1984 design, except for the two 64 kilobit * 4 bit DRAM chips that replaced the original eight 64 kilobit * 1 bit ICs.

After the release of the C64C, MOS Technology began to reconfigure the C64's chipset to use HMOS production technology. The main benefit of using HMOS was that it required less voltage to drive the IC, which consequently generates less heat. This enhanced the overall reliability of the SID and VIC-II. The new chipset was re-numbered to 85xx in order to reflect the change to HMOS.

In 1987 Commodore released C64Cs with a totally redesigned motherboard commonly known as a "short board". The new board used the new HMOS chipset, featuring a new 64-pin PLA chip. The new "SuperPLA", as it was dubbed, integrated many discrete components and TTL chips. In the last revision of the C64C motherboard, the 2114 color RAM was integrated into the SuperPLA.

===Power supply===
The C64 used an external power supply. This saved space within the computer's case. The 1541-II and 1581 disk drives, along with various third-party clones, also came with their own external power supply "bricks". These power supplies were notorious for failing over time. Many lasted less than two years and had to be replaced. Commodore later changed the design, however the new version was also prone to failure. It has been speculated that these supplies failed due to voltage regulator overheating. They were entirely encapsulated within an epoxy resin, a poor conductor of heat and impossible to repair. As of 2010, many Commodore 64 owners use home-made power supplies, often using separate 5 volt DC and 9 volt AC power supplies, wired to a common plug that attaches to the Commodore 64.

===Specifications ===
====Internal hardware====
*Microprocessor CPU:
**MOS Technology 6510|MOS Technology 6510/8500 (the 6510/8500 being a modified 6502 with an integrated 6-bit I/O port)
**Clock speed: 0.985 MHz (PAL) or 1.023 MHz (NTSC)
*Video: MOS Technology VIC-II 6567/8562 (NTSC), 6569/8565 (PAL)
**16 colors
**Text mode: 40*25 characters; 256 user-defined chars (8*8 pixels, or 4*8 in multicolor mode); 4-bit color RAM defines foreground color
**Bitmap modes: 320*200 (2 unique colors in each 8*8 pixel block), 160*200 (3 unique colors + 1 common color in each 4*8 block)
**8 hardware sprites of 24*21 pixels (12*21 in multicolor mode)
**Smooth scrolling, raster interrupts
*Sound: MOS Technology 6581/8580 SID
**3-channel synthesizer with programmable ADSR envelope
**8 octaves
**4 waveforms per audio channel: triangle, sawtooth, variable pulse, noise
**Oscillator synchronization, ring modulation
**Programmable filter: high pass, low pass, band pass, notch filter
*Input/Output: Two 6526 Complex Interface Adapters
**16 bit parallel I/O
**8 bit serial I/O
**24-hours (AM/PM) Time of Day clock (TOD), with programmable alarm clock
**16 bit interval timers
*RAM:
**64kB, of which 38kB (minus 1 byte) were available for BASIC programs
**512 bytes color RAM (memory allocated for screen color data storage)
**Expandable to 320kB with Commodore 1764 256kB RAM Expansion Unit (REU); although only 64kB directly accessible; REU mostly intended for GEOS. REUs of 128kB and 512kB, originally designed for the C128, were also available, but required the user to buy a stronger power supply from some third party supplier; with the 1764 this was included. Creative Micro Designs also produced a 2MB REU for the C64 and C128, called the 1750 XL. The technology actually supported up to 16MB, but 2MB was the biggest one officially made. Expansions of up to 16MB were also possible via the CMD SuperCPU.
*ROM:
**20kB (9kB BASIC 2.0; 7kB Kernel; 4kB character generator, providing two 2kB character sets)

====I/O ports and power supply====
[[Image:C64 Interfaces.jpg|thumb|right|300px|Commodore 64 ports (from left: Cartridge, RF-adj, RF, A/V, 488, Tape, User + Joy1, Joy2, Power)]]

*I/O ports:
**Cartridge expansion slot (slot for edge connector with 6510 CPU address/data bus lines and control signals, as well as GND and voltage pins; used for program modules and memory expansions, among others)
**Integrated RF modulator antenna output via a RCA connector. The used channel could be adjusted from number 36 with the potentiometer to the left.
**8-pin DIN connector containing composite video output, separate Y/C outputs and sound input/output. Beware that this is the 270° (horseshoe) version of the plug, not the 360° circular version. Also note that some early C64 units use a 5-pin DIN connector that carries composite video and luminance signals, but lacks a chroma signal.
**Serial bus (serial version of IEEE-488, 6-pin DIN plug) for CBM printers and disk drives
**PET-type Commodore Datassette 300 baud tape interface (edge connector with digital cassette motor/read/write/key-sense signals, Ground and +5V DC lines. The cassette motor is controlled by a +5V DC signal from the 6502 CPU. The 9 V AC input is transformed into unregulated 6.36 V DC which is used to actually power the cassette motor.
**User port (edge connector with TTL-level signals, for modems etc.; byte-parallel signals which can be used to drive third-party parallel printers, among other things, 17 logic signals, 7 Ground and voltage pins, including 9V AC)
**2 * screwless DE9M game controller ports (compatible with Atari 2600 controllers), each supporting five digital inputs and two analog inputs. Available peripherals included digital joysticks, analog paddles, a light pen, the Commodore 1351 mouse, and the unique KoalaPad.

*Power supply:
**5V DC and 9VAC from an external "power brick", attached to a 7-pin female DIN-connector on the computer

====Comparison====
*[[Comparing C64 to CPC]]

====Peripherals====
<gallery widths="160px" heights="120px" perrow="4">
Image:Commodore 1541 front cropped.jpg|Commodore 1541 Floppy Drive, 1st model.
Image:Commodore 1541 white.jpg|Commodore 1541C Floppy Drive, 2nd model.
Image:C64-IMG 5372.jpg|Commodore 1541-II Floppy Drive, 3rd model.
Image:Commodore-Datassette.jpg|Commodore 1530 Datasette
Image:Commodore Matrixdrucker MPS-802.jpg|Commodore MPS-802 Dot-matrix Printer
Image:CommodoreVICModem.jpg|Commodore VIC-Modem
Image:Commodore blockomaus.jpg|Commodore Mouse
Image:Commodore_1702_(made_by_JVC)_front.jpg|Commodore 1702 video monitor
</gallery>

[[Category:Non CPC Computers]]

ASIC

2017-03-09T04:35:22Z

Dingo: a bit expanded. Q: Is there a software or HDL emulation of the "Amstrad ASIC" and the "VGA"?

'''Application-Specific Integrated Circuit''' (ASIC)

An '''ASIC''' is an especially manufactured custom chip designed to fulfill special functions.

The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available ([[COTS]]), but has to be ordered as a genuine part, prices dictated by the seller.

After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like [[CPLD]] or [[FPGA]], they essentially became unavailable. Commodore used a plethora of ASICs in their machines (VIC, SID, PAULA,......); [[MSX]] or the [[IBM PC]]/XT/AT were the opposite in using only [[COTS]] components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).

==Amstrad Custom chips==

The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).

Latter [[CPC]] cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the [[CRTC]].

The Amstrad [[Plus]] included a "second heart" simply referred as the ASIC.

CPC+ ASIC's part number is 40489

==Emulated chips==

CPC+ ASIC emulates the following chips :

* [[CRTC]] 6845
* [[Gate Array]]
* [[PAL16L8|PAL]] (128K RAM paging)
* [[8255 PPI]]
* Printer Port Data and Strobe
* Floppy Motor enable [[flip-flop]], Floppy Address decoding (FDC chip Select)

==New features==

This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".

*Hardware Sprites.
*Soft scrolling (in complement with register 12&13 of the CRTC)
*Screen splitting
*Programmable and vectorised interrupts
*DMA sound channels
*Specific ROM switching

== Known Flaws==

The Amstrad Plus ASIC improved a lot of the old CPC's capability.
Yet this was a bit flawed.

*Despite removing some tasks from the CPU ([[Z80]]), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.

*PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.

*Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high word for vector table. ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC generates sometimes a bad values and the raster interrupt routine is called instead of DMA0 routine. The reasons of this bug are not known.

*There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.

*Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.

*Original CPC colors emulation is not correct.

==Internal Links==

*[[Arnold V specs]]
*[[Arnold V Specs Revised]]
*[[Programming:Unlocking ASIC]]
*[[B-ASIC]]

*[[CRTC]]
*[[Gate Array]]

==External Links==

*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia]
General information on ASICs.

*[http://www.cpctech.org.uk/docs/arn5new.html Asic and Plus features at Unofficial CPC ressources 1.4]
*[http://www.cpctech.org.uk/docs/arnold5a.html Asic and Plus features at Unofficial CPC ressources 1.5]
*[http://www.cpctech.org.uk/docs/cpcplus.html Extra Plus Hardware Information]

[[Category:CPC Plus|*]][[Category:Electronic Component]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]]
[[Category:Stub]][[Category:CPC Internal Components]]

FPGA

2017-03-09T04:25:47Z

Dingo: expanded a bit.

FPGA (field-programmable gate array)

This is a reprogrammable [[COTS]] Instruction set Processor (IP). It consists of a re-programmable ("FP") Gate Array (GA), i.e. a [[FET]] (Field-Effect Transistor) array where the transistors can be set by the FET Gate to "conduct" or "resist". This can flexibly simulate many different logical ICs.

== FPGA basics ==
You know what a "truth table" is ? Here a example : 
'''XOR''' truth table :
A B | C
0 0 | 0
0 1 | 1
1 0 | 1
1 1 | 0

In a truth table you have got eg. 2 input wires, and 1 output wires.

A FPGA is programmed by a LUT (Look-Up Table) that has to be loaded into volatile memory at power-up. In a FPGA LUT you have got 10,000,000,000,000,000 input/output wires.

As it is complex to feed the table values, special languages (HDL - Hardware Description Language) are used to feed them : [[VHDL]] (and -blech!!!- verilog)

The Gate Array (GA) in Amstrad graphics is an [[ASIC]].

== CPLD ==
[[CPLD]] are re-programmable IPs that are faster and non-volatile; however, they are not as versatile as FPGAs, so FPGAs offer more possibilities closed to CPLDs. They consist of AND- and OR-matrices that can be connected to a signal or the inverted signal (NOT); those [[minterm]]s can construct all other logical equasions (to the boundaries of the chip).

Common CPLDs are made by Atheros (now part of Intel) and Altera.

VHDL

2017-03-09T03:52:58Z

Dingo: Expanded; Ada explained (perhaps better to move it into an article of its own); CPLD; Standards

VHDL (very high-level hardware description language)

This is an electronic language having electronic behaviour. You can implement what you want numerical electronic schematics (you can also draw them and translate then into VHDL)

Its syntax does looks like and is derived from the Ada language family. It differs from computer langage as its first instruction does generaly look like :
if rising_edge(clock) then
output_wire <= input_wire xor 1;
end if;

All instructions are run at the same time/edge. Next values being computed from previous values. The time an output value takes to be affected by an input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta-time and number of clock edges, as certain components are using rising_edge and others falling_edge. delta-time is just about vocabulary speaking, it is the time between the action is launched and then takes effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.

You can also have local registered values, using affectation operator ":=", without delta-time (at once) :
output_wire_mem := input_wire xor 1;
output_wire_mem := output_wire_mem xor 1;
output_wire <= output_wire_mem;

== Application ==
VHDL can be synthetised (compiled) into IP (Instruction set Processor) chips like [[CPLD]] and [[FPGA]] chips, apart from generating a [[netlist]] for [[ASIC]] building.

Two families of [[FPGA]] chips exists : Xilinx (Diligent starter-kits are really fun and instructive) and Altera (cheaper). You cannot really compare them, units are not the same between them...

[[CPLD]]s are faster and do not need to re-load their instructions at power-up, but do not offer the flexibility of FPGAs. An Intel 386 has been simulated on a CPLD (Complex Programmable Logic Device). Two common families are Atheros (now Intel) and Altera.

== Characteristics ==
VHDL is more strict than Verilog, Verilog is more C language like. Verilog seems more used in America and VHDL in Europe. But you can plug their components together using drawn schematics.

In order to use the same language concepts in Hardware Description (HDL - Hardware Description Language) and Software development, SystemC was also developed and standardised. There are, however, boni in using VHDL and Ada as development languages from the same family.

Alas, VHDL to-date lacks exception handling, apart from the Assert-pragma.

=== Standardisation ===
VHDL is standardised in IEEE Std 1076 and its substandards. Parts fo them are also part of IEC standard 61691 "Behavioural Languages":
* IEEE Std 1076.1 VHDL Language Reference Manual = IEC 61691-1-1
* IEEE Std 1076.2 VHDL Mathematical Packages = IEC 61691-3-2
* IEEE Std 1076.3 VHDL Synthesis Packages = IEC 61691-3-3
* IEEE Std 1076.4 VITAL ASIC = IEC 61691-5
* IEEE Std 1076.5 VHDL Register Transfer Level Synthesis
* IEEE Std 1076.6 VHDL Analog and Mixed-Signal Extensions = IEC 61691-6

IEC 61691 is a standard for Behavioural Languages (Hardware Design Languages):
* IEC 61691-1-1 VHDL LRM = IEEE Std 1076.1
* IEC 61691-2 VHDL Multilogic System for Model Interoperability
* IEC 61691-3-2: Mathematical Operation in VHDL
* IEC 61691-3-3: Synthesis in VHDL
* IEC 61691-4 Verilog HDL
* IEC 61691-5 VITAL ASIC = IEEE Std 1076.4
* IEC 61691-6 VHDL Analog and Mixed-Signal Extensions = IEEE Std 1076.6
* IEC 61691-7 SystemC LRM

=== Ada language family ===
Ada (iterations Ada83, Ada95, Ada2005 and Ada2012) offers strict typing and is a higher-level language much like PL/I and [[PL/M]] (the HLL used for programming [[CP/M]]); requirements to strictly adhere to standards kept it from forking into countless libraries and frameworks like C and Java. Exception handling (alas, NOT yet implemented in VHDL) and the ASSERT pragma (standard since Ada2005, implemented into VHDL) offer safety constraints. It came out of a 'ricain Department of Defence (DoD) concourse as the winner in 1976 and is an open standard from the start.

Ada became notorious after the ARIANE-5 self-destructed on her maiden voyage; however, it was human failure on the part of a programmer. After it was proven that variable type constraints could not be exceeded by the ARIANE-4, constraint checks were switched off to make the code faster. ARIADNE-5 however, designed as a carrier platform for the cancelled HERMES space shuttle project, was considerably heavier and values DID overflow; however, the programmers re-used ARIADNE-4 code without switching constraint checks (which would have prevented the accident) back on.

The US En Route Air Traffic Control system however in 2009 was completed using Ada2005 under budget and ahead of schedule [http://www.iaeng.org/publication/IMECS2009/IMECS2009_pp1095-1099.pdf due to Ada05's engineering capabilities].

Detrimental to Ada's widespread use in the FLOSS (Free/Libre Open Source Software) community are its "evilness" as a DoD standard and its "differentness" as a Wirthean language (akin to educational PASCAL) for C/C++-programmers; however, [http://www.cs.uni.edu/~mccormic/4740/guide-c2ada.pdf these differences DO address common C/C++ design flaws, so it can be considered an "acquired taste"]. Strongly typed, it tends to display faults ("hidden" points of failure) more often into direct errors (the compiler stops) rather than to allow them to manifest themselves as failures (system stops working suddenly).

Apart from ARIANE rockets and Air Traffic Control systems, it is also used in airplanes, medical technology, the PANAVIA Tornado, the Eurofighter Typhoon, Eurocopter Tigre and NH-90 systems, and about any mission-critical system a simple reboot on failure is no option. Since Ada95, there are Object Oriented addition to Ada. A superset of Ada called SPARK that can be compiled in normal Ada compilers (the extra instructions are inside comments) is for highly verified code; AdaDoc in Ada2012 offers a JavaDoc-like Documentation generation system.

The [http://www.kuhmann.com/Cromemco/Cromemco%20CS250.htm Cromemco CR-250 Motorola 68000 S-100] machine was in widespread use as USAF Mission Support System (1986-1990), so a CP/M Ada83 compiler should be available.

* [http://www.makewithada.org/ Make with Ada programming competition]
* [http://adahome.com/ AdaHome - Home of the Brave Ada Programmers]
* [http://ada-europe.org Ada Europe]
== Tools ==
IDE :
* Xilinx webpack
* Quartus web edition (Altera)

Development starter-kit :
* [http://store.digilentinc.com/ Diligent] (instructive - really nice for learning)
* [http://www.lextronic.fr/ Lextronic] - fr

Final platform (can be also used to develop) :
* [[FPGAmstrad]] on MiST-board
** [http://www.amedia-computer.com Amedia Computer] - fr

== Books ==
* Conception de circuits en VHDL et VHDL-AMS / Principes et méthodologie / Collection POLYTECH / Cépaduès-éditions / D. HOUZET L. BARRANDON
* VHDL-AMS / Applications et enjeux industiels / Cours et exercices corrigés / 2e et 3e cycles écoles d'ingénieurs/ DUNOD / Yannick Hervé

VHDL-AMS is theorical, it is about using an analog version of VHDL not running in FPGA. But VHDL-AMS books does cover also VHDL (if an author of book does understand VHDL-AMS, sure he does understand VHDL perfectly.....)

Dust Covers

2017-03-04T03:04:48Z

Dingo: /* History */

[[Category:CPC History]]
Dust Covers are especially molded plastic or wrapper covers to protect the CPC from dust when switched off. Some people think they have been the most useless hardware add-on ever produced for CPC computers. These accessories have been advertised to "protect" the CPC's dust-resistant ''sealed membrane keyboard'', or even its ''vacuum-based monitor'' against dust.

== History ==

Although being completely useless, dust covers have been (in germany, at least) almost more popular than [[Digital Joysticks|joysticks]]. Whereas, it had to be a ''real'' dust cover - one needed to buy it (using old newspapers or worn T-shirts would have been déclassé).

Today, Dust Covers are more or less unknown. But, they have left some scars: Many people still feel irrationally guilty when exposing computer hardware to dust. The dust cover phenomenon (eighties) can be compared with the hype for equally useless ''mouse pads'' (nineties), ''protective foils'' for LCD screens (first decade of 21st century), and ''sliced bread'' (thirties).

On a more serious note, mouse pads ''were'' a boon prior to all mouses being optical because ball mouses ''do'' tend to be a PITA on polished surfaces. (Nowadays, mats are used to protect the polished surface from scratches by them); and dust covers not hindering air flow are on the wish list of any home-server admin, especially those who have experienced dust fires in long-running servers.

In the 1980, many computers were not put in living rooms, but (childrens') bedrooms, attics, basements or even workshops to control wood- or metal-working hardware. Those places tended to be prone to much dust, and the computer was only on for a few hours a day. Consumer products quite often were prone to mechanical jams due to dust, so especially in professional workshops, covers were regularly used. Industry DP was often so prohibitively expensive that home computers - quite often the C64, but the CPC offered a Z80 and CP/M as a boon - popped up in the most curious places (eg. a C64 was used to control the water supply of a German commune in the mid-80s).

Of course, dish towels ''were'' used; however, in 1987 a [[CPC 6128]] with [[GT64/GT65|GT65]] cost DM1.500,-, not counting the [[Schneider RS232 Interface]] often necessary for controlling applications, plus application-specific sensors and actors - on 2% inflation for 30 years and in €uro, that would be 1500*1,02^30 / 1,95583 = ~€1.390,-. About DM20,- for a molded dust cover that did cover the machine better really did not weigh that much considering those dimensions.

== Pictures ==

<gallery>
Image:Dust-cover-for-6128-keyboard.JPG|CPC 6128 with Dust Cover
Image:Keyboard membrane 1.jpg|Sealed 100% dust-resistant 6128 keyboard membrane
Image:Data Media Advert (CPC International 08-85, page 2).jpg|Advert
Image:Data Media Advert (CPC International 12-85, page 103).jpg|Advert
</gallery>

== Legal Status ==

There are no known laws against producing, distributing, or even using dust covers. However, users are likely to lose their precious warranty if a computer catches fire because of covering its ventilation holes after forgetting to switch off the power-supply. Fortunately, the dust cover users never realized that dilemma, otherwise they'd have probably died from a heart-attack when trying to find a solultion to the question: Risk the warranty, or risk the dust?

As users were often technically savvy, however, that dilemma did occur quite seldom (probably only in metal workshops where the metal-working machine was controlled by CPC when producing metal dust), as the computers were covered only when switched off.

Dust Covers

2017-03-04T03:02:36Z

Dingo:

[[Category:CPC History]]
Dust Covers are especially molded plastic or wrapper covers to protect the CPC from dust when switched off. Some people think they have been the most useless hardware add-on ever produced for CPC computers. These accessories have been advertised to "protect" the CPC's dust-resistant ''sealed membrane keyboard'', or even its ''vacuum-based monitor'' against dust.

== History ==

Although being completely useless, dust covers have been (in germany, at least) almost more popular than [[Digital Joysticks|joysticks]]. Whereas, it had to be a ''real'' dust cover - one needed to buy it (using old newspapers or worn T-shirts would have been déclassé).

Today, Dust Covers are more or less unknown. But, they have left some scars: Many people still feel irrationally guilty when exposing computer hardware to dust. The dust cover phenomenon (eighties) can be compared with the hype for equally useless ''mouse pads'' (nineties), ''protective foils'' for LCD screens (first decade of 21st century), and ''sliced bread'' (thirties).

On a more serious note, mouse pads ''were'' a boon prior to all mouses being optical because ball mouses ''do'' tend to be a PITA on polished surfaces. (Nowadays, mats are used to protect the polished surface from scratches by them); and dust covers not hindering air flow are on the wish list of any home-server admin, especially those who have experienced dust fires in long-running servers.

In the 1980, many computers were not put in living rooms, but (childrens') bedrooms, attics, basements or even workshops to control wood- or metal-working hardware. Those places tended to be prone to much dust, and the computer was only on for a few hours a day. Consumer products quite often were prone to mechanical jams due to dust, so especially in professional workshops, covers were regularly used. Industry DP was often so prohibitively expensive that home computers - quite often the C64, but the CPC offered a Z80 and CP/M as a boon - popped up in the most curious places (eg. a C64 was used to control the water supply of a German commune in the mid-80s).

Of course, dish towels ''were'' used; however, in 1987 a [[CPC 6128]] with [[GT64/GT65|GT65]] cost DM1.500,-, not counting the [[Schneider RS-232]] interface often necessary for controlling applications, plus application-specific sensors and actors - on 2% inflation for 30 years and in €uro, that would be 1500*1,02^30 / 1,95583 = ~€1.390,-. About DM20,- for a molded dust cover that did cover the machine better really did not weigh that much considering those dimensions.

== Pictures ==

<gallery>
Image:Dust-cover-for-6128-keyboard.JPG|CPC 6128 with Dust Cover
Image:Keyboard membrane 1.jpg|Sealed 100% dust-resistant 6128 keyboard membrane
Image:Data Media Advert (CPC International 08-85, page 2).jpg|Advert
Image:Data Media Advert (CPC International 12-85, page 103).jpg|Advert
</gallery>

== Legal Status ==

There are no known laws against producing, distributing, or even using dust covers. However, users are likely to lose their precious warranty if a computer catches fire because of covering its ventilation holes after forgetting to switch off the power-supply. Fortunately, the dust cover users never realized that dilemma, otherwise they'd have probably died from a heart-attack when trying to find a solultion to the question: Risk the warranty, or risk the dust?

As users were often technically savvy, however, that dilemma did occur quite seldom (probably only in metal workshops where the metal-working machine was controlled by CPC when producing metal dust), as the computers were covered only when switched off.

Dust Covers

2017-03-04T03:00:07Z

Dingo: Ahem... THAT fad really was not THAT useless, considering the workshops and basements where the computers stood.

[[Category:CPC History]]
Dust Covers are especially molded plastic or wrapper covers to protect the CPC from dust when switched off. Some people think they have been the most useless hardware add-on ever produced for CPC computers. These accessories have been advertised to "protect" the CPC's dust-resistant ''sealed membrane keyboard'', or even its ''vacuum-based monitor'' against dust.

== History ==

Although being completely useless, dust covers have been (in germany, at least) almost more popular than [[Digital Joysticks|joysticks]]. Whereas, it had to be a ''real'' dust cover - one needed to buy it (using old newspapers or worn T-shirts would have been déclassé).

Today, Dust Covers are more or less unknown. But, they have left some scars: Many people still feel irrationally guilty when exposing computer hardware to dust. The dust cover phenomenon (eighties) can be compared with the hype for equally useless ''mouse pads'' (nineties), ''protective foils'' for LCD screens (first decade of 21st century), and ''sliced bread'' (thirties).

On a more serious note, mouse pads ''were'' a boon prior to all mouses being optical because ball mouses ''do'' tend to be a PITA on polished surfaces. (Nowadays, mats are used to protect the polished surface from scratches by them); and dust covers not hindering air flow are on the wish list of any home-server admin, especially those who have experienced dust fires in long-running servers.

In the 1980, many computers were not put in living rooms, but (childrens') bedrooms, attics, basements or even workshops to control wood- or metal-working hardware. Those places tended to be prone to much dust, and the computer was only on for a few hours a day. Consumer products quite often were prone to mechanical jams due to dust, so especially in professional workshops, covers were regularly used. Industry DP was often so prohibitively expensive that home computers - quite often the C64, but the CPC offered a Z80 and CP/M as a boon - popped up in the most curious places (eg. a C64 was used to control the water supply of a German commune in the mid-80s).

Of course, dish towels ''were'' used; however, in 1987 a [[CPC 6128]] with [[GT 65]] cost DM1.500,-, not counting the [[Schneider RS-232]] interface often necessary for controlling applications, plus application-specific sensors and actors - on 2% inflation for 30 years and in €uro, that would be 1500*1,02^30 / 1,95583 = ~€1.390,-. About DM20,- for a molded dust cover that did cover the machine better really did not weigh that much considering those dimensions.

== Pictures ==

<gallery>
Image:Dust-cover-for-6128-keyboard.JPG|CPC 6128 with Dust Cover
Image:Keyboard membrane 1.jpg|Sealed 100% dust-resistant 6128 keyboard membrane
Image:Data Media Advert (CPC International 08-85, page 2).jpg|Advert
Image:Data Media Advert (CPC International 12-85, page 103).jpg|Advert
</gallery>

== Legal Status ==

There are no known laws against producing, distributing, or even using dust covers. However, users are likely to lose their precious warranty if a computer catches fire because of covering its ventilation holes after forgetting to switch off the power-supply. Fortunately, the dust cover users never realized that dilemma, otherwise they'd have probably died from a heart-attack when trying to find a solultion to the question: Risk the warranty, or risk the dust?

As users were often technically savvy, however, that dilemma did occur quite seldom (probably only in metal workshops where the metal-working machine was controlled by CPC when producing metal dust), as the computers were covered only when switched off.

Z80

2017-03-04T02:29:03Z

Dingo: /* Part numbers used in the Amstrad CPC during its lifetime */ VERY spotty. Can't find the wikisyntax to link to en.wikipedia for eZ80 etc..

[[image:Z80A.jpg|thumb|Zilog Z80A]]
Microprocessor from Zilog, which is used in the Amstrad CPC Computers. The Z80/Z80A was a very popular microprocessor, used in a great variety of home computers and appliances as far-fetched as satellites. It was even used in the Commodore C128 as a secondary processor in order to achieve [[CP/M]] compatibility.

== Description ==

The Z80 microprocessor is an 8 bit [[CPU]] with a 16 bit address bus capable of direct access to 64k of memory space. It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, access to an additional 308 instructions. The Z80 was modelled after the [[8080]] and contains the seventy-eight 8080 opcodes as a subset to its language.

Programming features include an accumulator and six 8-bit registers that can be paired as three 16-bit registers. In addition to the general registers, a stack pointer, program counter, and two index (memory pointer) registers are provided. While not in the same league as the Intel 80x86 or the [[Motorola 68000]] series, the Z80 is extremely useful for low cost control applications. One of the more useful features of the Z80 is the built-in refresh circuitry for ease of design with DRAMs.

The Z80 comes in a 40 pin DIP package. It has been manufactured in A, B, and C models, differing only in maximum clock speed. It also has been manufactured as a stand-alone microcontroller with various configurations of on-chip RAM and EPROM.

== Part numbers used in the Amstrad CPC during its lifetime ==

The Z80 CPU has been manufactured by others, and various Z80s have been used in the construction of the CPC during its lifetime.

* SGS Z8400AB1
* ST Z8400AB1
* ZILOG Z8400APS
* ZILOG Z0840004PSC

=== modern incarnatinons ===
{{stub}}

Apart from surplus/new Z80-clones that are quite easy to find, many emulations depend on software implementations of the Z80:

* The [[T80]] is a [[VHDL|VHDL]] implementation of the Z80 and Z80A, finished in 2002 on [[OpenCores|OpenCores]]
* [[arnold]] uses [[InkZ80]], written in C++ (apart from the author-designed C simulation)
* On OpenCores, there is also a [[Verilog|Verilog]] implementation of the Z80.

[[Zilog]] itself offers the [[eZ80|eZ80]] processor, a new, 50MHz design. Kits now have reached a less-than-prohibitive price range and may be available without a business.

== See also ==

* [[Z80 - undocumented opcodes]]

== Tutorials ==

== Weblinks ==

*[[Zilog]] [http://www.zilog.com]
*[http://www.z80.info/z80cs.htm Computer Systems based on Z80 Family]
*[http://en.wikipedia.org/wiki/Z80 The Z80 processor on Wikipedia]

== Opcodes ==

Check the end of the document for explanations of abbreviations used below.

=== Alfabethical list ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Mnemonic''||''Clock''||''Size''||''SZHPNC''||''Opcode''||''Description||''Notes''
|- style="background:#efefef;"
|ADC A, r||4||1||rowspan=5|*** V0 *||88 + rb||rowspan=5|Add with Carry||rowspan=5|A = A + s + CY
|- style="background:#efefef;"
|ADC A, N||7||2||CE XX
|- style="background:#efefef;"
|ADC A, (HL)||7||1||8E
|- style="background:#efefef;"
|ADC A, (IX + N)||19||3||DD 8E XX
|- style="background:#efefef;"
|ADC A, (IY + N)||19||3||FD 8E XX
|-
|ADC HL, BC||15||2||rowspan=4|**? V0 *||ED 4A||rowspan=4|Add with Carry||rowspan=4|HL = HL + ss + CY
|-
|ADC HL, DE||15||2||ED 5A
|-
|ADC HL, HL||15||2||ED 6A
|-
|ADC HL, SP||15||2||ED 7A
|- style="background:#efefef;"
|ADD A, r||4||1||rowspan=5|*** V0 *||80 + rb||rowspan=5|Add (8-bit)||rowspan=5|A = A + s
|- style="background:#efefef;"
|ADD A, N||7||2||C6 XX
|- style="background:#efefef;"
|ADD A, (HL)||7||1||86
|- style="background:#efefef;"
|ADD A, (IX + N)||19||3||DD 86 XX
|- style="background:#efefef;"
|ADD A, (IY + N)||19||3||FD 86 XX
|-
|ADD HL, BC||11||1||rowspan=4|--?- 0 *||09||rowspan=4|Add (16-bit)||rowspan=4|HL = HL + ss
|-
|ADD HL, DE||11||1||19
|-
|ADD HL, HL||11||1||29
|-
|ADD HL, SP||11||1||39
|- style="background:#efefef;"
|ADD IX, BC||15||2||rowspan=4|--?- 0 *||DD 09||rowspan=4|Add (IX register)||rowspan=4|IX = IX + pp
|- style="background:#efefef;"
|ADD IX, DE||15||2||DD 19
|- style="background:#efefef;"
|ADD IX, IX||15||2||DD 29
|- style="background:#efefef;"
|ADD IX, SP||15||2||DD 39
|-
|ADD IY, BC||15||2||rowspan=4|--?- 0 *||FD 09||rowspan=4|Add (IY register)||rowspan=4|IY = IY + rr
|-
|ADD IY, ||15||2||FD 19
|-
|ADD IY, IY||15||2||FD 29
|-
|ADD IY, SP||15||2||FD 39
|- style="background:#efefef;"
|AND r||4||1||rowspan=5|***P00||A0+rb||rowspan=5|Logical AND||rowspan=5|A=A&s
|- style="background:#efefef;"
|AND N||7||2||E6 XX
|- style="background:#efefef;"
|AND (HL)||7||1||A6
|- style="background:#efefef;"
|AND (IX+N)||19||3||DD A6 XX
|- style="background:#efefef;"
|AND (IY+N)||19||3||FD A6 XX
|-
|BIT b,r||8||2||rowspan=4|?*1?0-||CB 40+8*b+rb||rowspan=4|Test Bit||rowspan=4|m&{2^b}
|-
|BIT b,(HL)||12||2||CB 46+8*b
|-
|BIT b,(IX+N)||20||4||DD CB XX 46+8*b
|-
|BIT b,(IY+N)||20||4||FD CB XX 46+8*b
|- style="background:#efefef;"
|CALL NN||17||3||------||CD XX XX||Unconditional Call||-(SP)=PC,PC=nn
|-
|CALL C,NN||17/1||3||rowspan=8|------||DC XX XX||rowspan=8|Conditional Call||If Carry = 1
|-
|CALL NC,NN||17/1||3||D4 XX XX||If carry = 0
|-
|CALL M,NN||17/1||3||FC XX XX||If Sign = 1 (negative)
|-
|CALL P,NN||17/1||3||F4 XX XX||If Sign = 0 (positive)
|-
|CALL Z,NN||17/1||3||CC XX XX||If Zero = 1 (ans.=0)
|-
|CALL NZ,NN||17/1||3||C4 XX XX||If Zero = 0 (non-zero)
|-
|CALL PE,NN||17/1||3||EC XX XX||If Parity = 1 (even)
|-
|CALL PO,NN||17/1||3||E4 XX XX||If Parity = 0 (odd)
|- style="background:#efefef;"
|CCF||4||1||--?-0*||3F||Complement Carry Flag||CY=~CY
|-
|CP r||4||1||rowspan=5|***V1*||B8+rb||rowspan=5|Compare||rowspan=5|Compare A-s
|-
|CP N||7||2||FE XX
|-
|CP (HL)||7||1||BE
|-
|CP (IX+N)||19||3||DD BE XX
|-
|CP (IY+N)||19||3||FD BE XX
|-
|CPD||16||2||****1-||ED A9||Compare and Decrement||A-(HL),HL=HL-1,BC=BC-1
|-
|CPDR||21/1||2||****1-||ED B9||Compare, Dec., Repeat||CPD till A=(HL)or BC=0
|-
|CPI||16||2||****1-||ED A1||Compare and Increment||A-(HL),HL=HL+1,BC=BC-1
|-
|CPIR||21/1||2||****1-||ED B1||Compare, Inc., Repeat||CPI till A=(HL)or BC=0
|- style="background:#efefef;"
|CPL||4||1||--1-1-||2F||Complement||A=~A
|-
|DAA||4||1||***P-*||27||Decimal Adjust Acc.||A=BCD format (dec.)
|- style="background:#efefef;"
|DEC A||4||1||rowspan=10|***V1-||3D||rowspan=10|Decrement (8-bit)||rowspan=10|s=s-1
|-
|DEC B||4||1||05
|-
|DEC C||4||1||0D
|-
|DEC D||4||1||15
|-
|DEC E||4||1||1D
|-
|DEC H||4||1||25
|-
|DEC L||4||2||2D
|-
|DEC (HL)||11||1||35
|-
|DEC (IX+N)||23||3||DD 35 XX
|-
|DEC (IY+N)||23||3||FD 35 XX
|-
|DEC BC||6||1||rowspan=4|------||0B||rowspan=4|Decrement (16-bit)||rowspan=4|ss=ss-1
|-
|DEC DE||6||1||1B
|-
|DEC HL||6||1||2B
|-
|DEC SP||6||1||3B
|- style="background:#efefef;"
|DEC IX||10||2||rowspan=2|------||DD 2B||rowspan=2|Decrement||rowspan=2|xx=xx-1
|- style="background:#efefef;"
|DEC IY||10||2||FD 2B
|-
|DI||4||1||------||F3||Disable Interrupts||
|- style="background:#efefef;"
|DJNZ $+2||13/8||1||------||10||Dec., Jump Non-Zero||B=B-1 till B=0
|-
|EI||4||1||------||FB||Enable Interrupts||
|- style="background:#efefef;"
|EX (SP),HL||19||1||rowspan=5|------||E3||rowspan=5|Exchange||(SP)<->HL
|- style="background:#efefef;"
|EX (SP),IX||23||2||DD E3||(SP)<->xx
|- style="background:#efefef;"
|EX (SP),IY||23||2||FD E3||
|- style="background:#efefef;"
|EX AF,AF'||4||1||08||AF<->AF'
|- style="background:#efefef;"
|EX DE,HL||4||1||EB||DE<->HL
|- style="background:#efefef;"
|EXX||4||1||------||D9||Exchange||qq<->qq' (except AF)
|-
|HALT||4||1||------||76||Halt||
|- style="background:#efefef;"
|IM 0||8||2||rowspan=3|------||ED 46||rowspan=3|Interrupt Mode ||rowspan=3|(n=0,1,2)
|- style="background:#efefef;"
|IM 1||8||2||ED 56
|- style="background:#efefef;"
|IM 2||8||2||ED 5E
|-
|IN A,(N)||11||2||------||DB XX||Input||A=(n)
|-
|IN (C)||12||2||***P0-||ED 70||Input*||(Unsupported)
|-
|IN A,(C)||12||2||rowspan=7|***P0-||ED 78||rowspan=7|Input||rowspan=7|r=(C)
|-
|IN B,(C)||12||2||ED 40
|-
|IN C,(C)||12||2||ED 48
|-
|IN D,(C)||12||2||ED 50
|-
|IN E,(C)||12||2||ED 58
|-
|IN H,(C)||12||2||ED 60
|-
|IN L,(C)||12||2||ED 68
|- style="background:#efefef;"
|INC A||4||1||rowspan=7|***V0-||3C||rowspan=7|Increment (8-bit)||rowspan=7|r=r+1
|- style="background:#efefef;"
|INC B||4||1||04
|- style="background:#efefef;"
|INC C||4||1||0C
|- style="background:#efefef;"
|INC D||4||1||14
|- style="background:#efefef;"
|INC E||4||1||1C
|- style="background:#efefef;"
|INC H||4||1||24
|- style="background:#efefef;"
|INC L||4||1||2C
|-
|INC BC||6||1||rowspan=4|------||03||rowspan=4|Increment (16-bit)||rowspan=4|ss=ss+1
|-
|INC DE||6||1||13
|-
|INC HL||6||1||23
|-
|INC SP||6||1||33
|- style="background:#efefef;"
|INC IX||10||2||rowspan=2|------||DD 23||rowspan=2|Increment||rowspan=2|xx=xx+1
|- style="background:#efefef;"
|INC IY||10||2||FD 23
|-
|INC (HL)||11||1||***V0-||34||Increment (indirect)||(HL)=(HL)+1
|- style="background:#efefef;"
|INC (IX+N)||23||3||rowspan=2|***V0-||DD 34 XX||rowspan=2|Increment||rowspan=2|(xx+d)=(xx+d)+1
|- style="background:#efefef;"
|INC (IY+N)||23||3||FD 34 XX
|-
|IND||16||2||?*??1-||ED AA||Input and Decrement||(HL)=(C),HL=HL-1,B=B-1
|-
|INDR||21/1||2||?1??1-||ED BA||Input, Dec., Repeat||IND till B=0
|-
|INI||16||2||?*??1-||ED A2||Input and Increment||(HL)=(C),HL=HL+1,B=B-1
|-
|INIR||21/1||2||?1??1-||ED B2||Input, Inc., Repeat||INI till B=0
|- style="background:#efefef;"
|JP NN||10||3||rowspan=4|------||C3 XX XX||rowspan=4|Unconditional Jump||PC=nn
|- style="background:#efefef;"
|JP (HL)||4||1||E9||PC=(HL)
|- style="background:#efefef;"
|JP (IX)||8||2||DD E9||rowspan=2|PC=(xx)
|- style="background:#efefef;"
|JP (IY)||8||2||FD E9
|-
|JP C,$NN||10/1||3||rowspan=8|------||DA XX XX||rowspan=8|Conditional Jump||If Carry = 1
|-
|JP NC,$NN||10/1||3||D2 XX XX||If Carry = 0
|-
|JP M,$NN||10/1||3||FA XX XX||If Sign = 1 (negative)
|-
|JP P,$NN||10/1||3||F2 XX XX||If Sign = 0 (positive)
|-
|JP Z,$NN||10/1||3||CA XX XX||If Zero = 1 (ans.= 0)
|-
|JP NZ,$NN||10/1||3||C2 XX XX||If Zero = 0 (non-zero)
|-
|JP PE,$NN||10/1||3||EA XX XX||If Parity = 1 (even)
|-
|JP PO,$NN||10/1||3||E2 XX XX||If Parity = 0 (odd)
|- style="background:#efefef;"
|JR $N+2||12||2||------||18 XX||Relative Jump||PC=PC+e
|-
|JR C,$N+2||12/7||2||rowspan=4|------||38 XX||rowspan=4|Cond. Relative Jump||rowspan=4|If cc JR(cc=C,NC,NZ,Z)
|-
|JR NC,$N+2||12/7||2||30 XX
|-
|JR Z,$N+2||12/7||2||28 XX
|-
|JR NZ,$N+2||12/7||2||20 XX
|- style="background:#efefef;"
|LD I,A||9||2||rowspan=2|------||ED 47||rowspan=2|Load*||rowspan=2|dst=src
|- style="background:#efefef;"
|LD R,A||9||2||ED 4F
|-
|LD A,I||9||2||rowspan=2|**0*0-||ED 57||rowspan=2|Load*||rowspan=2|dst=src
|-
|LD A,R||9||2||ED 5F
|- style="background:#efefef;"
|LD A,r||4||1||rowspan=38|------||78+rb||rowspan=38|Load (8-bit)||rowspan=38|dst=src
|- style="background:#efefef;"
|LD A,N||7||2||3E XX
|- style="background:#efefef;"
|LD A,(BC)||7||1||0A
|- style="background:#efefef;"
|LD A,(DE)||7||1||1A
|- style="background:#efefef;"
|LD A,(HL)||7||1||7E
|- style="background:#efefef;"
|LD A,(IX+N)||19||3||DD 7E XX
|- style="background:#efefef;"
|LD A,(IY+N)||19||3||FD 7E XX
|- style="background:#efefef;"
|LD A,(NN)||13||3||3A XX XX
|- style="background:#efefef;"
|LD B,r||4||1||40+rb
|- style="background:#efefef;"
|LD B,N||7||2||06 XX
|- style="background:#efefef;"
|LD B,(HL)||7||1||46
|- style="background:#efefef;"
|LD B,(IX+N)||19||3||DD 46 XX
|- style="background:#efefef;"
|LD B,(IY+N)||19||3||FD 46 XX
|- style="background:#efefef;"
|LD C,r||4||1||48+rb
|- style="background:#efefef;"
|LD C,N||7||2||0E XX
|- style="background:#efefef;"
|LD C,(HL)||7||1||4E
|- style="background:#efefef;"
|LD C,(IX+N)||19||3||DD 4E XX
|- style="background:#efefef;"
|LD C,(IY+N)||19||3||FD 4E XX
|- style="background:#efefef;"
|LD D,r||4||1||50+rb
|- style="background:#efefef;"
|LD D,N||7||2||16 XX
|- style="background:#efefef;"
|LD D,(HL)||7||1||56
|- style="background:#efefef;"
|LD D,(IX+N)||19||3||DD 56 XX
|- style="background:#efefef;"
|LD D,(IY+N)||19||3||FD 56 XX
|- style="background:#efefef;"
|LD E,r||4||1||58+rb
|- style="background:#efefef;"
|LD E,N||7||2||1E XX
|- style="background:#efefef;"
|LD E,(HL)||7||1||5E
|- style="background:#efefef;"
|LD E,(IX+N)||19||3||DD 5E XX
|- style="background:#efefef;"
|LD E,(IY+N)||19||3||FD 5E XX
|- style="background:#efefef;"
|LD H,r||4||1||60+rb
|- style="background:#efefef;"
|LD H,N||7||2||26 XX
|- style="background:#efefef;"
|LD H,(HL)||7||1||66
|- style="background:#efefef;"
|LD H,(IX+N)||19||3||DD 66 XX
|- style="background:#efefef;"
|LD H,(IY+N)||19||3||FD 66 XX
|- style="background:#efefef;"
|LD L,r||4||1||68+rb
|- style="background:#efefef;"
|LD L,N||7||2||2E XX
|- style="background:#efefef;"
|LD L,(HL)||7||1||6E
|- style="background:#efefef;"
|LD L,(IX+N)||19||3||DD 6E XX
|- style="background:#efefef;"
|LD L,(IY+N)||19||3||FD 6E XX
|-
|LD BC,(NN)||20||4||rowspan=15|------||ED 4B XX XX ||rowspan=15|Load (16-bit)||rowspan=15|dst=src
|-
|LD BC,NN||10||3||01 XX XX
|-
|LD DE,(NN)||20||4||ED 5B XX XX
|-
|LD DE,NN||10||3||11 XX XX
|-
|LD HL,(NN)||20||3||2A XX XX
|-
|LD HL,NN||10||3||21 XX XX
|-
|LD SP,(NN)||20||4||ED 7B XX XX
|-
|LD SP,HL||6||1||F9
|-
|LD SP,IX||10||2||DD F9
|-
|LD SP,IY||10||2||FD F9
|-
|LD SP,NN||10||3||31 XX XX
|-
|LD IX,(NN)||20||4||DD 2A XX XX
|-
|LD IX,NN||14||4||DD 21 XX XX
|-
|LD IY,(NN)||20||4||FD 2A XX XX
|-
|LD IY,NN||14||4||FD 21 XX XX
|-
|LD (HL),r||7||1||rowspan=15|------||70+rb||rowspan=15|Load (Indirect)||rowspan=15|dst=src
|-
|LD (HL),N||10||2||36 XX
|-
|LD (BC),A||7||1||02
|-
|LD (DE),A||7||1||12
|-
|LD (NN),A||13||3||32 XX XX
|-
|LD (NN),BC||20||4||ED 43 XX XX
|-
|LD (NN),DE||20||4||ED 53 XX XX
|-
|LD (NN),HL||16||3||22 XX XX
|-
|LD (NN),IX||20||4||DD 22 XX XX
|-
|LD (NN),IY||20||4||FD 22 XX XX
|-
|LD (NN),SP||20||4||ED 73 XX XX
|-
|LD (IX+N),r||19||3||DD 70+rb XX
|-
|LD (IX+N),N||19||4||DD 36 XX XX
|-
|LD (IY+N),r||19||3||FD 70+rb XX
|-
|LD (IY+N),N||19||4||FD 36 XX XX
|-
|LDD||16||2||--0*0-||ED A8||Load and Decrement||(DE)=(HL),HL=HL-1,#
|-
|LDDR||21/1||2||--000-||ED B8||Load, Dec., Repeat||LDD till BC=0
|-
|LDI||16||2||--0*0-||ED A0||Load and Increment||(DE)=(HL),HL=HL+1,#
|-
|LDIR||21/1||2||--000-||ED B0||Load, Inc., Repeat||LDI till BC=0
|-
|NEG||8||2||***V1*||ED 44||Negate||A=-A
|-
|NOP||4||1||------||00||No Operation||
|-
|OR r||4||1||rowspan=5|***P00||B0+rb||rowspan=5|Logical inclusive OR||rowspan=5|A=Avs
|-
|OR N||7||2||F6 XX
|-
|OR (HL)||7||1||B6
|-
|OR (IX+N)||19||3||DD B6 XX
|-
|OR (IY+N)||19||3||FD B6 XX
|-
|OUT (N),A||11||2||rowspan=9|------||D3 XX||Output||(n)=A
|-
|OUT (C),0||12||2||ED 71||Output*||(Unsupported)
|-
|OUT (C),A||12||2||ED 79||rowspan=7|Output||rowspan=7|(C)=r
|-
|OUT (C),B||12||2||ED 41
|-
|OUT (C),C||12||2||ED 49
|-
|OUT (C),D||12||2||ED 51
|-
|OUT (C),E||12||2||ED 59
|-
|OUT (C),H||12||2||ED 61
|-
|OUT (C),L||12||2||ED 69
|-
|OUTD||16||2||?*??1-||ED AB||Output and Decrement||(C)=(HL),HL=HL-1,B=B-1
|-
|OTDR||21/1||2||?1??1-||ED BB||Output, Dec., Repeat||OUTD till B=0
|-
|OUTI||16||2||?*??1-||ED A3||Output and Increment||(C)=(HL),HL=HL+1,B=B-1
|-
|OTIR||21/1||2||?1??1-||ED B3||Output, Inc., Repeat||OUTI till B=0
|-
|POP AF||10||1||rowspan=4|------||F1||rowspan=4|Pop||rowspan=4|qq=(SP)+
|-
|POP BC||10||1||C1
|-
|POP DE||10||1||D1
|-
|POP HL||10||1||E1
|-
|POP IX||14||2||rowspan=2|------||DD E1||rowspan=2|Pop||rowspan=2|xx=(SP)+
|-
|POP IY||14||2||FD E1
|-
|PUSH AF||11||1||rowspan=4|------||F5||rowspan=4|Push||rowspan=4|(SP)=qq
|-
|PUSH BC||11||1||C5
|-
|PUSH DE||11||1||D5
|-
|PUSH HL||11||1||E5
|-
|PUSH IX||15||2||rowspan=2|------||DD E5||rowspan=2|Push||rowspan=2|-(SP)=xx
|-
|PUSH IY||15||2||FD E5|
|-
|RES b,r||8||2||rowspan=4|------||CB 80+8*b+rb||rowspan=4|Reset bit||rowspan=4|m=m&{~2^b}
|-
|RES b,(HL)||15||2||CB 86+8*b
|-
|RES b,(IX+N)||23||4||DD CB XX 86+8*b
|-
|RES b,(IY+N)||23||4||FD CB XX 86+8*b
|-
|RET||10||1||rowspan=9|------||C9||Return||PC=(SP)+
|-
|RET C||11/5||1||D8||rowspan=8|Conditional Return||If Carry = 1
|-
|RET NC||11/5||1||D0||If Carry = 0
|-
|RET M||11/5||1||F8||If Sign = 1 (negative)
|-
|RET P||11/5||1||F0||If Sign = 0 (positive)
|-
|RET Z||11/5||1||C8||If Zero = 1 (ans.=0)
|-
|RET NZ||11/5||1||C0||If Zero = 0 (non-zero)
|-
|RET PE||11/5||1||E8||If Parity = 1 (even)
|-
|RET PO||11/5||1||E0||If Parity = 0 (odd)
|-
|RET||10||1||------||C9||Return||PC=(SP)+
|-
|RET C||11/5||1||rowspan=8|------||D8||rowspan=8|Conditional Return||If Carry = 1
|-
|RET NC||11/5||1||D0||If Carry = 0
|-
|RET M||11/5||1||F8||If Sign = 1 (negative)
|-
|RET P||11/5||1||F0||If Sign = 0 (positive)
|-
|RET Z||11/5||1||C8||If Zero = 1 (ans.=0)
|-
|RET NZ||11/5||1||C0||If Zero = 0 (non-zero)
|-
|RET PE||11/5||1||E8||If Parity = 1 (even)
|-
|RET PO||11/5||1||E0||If Parity = 0 (odd)
|-
|RETI||14||2||------||ED 4D||Return from Interrupt||PC=(SP)+
|-
|RETN||14||2||------||ED 45||Return from NMI||PC=(SP)+
|-
|RLA||4||1||--0-0*||17||Rotate Left Acc.||A={CY,A}<-
|-
|RL r||8||2||rowspan=4|**0P0*||CB 10+rb||rowspan=4|Rotate Left||rowspan=4|m={CY,m}<-
|-
|RL (HL)||15||2||CB 16
|-
|RL (IX+N)||23||4||DD CB XX 16
|-
|RL (IY+N)||23||4||FD CB XX 16
|-
|RLCA||4||1||--0-0*||07||Rotate Left Cir. Acc.||A=A<-
|-
|RLC r||8||2||rowspan=4|**0P0*||CB 00+rb||rowspan=4|Rotate Left Circular||rowspan=4|m=m<-
|-
|RLC (HL)||15||2||CB 06
|-
|RLC (IX+N)||23||4||DD CB XX 06
|-
|RLC (IY+N)||23||4||FD CB XX 06
|-
|RLD||18||2||**0P0-||ED 6F||Rotate Left 4 bits||{A,(HL)}={A,(HL)}<- ##
|-
|RRA||4||1||--0-0*||1F||Rotate Right Acc.||A=->{CY,A}
|-
|RR r||8 ||2||rowspan=4|**0P0*||CB 18+rb||rowspan=4|Rotate Right||rowspan=4|m=->{CY,m}
|-
|RR (HL)||15||2||CB 1E
|-
|RR (IX+N)||23||4||DD CB XX 1E
|-
|RR (IY+N)||23||4||FD CB XX 1E
|-
|RRCA||4||1||--0-0*||0F||Rotate Right Cir.Acc.||A=->A
|-
|RRC r||8||2||rowspan=4|**0P0*||CB 08+rb||rowspan=4|Rotate Right Circular||rowspan=4|m=->m
|-
|RRC (HL)||15||2||CB 0E
|-
|RRC (IX+N)||23||4||DD CB XX 0E
|-
|RRC (IY+N)||23||4||FD CB XX 0E
|-
|RRD||18||2||**0P0-||ED 67||Rotate Right 4 bits||{A,(HL)}=->{A,(HL)} ##
|-
|RST 0||11||1||rowspan=8|------||C7||rowspan=8|Restart||rowspan=8|(p=0H,8H,10H,...,38H)
|-
|RST 08H||11||1||CF
|-
|RST 10H||11||1||D7
|-
|RST 18H||11||1||DF
|-
|RST 20H||11||1||E7
|-
|RST 28H||11||1||EF
|-
|RST 30H||11||1||F7
|-
|RST 38H||11||1||FF
|-
|SBC r||4||1||rowspan=5|***V1*||98+rb|| rowspan=5|Subtract with Carry|| rowspan=5|A=A-s-CY
|-
|SBC A,N||7||2||DE XX
|-
|SBC (HL)||7||1||9E
|-
|SBC A,(IX+N)||19||3||DD 9E XX
|-
|SBC A,(IY+N)||19||3||FD 9E XX
|-
|SBC HL,BC||15||2||rowspan=4|**?V1*||ED 42||rowspan=4|Subtract with Carry||rowspan=4|HL=HL-ss-CY
|-
|SBC HL,DE||15||2||ED 52
|-
|SBC HL,HL||15||2||ED 62
|-
|SBC HL,SP||15||2||ED 72
|-
|SCF||4||1||--0-01||37||Set Carry Flag||CY=1
|-
|SET b,r||8||2||rowspan=4|------||CB C0+8*b+rb||rowspan=4|Set bit||rowspan=4|m=mv{2^b}
|-
|SET b,(HL)||15||2||CB C6+8*b
|-
|SET b,(IX+N)||23||4||DD CB XX C6+8*b
|-
|SET b,(IY+N)||23||4||FD CB XX C6+8*b
|-
|SLA r||8||2||rowspan=4|**0P0*||CB 20+rb||rowspan=4|Shift Left Arithmetic||rowspan=4|m=m*2
|-
|SLA (HL)||15||2||CB 26
|-
|SLA (IX+N)||23||4||DD CB XX 26
|-
|SLA (IY+N)||23||4||FD CB XX 26
|-
|SRA r||8||2||rowspan=4|**0P0*||CB 28+rb||rowspan=4|Shift Right Arith.||rowspan=4|m=m/2
|-
|SRA (HL)||15||2||CB 2E
|-
|SRA (IX+N)||23||4||DD CB XX 2E
|-
|SRA (IY+N)||23||4||FD CB XX 2E
|-
|SLL r||8||2||rowspan=4|**0P0*||CB 30+rb||rowspan=4|Shift Left Logical*||rowspan=4|m={0,m,CY}<-
(SLL Instructions
are unsupported)
|-
|SLL (HL)||15||2||CB 36
|-
|SLL (IX+N)||23||4||DD CB XX 36
|-
|SLL (IY+N)||23||4||FD CB XX 36
|-
|SRL r||8||2||rowspan=4|**0P0*||CB 38+rb||rowspan=4|Shift Right Logical||rowspan=4|m=->{0,m,CY}
|-
|SRL (HL)||15||2||CB 3E
|-
|SRL (IX+N)||23||4||DD CB XX 3E
|-
|SRL (IY+N)||23||4||FD CB XX 3E
|-
|SUB r||4||1||rowspan=5|***V1*||90+rb||rowspan=5|Subtract||rowspan=5|A=A-s
|-
|SUB N||7||2||D6 XX
|-
|SUB (HL)||7||1||96
|-
|SUB (IX+N)||19||3||DD 96 XX
|-
|SUB (IY+N)||19||3||FD 96 XX
|-
|XOR r||4||1||rowspan=5|***P00||A8+rb||rowspan=5|Logical Exclusive OR||rowspan=5|A=Axs
|-
|XOR N||7||2||EE XX
|-
|XOR (HL)||7||1||AE
|-
|XOR (IX+N)||19||3||DD AE XX
|-
|XOR (IY+N)||19||3||FD AE XX
|}

=== Sorted by opcode ===

=== Ordered by function ===

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:CPC Internal Components]]

FPGAmstrad

2017-03-04T02:19:27Z

Dingo: /* Instruction timing */ wikilink - todo: VHDL (and -blech!!!- verilog)-codes for 'strad Chips (Z80 family, AY/YM, ...)

[[File:FPGAmstrad_cc2.jpg]]

This is a VHDL version of Amstrad CPC 6128 running on FPGA starter-kit NEXYS2 500k-gates from Digilent.
A starter-kit is a board made for learning FPGA, so it is a standard FPGA development board.

Please refer to [[http://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad MiST-board CoreDocAmstrad]] for the final user version, running on MiST-board platform.

Some games running on it : 1942 1943, 3D grand prix, A view to a kill, Action Fighter, animated strip poker, Antiriad, Arachnaphobia, Arkanoid, Arkanoid Revenge of Doh, Asphalt, Axiens, Barbarian MH, Barbarian PA, Barbarian II, Battleships, Bomb Jack I and II, Boulder Dash, Bruce Lee, Bubble Ghost, Buggy Boy, Bully's Sporting Darts, Cauldron I and II, Chase HQ, Chicken Chase, Classic Axiens, Classic Invaders, Crazy Cars, Crazy Snake, Dan Dare I II and III, Dizzy 7, Donkey Kong, Double Dragon I and II, Druid, E-Motion, Exolon, Express, Fruity Frank, Ghost'n'Goblins, Golden Axe, Gryzor, Heart Land, Hold-up, Hyper bowl, Ikari Warriors, Impossible Mission, Invasion of the Zombie Monsters, Iron Lord, Killapede, Klax64, Laser Squad, Light Force, Locomotion, Lode Runner, Macadam Bumper, Mange-Cailloux, Mario Bros, Maze Mania, P47, POP-UP, Prince of Persia, Prohibition, Realm, Rebel Star, Rick Dangerous I and II, R-Typeee, Rock Raid, Rogue, Rygar, Salamander, Sapiens, Shinobi, Sim City, Sorcery, Spectra, Spherica, Spin Dizzy, Star Ranger, Star Quake, Star Wars, Strider II, Super Ski, Superkid In Space, Tank Command, Tempest, Tetris 95, The Duct, The Empire Strikes Back, Trail Blazer, Trakers, Turbo Tortoise, Turrican I and II, Venoms, Victory Road, Vixen, WEC Le Mans, West Bank, Wizard's Lair, Word Cup Challenge, Word Series Baseball, Xevious, Xor, Zolyx.
----
[[File:ghostngoblins.jpg]]

== How to assemble it ==

'''You need:'''

*a "NEXYS2 500kgates" starter kit from Diligent [[http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2]] (1200kgates should be better for future version => in fact I choosen NEXYS4, it is same RAM inside) also in France : [[http://www.lextronic.fr/]] or in Germany : [[http://www.trenz-electronic.de/]]
*a "PMODSD" module for reading sdcard [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,513&Prod=PMOD-SD]]
*an alimentation (cause they don't give it with starter kit) [[http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,393&Cat=3#DTSWPS]]
*optionally a DIGILENT USB JTAG (normally starter kit can be programmed directly by usb, but I don't have tested this way) [[http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-USB]]
*a 4GB SDCARD (no more), I have exactly a "SDHC 4GB class4 Verbatim"
*the binary of this project (candidate 002) : source+500k-gates binary [[http://yunyunaof.free.fr/BuildYourOwnZ80Computer_amstrad_vhdl_002_repack.zip]] ; 1200k-gates binary [[http://yunyunAoF.free.fr/amstrad_switch_z80_vga_sd_orion_candidate_002_1200k_binary.zip]]
*several ROM files: OS6128.ROM BASIC1-1.ROM AMSDOS.ROM (from JavaCPC[[http://sourceforge.net/projects/javacpc/]]); MAXAM.ROM[[http://www.cpcwiki.eu/index.php/MAXAM#Download]]
*one or more DSK files : TEMPEST.DSK[[http://www.cpcgamereviews.com/t/index2.html#tempest]] ARKANOID.DSK[[http://www.cpcgamereviews.com/a/index7.html#arkanoid]] FRUITY.DSK[[http://www.cpcgamereviews.com/f/index7.html#fruity_frank]] BRUCELEE.DSK[[http://www.cpcgamereviews.com/b/index12.html#bruce_lee]] CHASEHQ.DSK[[http://www.cpcgamereviews.com/c/index4.html#chase_hq]] WIZLAIR.DSK[[http://www.cpcgamereviews.com/w/index4.html#wizards_lair]] XEVIOUS.DSK[[http://www.cpcgamereviews.com/x/index.html#xevious]] BOULDER.DSK[[http://www.cpcgamereviews.com/b/index10.html#boulder_dash]] CLASSIC_AXIENS.DSK[[http://www.cpcgamereviews.com/c/index6.html#classic_axiens]] CLASSIC_INVADERS.DSK[[http://www.cpcgamereviews.com/c/index6.html#classic_invaders]] GRYZOR.DSK[[http://www.romnation.net/srv/roms/3452/amstrad/Gryzor-UK-1987.html]] PRINCE.DSK[[http://www.cpcgamereviews.com/p/index7.html#prince_of_persia]] BUGGY.DSK[[http://www.cpcgamereviews.com/b/index13.html#buggy_boy]] TRAIL.DSK[[http://www.cpcgamereviews.com/t/index9.html#trailblazer]] P47.DSK[[http://www.cpcgamereviews.com/p/index3.html#p-47_the_freedom_fighter]] SUPER_SKI.DSK[[http://www.cpcgamereviews.com/s/index24.html#super_ski]] ACTION_FIGHTER.DSK[[http://www.cpcgamereviews.com/a/index.html#action_fighter]]

A package that contains minimum set of ROM and DSK for filling simply sdcard [[http://yunyunAoF.free.fr/OS6128_BASIC1-1_AMSDOS_MAXAM.zip]] (OS6128, BASIC1-1, AMSDOS, MAXAM)

 '''You have to:'''

*program FPGA with the binary file "amstrad_switch_z80_vga_sd.bit" of this project, for it I use Digilent Adept software and my USB JTAG cable
*format your 4GB SDCARD in FAT32 4096 byte allocation size
*copy ROM and DSK on SDCARD
*plug PMODSD on slot JC1 of starter kit, and set all 8 switches to 0
*plug VGA, and turn on starter kit

[[File:FPGAmstrad_minimal_plug.jpg]]

'''You can:'''

*plug a PS/2 keyboard, and type "cat"
*increment switch to select another disk at boot, if screen became RED, it's that binary value done by switches is too big, leds are doing a small animation when a disk is correctly loaded
*plug principal joystick on slot JB1 (Vcc 3.3v is common)
*plug another joystick on slot JA1 (Vcc 3.3v is common)
*plug a jack on slot JD1, one at upper GND plug, and second wire at next plug, just at left of it (if it was 3.3v Vcc, choose the right one instead)

[[File:FPGAmstrad_sound_plug.jpg]]

Wires are plugs at upper part of pmod D.

From bottom to upper: [nothing: Vcc 3.3v] [blue: GND] [red: sound]

Sure you can connect a jack...

And two joysticks.
On pmod B: bottom is (both) 3.3v, so joystick's common, next is (both) GND (not used), and others are joystick connections, to test manually :)

[[File:FPGAmstrad.jpg]]

----
==Video==
http://www.youtube.com/watch?v=Z8FB_eIy8LY
----

== Last news about this project ==
In September 2016, FPGAmstrad does use external RAM as RAM+VRAM, no more "LowerVRAM/UpperVRAM" switches to select in OSD menu.

[[File:Fpgamstrad jocker batdemo.png|thumbnail|Using 64K of VRAM...]]

In August 2016, FPGAmstrad does pass some arnoldemu's testbench : PPI PSG CPCTEST.

In February 2016, FPGAmstrad has a TV mode (original signal)

In September 2016, FPGAmstrad has write access on both disk drives, and can change dsk.

In March 2015, FPGAmstrad is stable on MiST-board, please refer to [http://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad MiST-board CoreDocAmstrad] and [http://code.google.com/p/mist-board/source/browse/#svn/trunk/bin/cores/amstrad mist-board amstrad bin core]

In December 2014, FPGAmstrad is stable on NEXYS4, WIP, BOOTLOADER improved, VRAM improved (with BORDER colors !), RAM relaxed, no more timeout in keyboard key-press, Ghouls 'n' Ghosts, Macadam, a lot more to do. 14% of platform is used.

In November 2014, I bought MIST board, with two pro joysticks.

In September 2014, I bought NEXYS4, more powerfull than NEXYS2, with same external RAM, internal mini-sd, no PS/2 (it is a pmod option)... I have some patchs to make (MSB FAT32 offset). I would like to make a USB snifer also with it (usb to ethernet (wireshark))
----

== Contact ==

I am Freemac, my IRL name is Renaud Hélias.

You can contact me by mail to renaudhelias @t gmail d0t com, if you have questions about assembling this project.

Follow me on [http://plus.google.com/u/0/102709294612470681079 my google plus account]!

----

== Tests done ==

Great games that are running properly are listed at top of page.

===On MiST-board CoreAmstrad version===
Games that doesn't run are :
*'''ACPC_logon_system.dsk''': text scrolling lag. This demo will be used for horizontal ink calibration (when I’ll buy a luxurious FPGA platform... I need in fact 224KB of internal RAM to do it), and CRTC overcounts.
*'''commando.dsk''': pixels that should be deleted are not deleted (only VRAM &C000-FFFF seems used)
*'''split ink demo.dsk''': (from cpcrulez) : may help about ink raster calibration.
*'''Sultan's Maze.dsk''': does need the right part of keyboard (F0-F9 are used for directions in this game)
*'''Orion Primes.dsk''': does display "secteurs entrelacés" - "vérifiez votre copie", a FDC problem.
*'''Batman_Forever.dsk''': some problem during flying chip demo part, and several rupture showing ghost lines around Vcc=0.
*'''30YMD.dsk''': in Benediction demo, at bottom some time you see some ghosts of central animation (too many HSync per screen ?)
*'''arkanoid2.dsk''': don't run in r005.8.13, but fine in r005.8.13e (experimental fork)
*'''trailblazer.dsk''': no more "raster" problem since r005.5, it's now perfect ! Palette heuristic offset (done for unlocking Batman Forever Demo) has a small effect in left (squares are not separated by a black line in first column)
*'''imperial_mahjong.dsk''': modern EXA/EXA2 resolution not passing my color pallet heuristic :p
*'''rtypeee.dsk''': at begin of presentation, a draw of "jack plug" is done in a strange video mode, more than 200 pixels of height !, see [http://cpc.sylvestre.org/musee/musee_flipping_lace.html flipping lace]
*'''S&Koh.dsk''': LOGON SYSTEM, black screen in r005.8.4... damn
*'''Pinball_Dreams__PREVIEW.DSK''': Does run in experimental/ versions r005.8.9.2 and r005.9.11e (experimental forked version of r005.9.11 using flag FPGAmstrad_amstrad_motherboard.vhdl.HACK_Z80=false). Does freeze in !experimental versions when background music is special (not long classic background music) and you press two buttons (left/right flipper keys) at the same time.

'''Arkanoid.dsk''' stars use rupture address (changing address several time during display of one image), it is now supported on "candidate 001" version of FPGAmstrad. Run better in r005.9.11e than in r005.9.11.

'''Gryzor''' and '''Prince of Percia''' use rupture ink/mode (changing ink and mode during display of one image), it is now supported on "candidate 002" version of FPGAmstrad

Gryzor is really sensitive to Amstrad general stability : do press esc at start menu does activate music during game, if no music, FPGAmstrad is in an instable version (last known stable version r003.8)

'''Crazycars2.dsk''' first car image use 32KB of VRAM, it is now supported on "candidate 001" version of FPGAmstrad.

'''Ghouls'n'Ghost.dsk''' / '''Ecole.dsk''' does need RAM write when writing in ROM (RAM is beside ROM, hard to emulate with asynchronous SDRAM controler, MiST does use a hacked synchronous RAM done for that)

'''moktar.dsk''' / '''super_cauldron.dsk''' does run fine since r004.8.1.1.

'''CPC Aventure''' does run fine since r005.2 (message about turning disk now displayed)

'''prehistorik.dsk''' does run fine since r005.2 (key can now be pressed in intro demo)

'''Sim City''' and '''Hero Quest''' run fine since r005.2 (it was about "key always pressed"), but does need a hard boot (not quick reset keyboard key), certainly a small problem of component init state.

A lot of demos don't pass in NEXYS4 FPGAmstrad's version (I need to implement back the SDRAM hacked in MiST board FPGAmstrad version). [http://cpcrulez.fr/Scene_Demos/index.php CPCRULES demos] is a cool ressource as it contains simple dsk formats.

'''crazycar.dsk''' does use lowerVRAM=00 (&0000-3FFF and &C000-FFFF area for VRAM)

'''crazycar2.dsk''' does use lowerVRAM=10 (&8000-BFFF and &C000-FFFF area for VRAM) while overscan presentation, and lowerVRAM=00 (&0000-3FFF and &C000-FFFF area for VRAM) during play. Run fine since r005.7

'''buggyboy.dsk''': I found one dsk running correctly and another not : problem on this last one is about turning left/right effect : the car continues straight (it seems a prototype bad version)

'''superski.dsk''' : don't forget to disable autofire, in jump, do press fire+up or down.

'''protext.rom''': All right since r004 (before, in edit mode, if I pressed continuously one key, it did write ten letter and freeze/crash. Do note that a number is incremented in live at top right, so this is a complex software, good for keyboard vector stability tests)

'''atomdriv.dsk''': unlocked since r004.5 (the game and music did freeze (ROM unplugged shall return xFF))

'''rtypeee.dsk''': unlocked since r004.7. Does use special read FDC cmd, with BOT different of EOT (begin of track/end of track), so reading several 512 bytes blocks in one FDC command only.

'''Arkanoid Revenge of Doh''' and '''Asphalt''' are two games that doesn't support ROM extensions : Doh starts to show small bad layers, and Asphalt does crash and reset before main menu... if you add another gadget ROM.

'''antiriad.dsk''': no keyboard/joystick between r004.5 and r004.7. By adding pull-up at r004.5 I lost this game, by implementing a better PPI in r004.8 this game run fine : Antiriad is back !

'''-circles.dsk''': this demo freeze does since r004.8 (PPI border effect ?) and is back since r005.5, it was nice to calibrate SOUND clock : I did generate 8 candidates of synchronizing this clock (1MHz from 4MHz : 1100 0110 0011 1001, and 0.5 deltas : 1100i, 0110i, 0011i, 1001i), only one does not freeze -circles... so I release r005.5 candidate. This demo is a great one around calibrating Yamaha clock.

'''Nigel Mansell's Grand Prix.dsk''': Only one race track seems ok : Monaco (Brazil track does not start). Unclassified : this disk bug also with other emulators, certainly a bad dsk dump here, TOSEC version of Nigel Mansell does run fine (but some legendary traces of "SK bit purpose" needed by here (in FDC, setting SK does jump deleted disk tracks), perhaps to investigate)

'''saboteur2.dsk''': run fine since r005.5 (nice music and then freeze problem), it was about Yamaha clock generator (generated by Gatearray, versus WAIT_n added in short Z80 instruction to let them during all 4 clocks (Z80 in Amstrad does use 4T or 8T instructions (WAIT_n does insert missing T)). Does freeze at welcome since r005.8.7. Back since r005.8.10.

'''tetris95.dsk''' : bad in r005.8.9.2 (4 beep while breaking 3 lines (instead of 3 beep while breaking 3 lines), was correct in r005.8.4. Back since r005.8.10.

{| class="wikitable"
|-
! Game !! Welcome !! Title !! Game
|-
| CrazyCar2 || || 1011 || 0011
|-
| One || || 0111 || 0011
|-
| Scarabus || || 0111 || 0011
|-
| Ace || || || 0010
|-
| Tintin || 0111 || 1011 || 0111
|-
| Devil's Crown || || 0001 || 0011
|-
| Mach 3 || 0111 || 0111 || 0110
|-
| Paranoia (1994) || || 1011 || 0001
|-
| World Class Rugby || 1011 || 0001 || 0001
|-
| Miam Cobra || || || 1001
|-
| Galivan || || || 0001
|}

'''XOR.dsk''' does use lowerVRAM=01 (&4000-7FFF and &C000-FFFF area for VRAM)

TODO :

*To test also : [http://www.speccy.pl/archive/prod.php?id=335 Unlimited Bobs (Dr.Piotr).dsk] demo.

== Effort done ==

=== Instruction timing ===
I tested instruction timing of [[T80]] compare to instruction timing of JavaCPC emulator. I deduce synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in order to have a multiple of 4 Tstates per instruction. I deduce also one WAIT_n inserted during MEM_WR operation (yes I log testbench T80, I’m crazy)

I just made a test bench log of T80 (log of instruction's M1, and first M1 coming after knowing that I send a lot of NOP after my instruction), and compare it to a JavaCPC timing array. Some instructions was not tested (interrupt wait, and special timing (instructions with change timing)), but all others passed correctly.

==== Instruction timing : currently in r008.5.14 ====
In GA, I do use begin of edge for IO_ACK instead of state.

M1 reached same time of IO_ACK are ignored (not M1) in WAIT_n generator.

MEM_WR has an OSD menu choice to switch between "quick" and "slow", "slow" mode does insert ONE WAIT_n during detection of MEM_WR. This switch exists because somes games are running in "slow" mode and others in "quick" mode.

==== Instruction timing : talk about r008.5.14 ====

In fact it exists several instruction making MEM_wr, and adding each one ONE WAIT_n does result in different case of synchronization.

[http://www.cpcwiki.eu/forum/emulators/cpc-z80-timing/ CPC Z80 timing]

If it's about managing GA reading pixels, perhaps not only M1 signal are synchronized but also the MEM_RD and MEM_WR accesses at another offset.

[http://amstrad.eu/modules/newbb/viewtopic.php?post_id=24592 Timings instructions Z80 sur CPC]

If interruption r52 is regular, even while making a continues MEM_WR, interruption (int<='1') shall be taken into account above WAIT_n insertions ?

In Z80 sequence diagram, an IO_ACK(+M1) is preceded by M1 (single)

cpctest.dsk -Timing Instruction- is different while using mode "MEM_WR=slow" and "MEM_WR=quick". Strangly better using "MEM_WR=quick".

Current version is using "Z80_HACK=true" (parameter set during compilation), that shunt Z80.WAIT_n entry, Z80.clock is slow down during theses WAIT_n. It's the only current way I succeed in slowing down enough Timing Instruction for unlocking Saboteur 2 game.

Key games here are : Saboteur 2 (run fine with "MEM_WR=slow", does freeze with "MEM_WR=quick") and Arkanoid II (run fine with "MEM_WR=quick", too slow using "MEM_WR=slow")

[http://www.cpcwiki.eu/forum/programming/cpc-z80-commands-and-how-long-they-take/40/ CPC Z80 Commands and how long they take...]

=== Test of a real Zilog 80 ===
[[File:Z80fx2bb.jpg]]
Code name : Z80fx2bb, real Z80@2MHz (instead of 4MHz) on fx2bb extension card.

For it I plug all wires simply from 1 to 40. Some wires are cut, some are Vcc, others GND. Z80 output are directly connected, Z80 input are pull-up with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v do output 3.3v.

In fact the only difference between T80 of opencore and real Z80 is that T80 run on rising_edge, and Z80 run during low state. Test past with little modification of sequencer forcing it do nothing during low state of z80, resulting a downclock (memory is too overclocked with this sequencer modification), perhaps using buffer on address bus and data bus could solve this detail... but as it runs for me it is not a problem.

==== TODO : Z80 testbench ====

[http://www.cpc-power.com/index.php?page=detail&num=12883 CPC-Power Z80 FULL TEST (UK) (2012) - UTILITAIRE]

Some errors detected in r005.8.4 (test done by Philippe D.)

[http://www.winape.net/download/plustest.zip WinAPE plustest.zip (including Instruction and Interrupt timing tests)]

=== Alignment of HSYNC Interrupt ===
Interrupt are respected since version "candidate 001" of FPGAmstrad.

[[File:JavaCPC_running_norecess.jpg]]

JavaCPC running norecess's "using-interrupts" code [[http://norecess.cpcscene.net/using-interrupts.html]]

It could be interesting to test this asm code on next version of FPGAmstrad.
==== TODO : arnoldemu testbench - cpctest ====
[http://www.cpcwiki.eu/forum/emulators/amstrad-cpc-%27acid%27-test/ forum : amstrad cpc "acid" test] => ''I have uploaded updated tests : [http://cpctech.cpc-live.com/test.zip http://cpctech.cpc-live.com/test.zip]''

Tests done here : ppi/psg/cpctest.

[[File:arnoldemu_testbench_CPCTEST-r005-6.png]]

In r005.6, I reach successfully some arnoldemu tests to calibrate more efficiently HSYNC interrupt : ppi.bin, psg.bin, cpctest.bin.

Games unlocked by r005.6 : Sigma7, Pac-land, Golden Tail.

In r005.8, Prehistorik is running fine.

In r005.8.4, arnoldemu testbench "cpctest" does fail :/

In r005.8.7, arnoldemu testbench "cpctest" is OK

In r005.8.14 version, using default mode "MEM_wr:quick", is OK. And Prehistorik II is running fine.

===== TODO : arnoldemu testbench - crtctest =====
Adding choice of CRTC 0 or 1 on OSD, and passing this test could be great.

=== ram_palette ===
VRAM contains 800x300 amstrad pixels (VZoom x2), displayed VGA 800x600@72Hz with fix regular border at 768×576 and fix inside border at 768×544.

* simple_GateArrayInterrupt.vhd (GA to VRAM) parameters : VRAM_Hoffset/VRAM_Voffset
* aZRaEL_vram2vgaAmstradMiaow.vhd (VRAM to VGA) parameters : H_BEGIN/H_END/V_BEGIN/V_END (theorical fixed values)
To calibrate : VRAM_Hoffset++ does offset one char left. VRAM_Voffset++ does offset one line up. On display H_BEGIN does begin to scan lines of VRAM. But V_BEGIN does not enter in consideration here : vertical=0 does begin to scan columns of VRAM.

In original CPC, top border has 1/2 char more than bottom border. I used Batman Forever default welcome/calibration screen to calibrate VRAM offsets.

RAM_palette contains the ink list and the mode for each line of VRAM, sampled at horizontal middle of 800x600 screen, and used at begin of each line.

=== Sniffing of a real Amstrad ===
[[File: cpc_plus_m1.jpg]]
Code name: Raptor

I listen to some wires of my Amstrad CPC 6128 plus, but I can't access VSYNC/HSYNC output of CRTC, so I have to buy another model in order to do this test. In fact you can listen at clock of Amstrad and transmit it to FPGA DCM component, resulting a accelerated clock sequence, that's it, with FPGA DCM you can overclock output Amstrad clock signal in order to insert more operations, I use this tip for listening signals and save them inside starter kit asynchronous RAM (write, stop write, write, stop write... I’m a perfectionist paranoid...)

You can power Amstrad CPC using extension port, applying 5v. By doing it, power down button of Amstrad doesn’t run. Using this way you reach a common 5v power between starter-kit and Amstrad. I connected wires from extension port directly to FPGA, as they are used just for listening.

=== ROM and RAM extension ===

In r004, you have more RAM +512KB, and you can add ROMs.
* LowerROM has .eZZ file extension
* UpperROM has .e00 ot eFF file extension (hexa)

In r005.4, I add another UpperROM set : .f00 to .fFF file extension (hexa). If you press "space" during a reset_key ("page up" key), upperROM files used range from .f00 to .fFF instead of ranging from .e00 to .eFF. LowerROM .eZZ file extension is still used in both case.

=== Sound output ===

==== PWM ====

Using a simple PWM, data is entered at a certain speed, the PWM clock speed.

If you simulate a constant PWM output signal at middle range of voltage (state just between 0V and 5V : 2.5V), it results an alternance of 0V and 5V, that result in a noise sound. In Arkanoid, this defect make some continues sounds instead of silents...

My idea is generating a sound having a frequency upper than dog ultra sound, while I want to simulate a constant 2.5V.

For this I do use two clocks entries in my PWM : one about data entry, and another about algorithm execution.

This result a high quality sound output (in addition to this nice [http://www.fpgaarcade.com/library.htm Yamaha sound chip from fpgaarcade])

==== Stereo sound output ====
[[File:STarKos1 21 FPGAmstrad_800x600.png|none|STarKos 1.21 running on FPGAmstrad]]

Sound chip was modified in order to get channel A+B at left, and channel B+C at right.
It was tested OK using [http://www.grimware.org/doku.php/documentations/software/starkos/start STarKos 1.21] sound tracker (track "Carpet")

=== DONE: Another disk selector ===

In first version of FPGAmstrad (NEXYS2) I used switches for disk selection. As final FPGA platform doesn't have any switches set, I have to add an BASIC instruction for it, something like "OUT &CAFE,disk_number" could be fine.

Since FPGAmstrad in NEXYS4, disk selection is done from keyboard, using "OUT &CAFE,disk_number" instruction.
A reset key was added also.
"PRINT INP(&CAFE)" does print current disk selected number.

==== DONE : A advanced dsk drive ====

Done on r004, I added also a second Drive in order to copy easily files from one disk to another.

Irregular sector size ok.

You just have to select Drive A or B from OSD before selecting another dsk file.

Write is done directly on sdcard dsk file, so you can save games, and write texts...

You can now change disk without reset. And then play games using several disks.

[http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/fdc-floppy-t80ds-detection/ CPCWiki forum - Amstrad CPC hardware - FDC floppy t80ds detection] : talk about FDC in MiST-board CoreAmstrad.

==== DONE : A advanced FDC (with write access and more) ====
Since r004 "mecashark", the FDC implementation has write access !

==== UNDONE : FAT32 fragmented files support ====
Since advanced FDC, dsk files have to be defragmented. Only ROMs are safe with a not defragemented sdcard...

==== TODO : SNAP DSK ====
Add an option in OSD MENU : "SNAP DSK". Does create a copy of current disk in current drive into "SNAP[number].DSK". Heuristic for number : file count (at boot, incremented at each snap dsk done)

=== TODO : A X/Y input ===

I want to work also on screen-pen entry, is there a manner to detect an analog X/Y as pen or gun ? YES : [http://java.cpc-live.com/gx4000.php Markus Hohmann] does it, he implements the lightgun on JavaCPC-GX4000 using mouse :)

http://cpcrulez.fr/hardware-pistolet-magnum_light_phaser_ACPC.htm

register 11,12 and 13 ?

=== DONE: A SCART output ===

In order to plug FPGAmstrad on TV, and help debugging. And also to test a simple scan-doubler.

r005c17 : experimental version, original signal TV output is running fine, with OSD menu. Have to add a flag in mist.ini instead of using OSD menu.
scan-doubler doesn't run ok in mode 2, and has strange offset with Arkanoid (vertical display games), so it unvalidated : only original TV output will be added to r004 in r005.

r005 : VGA 60H/TV 50Hz.

==== TODO : A SCART output with border ====

Original output signal has no border, I have to implement the original border in TV mode.

Priority: HIGH! (asked by Markus Hohmann)

==== DONE : move SCART parameter into mist.ini ====
Doing like in other cores : do use the global "scandoubler" option in mist.ini to switch between VGA and TV mode.

==== TODO : mix SCART H and V sync into HV sync (sort of C sync) ====
[http://github.com/mist-devel/mist-binaries/issues/35 Amstrad CPC core · Issue #35 · mist-devel-mist-binaries · GitHub] :
SCART TVs expect a composite sync. The VGAs vsync is connected the SCART pin used to detect a RGB signal and is constantly driven high. A TV will not cope with a video signal with separate H and V sync.
Bu tit's usually sufficient to xor hsync and vsync to get a csync acceptable for many TVs.
So something like this
Vsync=1;
Hsync=old_Vsync xor old_Hsync;
See if another core already succeed in generating a 50Hz SCART 15khz RGBS output...

=== DONE : CRTC1 ===
r004.8 : a better CRTC/Gateway implementation, following better JEmu (JavaCPC) one... but it is a CRTC1 (but a better ONE)
Some bugs came from PPI also (keyboard bugs in particular), solved in r004.8

==== DONE : CRTC0 ====
CRTC0 seems the best one, some demo does cry when detecting a poor CRTC1 (CRTC1 seem a low cost version of CRTC0). I have to implement a CRTC0 instead of my current CRTC1...

In fact CRTC1 is the best one. CRTC2 is the low cost version. CRTC0 did appears before CRTC1.

Done in r005.8.14. Detected as CRTC0 by WakeUp! - "Enjoy the show" message displayed.

==== DONE : CRTC1 detection ====
I don't remember exactly, but in r005.8.4, one of "Midline Process"/"From Scratch"/"Pheelone" demo does crash due to a "CRTC1 needed" message : my CRTC1 seems not detected as a true CRTC1... If's "From Scratch" that does display this message in fact.

Done in r005.8.14 : Still Rising (Vanity) demo can be launched, better using "MEM_WR:slow" mode.

[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]

=== TODO : Interlaced scanlines ===

Interlaced scanline is an effect existing in CRTC (register R8) used by Wolfenstrad demo
Seen also at begin of '''R-Typeee.dsk''' ("stereo soundtrack" message's picture), and seem also used in a lot of recent demos as "flipping lace" effect.

Scanline is also used just at begin of '''Pinball_Dreams__PREVIEW.DSK''' (eagle draw) - in fact I've got a doubt here, it seems more about a problem of HSYNC edge choice of alignement here.

[http://cpc.sylvestre.org/technique/technique_identifier_crtc.html Les Sucres en Morceaux - Amstrad CPC - Identifier les CRTC]
OUT &BC00,8
OUT &BD00,3

[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
L'écran passe en 100Hz, les registres 4 et 7 doivent être doublés pour retomber sur 50Hz

=== DONE : Scanlines ===
Here effect is about simulating CRT (not CRTC.R8) original screen. There is several way to implement it.
Here, truly one line out of two is 1/2 darker. By visual effect this result in "a thin full black horizontal line".

[[File:FGPAmstrad cc withoutScanlines.png|thumbnail]]
[[File:FGPAmstrad cc withScanlines.png|thumbnail]]

=== DONE : Monochrome option ===
Add an option to turn screen into green monochrome mode (in mode TV and in mode VGA)

done in r005.8.9.2 (Soleil Vert demo)
[[File:Soleil vert CoreAmstrad.png|thumbnail]]

[http://cpc.sylvestre.org/technique/technique_coul1.html Les Sucres en Morceaux - Couleurs - 1 - Les couleurs du CPC]

==== TODO : Monochrome OSD ====

Could be great having the OSD in monochrome when monochrome is selected and scanlined when scanline is selected

=== TODO : Ethernet ===
Integration of "ethernec.v".

=== TODO : arnoldemu's testbench fdctest ===
arnoldemu's testbench to pass : test/fdctest/fdctest/fdctest.dsk

Contains the DFC "SK bit" test.

Have also to fix theses "Bad Command" responses from fdc (it seems that when you don't reach a track, you have to send back the current track instead of this "Bad Command" signal). Test : 30YMD demo, "disk change" message not running correctly, "another disk inserted" is not detected in this demo.

=== TODO : github migration ===
Have to migrate source-code repository from renaudhelias github to mist-devel github. And also update each url in head of source-code files...

=== PPI ===
Problematic here : Keyboard detection versus VSYNC signal versus interrupt cycle.

==== DONE : A better PIO ====

I'm looking after a great implementation of PIO, in original schematic of Amstrad, keyboard (output, not input) is mapped behind Yahama chip behind PIO.
In some emulators, keyboard is mapped directly behind PIO.
In original schematic, PIO is the only one component having a low state reset (0), I think that imply a 0 value as state init of internal components variable. Data bus of Z80 seems having a pull-up state (read 1 when nothing is plugged), for example a unplugged ROM does respond xFF in data-bus.

Update : arnoldemu's testbench PPI passed.

==== TODO : Yamaha clock ====
In r005.5 I build the Yamaha clock from GA. Unlocking "Saboteur 2" game.

Yamaha clock is generated by GA.

Yamaha clock (YM2149_linmix_AmstradStereo.vhd) is used only for "sound algorithm", not for setting/getting registers (registers are set using "BDIR BC2 BC1" wires), so I have to overclock the setting/getting register clock to simulate the original behaviour...
==== DONE : PPI clock ====
PPI in original schematic does not have clock ! So I have to overclock this one to simulate the original behaviour...

Overclocked at 16MHz.

=== TODO : a better border heuristic ===
Using winape testbench (plustest), test 2 does show somes problems while border does go out of screen, negative border does hide line itself.

----

== Agile method ==

This project results of a experiment applying Agile method.
Finally this project has taken 5 months. The result is a standalone platform that can run several games of Amstrad.
Normally, I had to dedicate 2 months on this project, but as result was so great, I continue to a standalone and better version.

This project was done for my father birthday, so sorry that I can't deliver it yet :^)

One day perhaps I'll write one book, or write a lot of wiki page by there, presenting step by step this adventure :)

But I want really to validate project before doing it. So it will stand a few I think.

=== Minimal Amstrad Architecture: Build your own Z80 Amstrad Computer ===
I explain here my first great experiment, having Amstrad saying hello :)
==== First schematic: Z80+RAM+ROM ====

Z80 can address from 0x0000 to 0xFFFF.

RAM is from 0x0000 to 0xFFFF.

You have lower and upper ROM, so starting at address 0x0000 you put OS464.ROM, and at address xC000 you put BASIC1-0.ROM.

*When Z80 do READ MEMORY, you read ROM
*When Z80 do WRITE MEMORY, you write RAM
*When Z80 do WRITE IO, you do nothing
*When Z80 do READ IO, you response it DATA=0x00

When you run this schematic on FPGA, RAM changes!

==== Second schematic RAM+VGA ====
With JavaCPC, when you snapshoot, and hex edit result file, you see RAM content starting at a certain address.

Do "paper 2", "cls" on JavaCPC, the screen became RED, and then save a snapshoot, you can see that last part (from 0xC000 to 0xFFFF) had change from a lot of 0x00 into a lot of 0xFF

So last part of RAM is used for video (it's shown on Quasar [[http://quasar.cpcscene.com/doku.php]] and other legend websites...)

For making my VGA module, I take a look at UNIX "modeline" command that give us all timing for VGA signals, and it run :)

After having a VGA module displaying a RED screen (yeah!), I made it scanning last part of RAM (from 0xC000 to 0xFFFF), and I solved the puzzle.

[[File:crtc_puzzle.jpg]]

RAM contain lines of 0xFF, each finishing by 0x00, but lines are not in great order

==== Third schematic Z80+ROM+RAM+VGA ====

Goal is: RAM empty at startup, VGA displays hello after run.

So you put the two last schematics together and tadam... got a problem.

The problem is that two components are accessing RAM in the same time: the Z80 and the VGA, so you had to make a sequencer. A sequencer is simply a counter fed by a clock: 00, 01, 10, 11. And you manage work task like this:

*00 RAM WRITE start from Z80
*01 RAM WRITE end from Z80
*10 RAM READ start from VGA
*11 RAM READ end from VGA

You plug sequencer(1) on z80 clock and not(sequencer(1)) on VGA...but another problem appears: VGA uses 25MHz speed for scanning RAM. So Z80 has to use same speed xD

To solve this problem you can use a special RAM done for this problem, a RAM that you can WRITE at a certain speed, and READ at another speed, this magic component is called '''ramb16_s16_s16'''. Note that they have no problem to write simultaneously on two RAM components, so that you can dump video RAM content using starter kit RAM, and you can display VGA using FPGA internal '''ramb16_s16_s16''' RAM.

[[File:build_your_own_z80_amstrad_computer.jpg]]

==== First and Second schematics video ====
http://www.youtube.com/watch?v=9Y-RvYMxnbE

Here I do program FPGA with a serial port RAM filler (homemade), and then I do upload ROMs (sooo long, you can show several blue progress bars), and then I do program FPGA first schematic : Z80+RAM+ROM, executing it, and then I do program second schematic : VGA is plugged on FPGA platform and does display "Ready".

Just about the "RAM filler", filling a RAM with data is perhaps the more important thing* about using FPGA platforms, do just remember that a RAM does keep its content as long as voltage is entered on it. So you can program FPGA without erasing RAM content. So you can program three FPGA programs : one for filling RAM, one for running a program using RAM, one for dumping RAM. Here I did use a serial transmit, but in fact, in last versions of FPGAmstrad, I do use a SDCARD with a homemade bootloader (filling RAM from SDCARD content)

I did use also Mock components, in first version of FPGAmstrad, FPGA platforms was too small, so I could have FPGAmstrad only with cool sound and low graphics, or else FPGAmstrad with cool graphics and no sound. Both using 100% of this old FPGA platform. A Mock component is a fake component, an empty one, just telling back "I'm OK, please thrust me I do exist" to others components trying to communicate with me (it's a entity with same in out ports as original but using constant output values)

* * [[http://cpcwiki.eu/index.php/FPGAmstrad#RAM_dump #RAM_dump]]

==== Third schematic Z80+ROM+RAM+VGA video ====
http://www.youtube.com/watch?v=w_wifI-bRJc

=== The three main FPGAmstrad schematics ===
==== FPGAmstrad_bootloader_sd schematic ====
After having a first running Amstrad, I had to turn it into as standalone version. In fact before this step Amstrad ROM was put into RAM using serial port ([[#RAM_dump]]), it was slow, and Amstrad ROM was lost when I unplug electricity.

Bootloader FAT32 SDCARD is the only component playing with sdcard. Its tasks, all launched at boot, are:

- deploying ROM file on physical RAM

- deploying Nth DSK file on physical RAM, N being the binary number selected by 8 switches

===== State machine =====
Both component of Bootloader, it is to say SPI_MASTER and SDRAM_FAT32_LOADER components, does use several state-machine, one state-machine per process, each process communicating with another one using "MASTER/SLAVE" : the master state-machine does ask a slave to do something, and slave does notify master when its task is finished.

Theses state-machine does use led debug : an integer contain the state of state machine, and this integer is displayed on 8 leds so you know where you are, it's for that I add several crash state in order to understand why and where component crash. In MiST-board, this is displayed on the five 7-segment I added in OSD, I add also a input in order to select one or another state machine.

==== FPGAmstrad_amstrad_video schematic ====

===== VGA =====

The main component of this schematic is called aZRaEL_vram2vgaAmstradMiaow, due to my first experimentation about drawing a picture on VGA screen.

VGA display component use same parameters than unix '''modeline''' command, that's all you need, with that parameters you can display something on VGA at the frequency/resolution you choose.

[[File:aZRaEL_RAM_test_ok_zoom4_decal64_inv.jpg]]

[[File:aZRaEL_test_vram2vga.jpg]]

===== VRAM to VGA =====
RAM and VGA does not use the same frequency. I add between them a magical VRAM having two clock entries and solving this problem automatically.

The magic RAM in FPGA, getting two clock entries, is not as magical as I was thinking : in fact it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compiling.

If you seem interested about strange clocks generated during last step of FPGA compile, do look after "time constraints file" and "timing closure".

==== FPGAmstrad_amstrad_motherboard schematic ====
This is the core part of FPGAmstrad, it does represent the motherboard schematic of Amstrad, it was aligned to JavaCPC source code.

I fill this schematic component per component, comparing behaviour to JavaCPC components.

JavaCPC is developed in Java, and Java is so cool (Java is better computer language ever, and VHDL is better FPGA language ever =P)

I tickle JavaCPC in order to compare its components to my ones.
===== Emulator Architecture =====
while (¡stop_emulation)
{
executeCPU(cycles_to_execute);
generateInterrupts();
emulateGraphics();
emulateSound();
emulateOtherSoftware();
timeSincronization();
}
Figura 2. Basic Emulator Algorithm.
Extracted from the book [[http://www.scribd.com/doc/53571848/27/Appendix-A-Space-Invaders-i8080-tutorial]],

Using this way, emulators reach a better running time. They don't need to implement the system-bus architecture[[http://en.wikipedia.org/wiki/System_bus]] (CONTROL DATA ADDRESS) crossing Von Neumann architecture[[http://en.wikipedia.org/wiki/John_von_Neumann]] (CU ALU MEM IO).

===== Component Architecture =====

Java is an object language, so having new, set, get, for each of its objects.

A Component Architecture in object language has a special cycle life :

*Build all components (new new new new new)
*Plug all components together (set set set set set)
*Run a main component.

Main component is Z80 on JavaCPC. In fact, JavaCPC's Z80 is already configured in order to run each instruction with a certain timing : a timing already synchronized with CRTC (each instruction takes 4 Tstates or 8 Tstates, Z80@4MHz CRTC@16bit@1MHz so drawing 8 colored pixels on mode 1 takes 4 Tstates)

My main component is [[#Clock_sequence]]

In real Amstrad, main component is GateArray.

The fact of choosing Z80 as main component just respects the emulation architecture.

===== Java debug mode =====

You can run JavaCPC on debug mode in Eclipse, and insert breakpoints.

It's useful for listening wires, and cut them. You can in live pause debug, cut a function and continue run.

===== Cut a wire, cut a function =====

Wire are done for sending message, a message in programming is a function call.

When we cut a input wire, we generally plug it to GND or Vcc.

For cutting a function, you have to insert a cut on it. A cut it's a return. You can insert a (very bad) forcing cut as:
if (1==1) return 0;
everywhere. So function is ended at this moment and next lines became death code. It exists quality code program for checking death code, because it's generally a bug of development, normally we put code in comment.

It is the way I used in order to induce JavaCPC, comparing it with my project.

=== Clock sequence ===
When we have to make several components to communicate in a perfect timing, making a sequencer is a nice approach : "It is now your turn to do something".

==== Clock sequence : first try (prototype) ====
Original Gatearray of Amstrad is a sequencer (counter plugged with a clock), it manage synchronization between video card and z80 and memory access.

Historically there is a link between CU of CU/ALU, and... control bus and... how making your own sequencer. But I will say no more in order to not disturb these text part xD

Whatever, I made my own sequencer here in form of a bus of 4 wires called CLK4. CLK4 execute a simple repetitive sequence like 0001 0010 0011... CLK4(3), the last wire is directly connected to Z80 clock entry. Component not using explicit CLK4 as clock entry are generally using a not(CLK4(3)) entry, in order to do operation not as same time than z80.

Real Amstrad use buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert by the way more pixels that can support my small CRTC...

How to use a sequence in VHDL :
if rising_edge(master_clk) then

if seq="00" then

elsif seq="01" then

elsif seq="10" then

else

end if

end if

What not to do :
if rising_edge(seq[0]) then

end if
Because that can auto-generate bad unwanted sub-clocks...

==== Clock sequence : under time constraints (quality) ====
In fact, it's better to create you clock sequencer wiring each CLK and not(CLK) directly from DCM, in this case you enter in time constraints norm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code (more stable/quality).

Clock sequence using a counter plugged with a clock was in fact a bad practice (but running fine in my first versions of FPGAmstrad as I'm a good blind developer), because output are not under clock constraint : just think about that a "not" component added just after a clock wire is a Time Constraints bad practice... destroying "time constraint" solver (the one telling you when your clock domains are bad (and why), "time constraint" is last step of FPGA compiling process, it is a important step about quality, it shall be respected (generaly in a very last development effort, I shall say in a deploy effort))

==== Clock sequence : mirror VRAM (performance) ====
In order to get a better external RAM performance, and getting more luck about porting my project into others FPGA platform, I do now use a "Mirror VRAM" : external is just used by Z80 read and write (no more clock sequence finally ^^'). And a write in video RAM zone (like "poke &C000,255") does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, this VRAM can be written at a certain speed and read at another for VGA purpose (FPGA internal RAM can be used like that)

=== USB joystick ===
Before learning final platform and its embedded controlers (USB joystick with a controler, is just 7 wires : left right up down buttonX buttonY buttonZ), and after having destroyed 12 collector original joysticks during tests... I did some research about simply connecting a modern USB joystick into FPGA. It was a part of my Agile Method run, I worked about two months on it.

http://www.youtube.com/watch?v=5BERbI2kyfM

==== Sniffing USB frames ====
USB uses two wires in order to transmit frames, green and white, each with two logical values: 0v and 5v.

Let's plug a joystick on PC, if you listen at its two wires, you can sniff a USB transmission. Finally you can save it for example on RAM.

These two wires can be traduced into one with four states: 00 01 10 11.

One of this states is sleep state, in fact it depends on USB mode you use.
===== USB mode: USB1 or USB2; low speed, full speed or high speed =====
For sampling, I speed up five times the saving speed on RAM. I succeed sampling an USB1 transmission: "Logitech dual action USB joystick", and an USB2: "Sony PS3 USB joystick". PS3 joystick is not stable enough with my FPGA, but Logitech joystick is correct.

http://github.com/renaudhelias/CoreAmstrad/blob/master/BuildYourOwnZ80Computer/USB_logitech.vhd

http://www.youtube.com/watch?v=2zEp1tHroBs

http://github.com/renaudhelias/CoreAmstrad/blob/master/BuildYourOwnZ80Computer/USB_ps3.vhd

http://www.youtube.com/watch?v=fh4v4OXridc

USB is just a state machine (welcome how are you today, show me your state, show me your state, show me your state....), encoding (have to read USB manual), you can use some usb snifer software to decode them. Snifer software does not show low level message (ack ko ok) but does show the high level message (ones that show that a button is pressed or not)

As it is just encoding, you can capture signals and show that they differ only when you do unpress or press a button.

===== pull up and pull down =====
If you respect USB protocol, you have to plug some pull-up and pull-down resistors and some capacitors. But as I am a bad electrician, I just simulate then in VHDL, they are important because they cause USB speed negotiations. You also have an electronic mechanism in order to detect presence of joystick plug, I don't care about it.

For reaching which wire you have to pull-up or pull-down, here the tips :
*For slave (ideal for sniffing) : just take your USB1 joystick without plug it, just supply it (+5v red, 0v black), and test while-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down.
*For master (ideal for creating a mini-host) : just take your PC USB1 port, and test while-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down. Normally you result two pull-down.

==== Synchronize, decode and check USB frames ====
One time sample is done, it is not readable. In fact USB frames are synchronized (they started with a certain synchronization pattern), encoded (NRZI), and checked (CRC). CRC type depends on frame length. Encoding is done for synchronization optimization.

Then using USB HID manual, you can understand type of frames, and author of them, and remark that the author alternate: USB master (PC) or USB slave (joystick)

You can use some "USB sniffer software" in order to understand more easily some frames contain, but they generally don't give all frame, and full frame.

[http://www.usb.org/developers/whitepapers/crcdes.pdf great crc check example in perl - offered by www.usb.org]

==== Build a minimum USB master frames state-machine ====
Let's just plug a USB joystick on FPGA, directly, permanently, thinking about minimum coding size : we can't implement full HID USB protocol on FPGA ^^'

Objective here is to build a minimum state-machine graph, having for transaction between state a "frame transmission". It is normal on USB protocol to have error of transmission, so you have also to put "error frame transmission" on the graph.

At stabilization, you finally switch between two states, one sending a certain frame that contains at different offset simply certain values of joystick button.

At start, some frames are employed for "next frame description", they can generally be ignored, as our USB architecture is fixed and minimal (one USB joystick, that's all)

==== go further with USB sniffer ====

A better way to snif USB could be generation of TCP/IP packets encapsuling USB packets, and to record them directly on PC from a RJ45 plug, using this way I could save more than 10 seconds of information transmission (RAM size is limited on FPGA platfoms)

[[File:Usb-paf.png|thumbnail]]

http://www.ulule.com/usb-paf (unfunded) => but MiST-board final platform does offer USB pro competition Joystick compatibility <3 <3 <3

----

== Platforms ==
=== Why NEXYS2 500kgates starter kit ===
==== Xilinx schematics ====
Xilinx webpack software permit drawing schematics as book schematics, My point of view is : "For programming a FPGA, you draw a schematic as old books and just press one button. Each component on this schematic can be edited, in a language called VHDL".

My source code is not Altera compatible because of schematics drawn, but webpack can export vhdl code from schematics if you want.

==== RAM dump ====

A starter kit that contains a RAM component, that you can dump separaly : you can change schematics without loosing RAM content ! - and so write a schematic for dump only ;)

While power is on you can:

*programming FPGA with a program/schematics done for filling RAM
*press reset button
*programming FPGA with a program/schematics done for using RAM
*press reset button
*programming FPGA with a program/schematics done for reading RAM
*press reset button

My own made program does it with poor serial port, so for dumping all RAM content it takes about 3 hours, and for dumping Amstrad RAM part it is about 15 minutes.

On [[http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 Diligent NEXYS2 official page]], you can download a "Onboard Memory controller reference design" that contains explanation and VHDL source code about dumping on RAM/ROM of NEXYS2 directly from PC (usb port). I didn't tested this yet, but it is certainly a nicer approach :P

==== FPGA internal RAM size ====
It's to know that a FPGA chip contain 45KB internal RAM (360Kb for NEXYS2 500k-gates, and 504Kb for 1200k-gates) so you can't insert a dsk inside. This internal RAM is already used in part by T80 (z80 from opencores), by the soundchip, and for special RAM '''ramb16_s16_s16''' (RAM with two different speed one for writing another for reading, in fact two RAM with a common part) that I use for VGA mode.

==== VHDL components size ====
T80 (z80 processor) take 100kgates

Yamaha sound chip (from fpgaarcade) take 50kgates

InterruptGenerator + VGA mode take 50kgates

Bootloader (for standalone) take about 120kgates (FAT32 protocol, SPI protocol, DSK protocol)

Actually the project take about 99.9% of 500kgates. But I think that TV mode will take a lower size. A bigger size shall be great for Amstrad CPC Plus version, if JavaCPC evolve, and then if I evolve ;)

=== Why MiST-board final platform ===
==== Final version of FPGAmstrad ====
[http://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad MiST-board : CoreDocAmstrad]
==== Altera schematics ====
Altera does also permit drawing schematics. I love schematics, my top file -gluing components- is sure a drawn schematic.
==== USB competition-pro Joystick ====
my favorite one <3
==== SDCARD entry robust ====
SDCARD player is nice built. It is not destroyed after 30 insertions.
It is also easy to program FPGA : I just have to put my files into a SDCARD, and it runs, that's all.
==== Metal case ====
It's a true final platform.
----

== MiST-board - Core Developer's Notes ==
Here, you'll find all the Amstrad MiST Core development strategy : deployment of FPGAmstrad project on this lovely MiST-board final FPGA platform.

You'll find also the Amstrad MiST Core source code.

Goto [http://github.com/mist-devel/mist-board/wiki/CoreDocAmstrad MiST-board : CoreDocAmstrad] if you want to test final version of CoreAmstrad running on MiST-board platform (a final-user platform)

=== From Xilinx to Altera schematics ===
For me, global schematics are really important, for developing and for deploying.
A schematic developed in order to be comparable to original documentation schematic is nice. FPGAmstrad is composed of 3 schematics :
* amstrad_motherboard : comparable to original Amstrad schematic.
* amstrad_video : does manage a true VGA output, using a internal VRAM.
* bootloader_sd : sdcard bootloader, in order to load ROM and dsk at boot, from sdcard.

As Xilinx schematics are not compatible with Altera, I do generate "vhf" files, and rename them :
* FPGAmstrad_amstrad_motherboard.vhd
* FPGAmstrad_amstrad_video.vhd
* FPGAmstrad_bootloader_sd.vhd

And then I make a global schematic in Altera, that contains the previous components, and several MiST-board controlers :
* FPGAmstrad_amstrad_motherboard.vhd
* FPGAmstrad_amstrad_video.vhd
* FPGAmstrad_bootloader_sd.vhd
* sdcard.v
* user_io.v
* data_io.v
* sdram.v
* osd.v

I create then a main clock component, generating all clocks I want even the not clocks (a good practice, while using "time constraints"),
I also add some adapters, about wire/bus range solving :
* MIST_SDRAM.vhd : each SDRAM has a different RAM bus size
* MIST_DQM.vhd : just a small wiring helper
* MIST_RGB.vhd : each VGA output has different count of colors
* MIST_STATUS.vhd : mapping status wires
* CONF_STR.vhd : generating OSD parameter

=== Xilinx to Altera ===
While generating vhf files from Xilinx Schematics, a lot of small components have to be adapted :
* INV component became 'not' instruction
* AND2 component became 'and' instruction
* OR2 component became 'or instruction
* GND component became '0' value
* VCC component became '1' value
The internal RAM, sync and async (with one or two clocks) are to adapt, I use mem_altera_gen.vhd for this purpose.

=== Special things done during deploy ===

sdram.v is personalized in order to solve address **after** the write or read event. It is due to Amstrad that permit writing in RAM hidden inside ROM : if I read I read ROM, if I write I write RAM.

sdram.v is also personalized in order having a clkref lower than 4MHz.

=== RAM optimization ===

Some efforts done about internal RAM.

As I could not do enter my 32KB VRAM, I used a 16KB+8KB+4KB VRAM, to display the 640x480 output, scanning my 800x600 VRAM : bottom of my VRAM is useless for a 640x480 display.

At this step, I have 0KB of internal RAM free. Now let's do appear 16KB more in order to deploy fully my FPGAmstrad project !

RAM inferred : [in Altera reg is inferred into RAM-block](http://quartushelp.altera.com/13.0/mergedProjects/hdl/vlog/vlog_file_dir_ram.htm) ([http://quartushelp.altera.com/13.0/mergedProjects/hdl/vlog/vlog_file_dir.htm more]), so a reg written like this :
reg [7:0] dir_entry_reg [31:0]
became RAM-block.

In data_io.v : dir_entry_reg does use /**synthesis noprune**/ in order to be not unwired. If I remove output dir_entry_d, RAM-block is inferred. If I let output dir_entry_d, LOGIC-block is inferred.

So I removed output dir_entry_d and set :
(* ramstyle = "logic" *) reg [7:0] dir_entry_reg [31:0] /* synthesis noprune */;
So I continue winning my 1KB internal RAM-block (here 256 Bytes was needed and turn into inferred LOGIC-block)

In sdcard.v
reg [7:0] buffer [511:0];
is a big reg and really important one (speaking to ARM SPI !), so I let it inferring into RAM-block.
But about cid and csd I does :
(* ramstyle = "logic" *) reg [7:0] cid [15:0];
(* ramstyle = "logic" *) reg [7:0] csd [15:0];
Winning 2KB of internal RAM for this small 128Bytes reg :)

In VRAM_Palette, I had 16KB. But in fact a raster line is a 2+16+1 RAM palette line, so each line I store 19KB, so in fact 19*600/2=5700 bytes (800x600 VRAM in fact thruly 800x300). So only a 8KB RAM palette only was needed in FPGAmstrad project finally.

At this step I won 10KB of internal RAM (I need 6KB more to succeed in my full FPGAmstrad deployment)

I can nibble 2KB more at end of RAM palette, that's what I does.

Now I have 12KB of internal RAM free :)

And 4KB in VRAM :
800x600=100*300=30KB full
800x480=100*240=24000 24000-16384=7616<8KB=8192
so VRAM with a start vertical offset can be composed of 16KB+8KB only. So I won my last 4KB here.

I did patch my simple_GateArrayInterrupt component by parametering vertical offset :

GA_interrupt : simple_GateArrayInterrupt
generic map (VRAM_Voffset=>38*8-30*8-4*8+4 +0 +15) -- MiST +15 ?

I also patched my aZRaEL_vram2vgaAmstradMiaow component by parametering vertical offset :

XLXI_476 : aZRaEL_vram2vgaAmstradMiaow
generic map (VOFFSET_NEGATIF =>0, -- MiST 0
VOFFSET_PALETTE=>0) -- MiST 0

Now I can use my 16KB free RAM in VRAM double buffer. Reaching a full FGPAmstrad project deploy on MiST-board, unlocking others games : it is what is done in realise 002 of Amstrad core. I tested ChaseHQ does now run fine.

== Source code ==
=== FPGAmstrad source code (Xilinx)===
The project binary downloadable on [[#How_to_assemble_it]] section contains in fact source code and the binary file (.bit)

This is a simple zip of project folder.

The project was done using '''Xilinx webpack'''

It contains some direct drawn schematics, and VHDL components

=== MiST-board CoreAmstrad source code (Altera) ===
[http://github.com/renaudhelias/CoreAmstrad MiST-board CoreAmstrad source code]

Compiling OK in Quartus II 13.0 (Altera IDE), and a few in ISE Design Suite 14.7 (Xilinx IDE) - I have to report back some modifications from my deploy platform(Altera MiST-board) to my dev platform (Xilinx NEXYS4 from Digilent Inc.)

----

== Schematics ==

I explode the main schematic into a task by component, so the schematic is big.

Starter kit use only one RAM physical component for RAM ROM and DSK alignment, so I had to manage accesses (it is possible in fact because Z80 is a sequential processor)

My clock take 4 wires, in fact it exists a clock sequence [[#Clock_sequence]] (during 1 z80 tic, I do several things)

RAM is done for being dump, comparable to JavaCPC snapshoots.

----

== Components ==

sound chip is [http://www.fpgaarcade.com/library.htm ym2149 fpgaarcade] one, patched, and repatched in order to get stereo sound.

PPI chip is [http://www.cpcwiki.eu/index.php/VHDL_implementation_of_the_8255_PIO 8255 CPCWiki] one, patched.

PWM chip is [http://www.fpga4fun.com/PWM_DAC.html PWM_DAC fpga4fun] one, patched in order to get high sound quality (my PWM has two clocks in entry)

== And thanks ==

Certainly first thanks to [http://java.cpc-live.com Markus Hohmann], for having programmed a Java version of CPC, I love Java and VHDL, so this project comes from this Java Amstrad emulator.

Secondary Steve Ciarca, author of "Build your own Z80 computer" (1981), so nice book.

Then the author of the VHDL version of Yamaha sound chip : [http://www.fpgaarcade.com/library.htm fpgaarcade]. And [http://opencores.org/project,t80 opencores] for the Z80 (T80)...

And websites that give access to so much old Amstrad resources like :
* [http://cpcwiki.eu/ CPCWiki] :) ''the Amstrad community''
* [http://quasar.cpcscene.com Quasar Net] fr ''lost legends''
* [http://www.grimware.org Grimware] ''lost schematics knowledge''
* [http://cpcrulez.fr/ CPCRULEZ] fr ''assembler and legends''
* [http://www.genesis8bit.fr/ Genesis8] fr ''games news''
* [http://www.amstradtoday.com/ Amstrad TODAY] fr ''a nice link list''
* [http://pushnpop.net Push'n'Pop] ''lost FDC knowledge''

And more :
* [http://www.cpcgamereviews.com CPC GAMES REVIEWS] ''large illustrated dsk image database''
* [http://java.cpc-live.com JavaCPC emulator] ''Markus Hohmann''
* [http://www.cpcmania.com CPCMANIA] ''plug Amstrad on TV''
* [http://bellaminettes.com Bellaminettes] fr ''Artist drawer -nice girls- from ACBM magazine - Les puces informatiques - Sasfepu''

=== Others tricks ===
If you aren't ready yet, here somes experiments (youtube) on real Amstrad :
* [http://www.youtube.com/watch?v=XKl93DmX9gk Test of SCART (TV) on Amstrad CPC 6128 +]
* [http://www.youtube.com/watch?v=XPmeyDbSwUI Test of external 3.5 disk on Amstrad CPC 6128 +]

[[Category:Hardware]]
[[Category:Emulator]]
[[Category:Non CPC Computers]]
[[Category:Clones]]

Gate Array

2017-03-04T02:12:57Z

Dingo: /* To calculate the colour value */

Gate Array

Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).

== Introduction ==

The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.

The Gate Array is described here is the one found in a standard CPC.

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
|''Data Bit 7''||''Data Bit 6''||''Function''
|-
| 0 || 0 || Select pen
|-
| 0 || 1 || Select colour for selected pen
|-
| 1 || 0 || Select screen mode, ROM configuration and interrupt control
|-
| 1 || 1 || RAM Memory Management (note 1)
|-
|}

===== Note =====

This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.

== Register 0 - Palette Index (Pen selection) ==

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 1 - Palette Data (Colour selection) ==

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 2 - Select screen mode and ROM configuration ==

This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.

=== Screen mode selection ===

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit 1'' || ''Bit 0'' || ''Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

=== ROM configuration selection ===

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Screen Mode slection
|-
| 0 || x
|}

== Register 3 - RAM Banking ==

This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate PAL that assists the Gate Array chip.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function 3
|-
| 6 || 1
|-
| 5 || b || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || b
|-
| 3 || b
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 RAM_4 RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 RAM_5 RAM_3 RAM_4 RAM_5 RAM_6 RAM_7
8000-BFFF RAM_2 RAM_2 RAM_6 RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 RAM_7 RAM_7 RAM_7 RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

=== Palette sorted by Hardware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 1 (41h) || (13) || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 2 (42h) || 19 || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 3 (43h) || 25 || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 4 (44h) || 1 || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 5 (45h) || 7 || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 6 (46h) || 10 || Cyan || 0|| 50|| 50|| bgcolor="#008080" |
|-
| 7 (47h) || 16 || Pink ||100|| 50|| 50|| bgcolor="#ff8080" |
|-
| 8 (48h) || (7) || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 9 (49h) || (25) || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 10 (4Ah) || 24 || Bright Yellow ||100||100|| 0|| bgcolor="#ffff00" |
|-
| 11 (4Bh) || 26 || Bright White ||100||100||100|| bgcolor="#ffffff" |
|-
| 12 (4Ch) || 6 || Bright Red ||100|| 0|| 0|| bgcolor="#ff0000" |
|-
| 13 (4Dh) || 8 || Bright Magenta||100|| 0||100|| bgcolor="#ff00ff" |
|-
| 14 (4Eh) || 15 || Orange ||100|| 50|| 0|| bgcolor="#ff8000" |
|-
| 15 (4Fh) || 17 || Pastel Magenta||100|| 50||100|| bgcolor="#ff80ff" |
|-
| 16 (50h) || (1) || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 17 (51h) || (19) || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 18 (52h) || 18 || Bright Green || 0||100|| 0|| bgcolor="#00ff00" |
|-
| 19 (53h) || 20 || Bright Cyan || 0||100||100|| bgcolor="#00ffff" |
|-
| 20 (54h) || 0 || Black || 0|| 0|| 0|| bgcolor="#000000" |
|-
| 21 (55h) || 2 || Bright Blue || 0|| 0||100|| bgcolor="#0000ff" |
|-
| 22 (56h) || 9 || Green || 0|| 50|| 0|| bgcolor="#008000" |
|-
| 23 (57h) || 11 || Sky Blue || 0|| 50||100|| bgcolor="#0080ff" |
|-
| 24 (58h) || 4 || Magenta || 50|| 0|| 50|| bgcolor="#800080" |
|-
| 25 (59h) || 22 || Pastel Green || 50||100|| 50|| bgcolor="#80ff80" |
|-
| 26 (5Ah) || 21 || Lime || 50||100|| 0|| bgcolor="#80ff00" |
|-
| 27 (5Bh) || 23 || Pastel Cyan || 50||100||100|| bgcolor="#80ffff" |
|-
| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" |
|-
| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| bgcolor="#8000ff" |
|-
| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| bgcolor="#808000" |
|-
| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| bgcolor="#8080ff" |
|}

=== Palette sorted by Firmware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Firmware Number'' || ''Hardware Number'' || ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0|| 54h ||Black || 0|| 0|| 0||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0||bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100||bgcolor="#ffffff"|
|}

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
* [[CPC Palette]] - some more details

=== To calculate the colour value ===

'''Red'''

0% => do not add anything

50% => add 3

100% => add 6

'''Green'''

0% => do not add anything

50% => add 9

100% => add 18

'''Blue'''

0% => do not add anything

50% => add 1

100% => add 2

=== Green Screen Colours ===

On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

==See also==

*[[Gate Array and ASIC Pin-Outs]]

*[[Video modes]] : for other informations on colours and pixels.

*[[CRTC]] : the other video stuff.
*[[ASIC]] : for Plus users

*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]

Gate Array

2017-03-04T02:12:12Z

Dingo: /* Palette R,G,B definitions */ BE; subtitle

Gate Array

Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).

== Introduction ==

The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.

The Gate Array is described here is the one found in a standard CPC.

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
|''Data Bit 7''||''Data Bit 6''||''Function''
|-
| 0 || 0 || Select pen
|-
| 0 || 1 || Select colour for selected pen
|-
| 1 || 0 || Select screen mode, ROM configuration and interrupt control
|-
| 1 || 1 || RAM Memory Management (note 1)
|-
|}

===== Note =====

This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.

== Register 0 - Palette Index (Pen selection) ==

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

 

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 1 - Palette Data (Colour selection) ==

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 2 - Select screen mode and ROM configuration ==

This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.

=== Screen mode selection ===

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit 1'' || ''Bit 0'' || ''Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

=== ROM configuration selection ===

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Screen Mode slection
|-
| 0 || x
|}

== Register 3 - RAM Banking ==

This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate PAL that assists the Gate Array chip.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function 3
|-
| 6 || 1
|-
| 5 || b || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || b
|-
| 3 || b
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 RAM_4 RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 RAM_5 RAM_3 RAM_4 RAM_5 RAM_6 RAM_7
8000-BFFF RAM_2 RAM_2 RAM_6 RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 RAM_7 RAM_7 RAM_7 RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

== Programming the Gate Array - Examples ==

Defining the colours, Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

=== Palette sorted by Hardware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 1 (41h) || (13) || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 2 (42h) || 19 || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 3 (43h) || 25 || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 4 (44h) || 1 || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 5 (45h) || 7 || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 6 (46h) || 10 || Cyan || 0|| 50|| 50|| bgcolor="#008080" |
|-
| 7 (47h) || 16 || Pink ||100|| 50|| 50|| bgcolor="#ff8080" |
|-
| 8 (48h) || (7) || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 9 (49h) || (25) || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 10 (4Ah) || 24 || Bright Yellow ||100||100|| 0|| bgcolor="#ffff00" |
|-
| 11 (4Bh) || 26 || Bright White ||100||100||100|| bgcolor="#ffffff" |
|-
| 12 (4Ch) || 6 || Bright Red ||100|| 0|| 0|| bgcolor="#ff0000" |
|-
| 13 (4Dh) || 8 || Bright Magenta||100|| 0||100|| bgcolor="#ff00ff" |
|-
| 14 (4Eh) || 15 || Orange ||100|| 50|| 0|| bgcolor="#ff8000" |
|-
| 15 (4Fh) || 17 || Pastel Magenta||100|| 50||100|| bgcolor="#ff80ff" |
|-
| 16 (50h) || (1) || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 17 (51h) || (19) || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 18 (52h) || 18 || Bright Green || 0||100|| 0|| bgcolor="#00ff00" |
|-
| 19 (53h) || 20 || Bright Cyan || 0||100||100|| bgcolor="#00ffff" |
|-
| 20 (54h) || 0 || Black || 0|| 0|| 0|| bgcolor="#000000" |
|-
| 21 (55h) || 2 || Bright Blue || 0|| 0||100|| bgcolor="#0000ff" |
|-
| 22 (56h) || 9 || Green || 0|| 50|| 0|| bgcolor="#008000" |
|-
| 23 (57h) || 11 || Sky Blue || 0|| 50||100|| bgcolor="#0080ff" |
|-
| 24 (58h) || 4 || Magenta || 50|| 0|| 50|| bgcolor="#800080" |
|-
| 25 (59h) || 22 || Pastel Green || 50||100|| 50|| bgcolor="#80ff80" |
|-
| 26 (5Ah) || 21 || Lime || 50||100|| 0|| bgcolor="#80ff00" |
|-
| 27 (5Bh) || 23 || Pastel Cyan || 50||100||100|| bgcolor="#80ffff" |
|-
| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" |
|-
| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| bgcolor="#8000ff" |
|-
| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| bgcolor="#808000" |
|-
| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| bgcolor="#8080ff" |
|}

=== Palette sorted by Firmware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Firmware Number'' || ''Hardware Number'' || ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0|| 54h ||Black || 0|| 0|| 0||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0||bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100||bgcolor="#ffffff"|
|}

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
* [[CPC Palette]] - some more details

=== To calculate the colour value ===

'''Red'''

0% => do not add anything

50% => add 3

100% => add 6

'''Green'''

0% => do not add anything

50% => add 9

100% => add 18

'''Blue'''

0% => do not add anything

50% => add 1

100% => add 2

=== Green Screen Colours ==0

On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

==See also==

*[[Gate Array and ASIC Pin-Outs]]

*[[Video modes]] : for other informations on colours and pixels.

*[[CRTC]] : the other video stuff.
*[[ASIC]] : for Plus users

*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]