CPCWiki - THE Amstrad CPC encyclopedia! - User contributions [en]

Technical documentation

2022-03-18T13:50:05Z

Bread80wiki: Moved Soft968 to firmware (etc) section. Clarified link to BIOS functions.

<div style="border: 1px solid rgb(228, 222, 222); margin: 0px 0px 5px; padding: 0.5em 1em; background-color: rgb(249, 249, 249);">
<center>

'''''Ongoing project for additional technical documentation: the [[KevArchive|local mirror]] of Kevin Thackers' archive at [http://www.cpctech.org.uk http://www.cpctech.org.uk].''''' </center></div>

== BASIC / Firmware / CP/M ==

* [[Locomotive BASIC]] (reference for BASIC commands, functions and error messages)
* [[Technical information about Locomotive BASIC]] (encoding of BASIC programs in memory)
* [[BIOS Functions]] (firmware routine summary)
* [[Soft968:_CPC_464/664/6128_Firmware|Soft968 Firmware Specification]] (the official Amstrad firmware documentation)

== DIY Hardware Projects ==

Can now be found under [[DIY|DIY & Repair]]

== Built-in connectors: pinout ==

* [[Connector:2nd disc drive (CPC664, CPC6128, CPC6128+)|2nd disc drive (CPC664, CPC6128, CPC6128+)]]
* [[Connector:Analogue joystick (CPC Plus only)|Analogue joystick (CPC Plus only)]]
* [[Connector:Aux socket (CPC Plus only)|Aux socket (CPC Plus only)]] (Lightgun)
* [[Connector:Cartridge Slot (CPC Plus only)|Cartridge Slot (CPC Plus only)]]
* [[Connector:Cassette recorder|Cassette recorder]]
* [[Connector:Digital joystick|Digital joystick]]
* [[Connector:Expansion port|Expansion port]]
* [[Connector:Monitor|Monitor]]
* [[Connector:Printer port|Printer port]]
* [[Connector:Stereo sound|Stereo sound]]

== Emulator file format specifications ==

* [[Format:CDT tape image file format|CDT - tape image file format]]
* [[Format:CPR CPC Plus cartridge file format|CPR - CPC Plus cartridge file format]]
* [[Format:DSC disk image file format|DSC - disk image file format]] (hardly used anymore)
* [[Format:DSK disk image file format|DSK - disk image file format]]
* [[Format:SNA snapshot file format| SNA - snapshot file format]]

== Hardware extensions ==

* [[M4_Board|M4-Wifi]]
* [[Programming:CPC Booster|CPC Booster]]
* [[Programming:SYMBiFACE II|SYMBiFACE II]]
* [[Peripherals]] (includes tech info, as far as known)

== Internal Components ==

* [[Default I/O Port Summary]] - map of built-in I/O ports of the CPC
* [[765 FDC]] - Floppy Disc Controller
* [[8255]] - PIO - I/O controller
* [[Arnold V Specs Revised]] - Arnold V (CPC+) Technical Specification
* [[AY-3-8912]] - Sound chip / keyboard controller
* [[Cassette data information]] - Information about the cassette storage system
* [[CRTC]] - Video chip
* [[Gate Array]] - Custom chip (frequency generation, colors, bank switching)
* [[PAL16L8]] - Controls RAM bank switching (see [[Gate Array]] for programming details)
* [[Power Supply for CPC and CPC plus]]
* [[Printer Port]]
* [[Mainboard Versions]]

== Service Manuals ==

* [[Service Manuals]]

== Protections ==

* [[8k Speedlock]]
* [[Alkatraz]]
* [[Speedlock]]
* [[Lenslok]]

== Specifications ==

*[[List of file formats|List of file formats]]
*[[Format:SGX (SymbOS graphic files)|SGX (SymbOS graphic files)]]
*[[Format:VID (SymbOS video files)|VID (SymbOS video files)]]
*[[Emulator IDs|List of Emulator IDs]]
*[[Class]] definitions of CPCs.

= Weblinks =

* https://acpc.me/#ACME/DOCS_TECHNIQUES

[[Category:Hardware|*]] [[Category:Manual|*]][[Category:CPC Internal Components]][[Category:Cpctech.org]][[Category:Software|*]][[Category:DIY| ]]

Technical documentation

2022-03-18T13:40:54Z

Bread80wiki: Added link to the PAL

<div style="border: 1px solid rgb(228, 222, 222); margin: 0px 0px 5px; padding: 0.5em 1em; background-color: rgb(249, 249, 249);">
<center>

'''''Ongoing project for additional technical documentation: the [[KevArchive|local mirror]] of Kevin Thackers' archive at [http://www.cpctech.org.uk http://www.cpctech.org.uk].''''' </center></div>

== BASIC / Firmware / CP/M ==

* [[BIOS Functions]]
* [[Locomotive BASIC]] (reference for BASIC commands, functions and error messages)
* [[Technical information about Locomotive BASIC]] (encoding of BASIC programs in memory)

== DIY Hardware Projects ==

Can now be found under [[DIY|DIY & Repair]]

== Built-in connectors: pinout ==

* [[Connector:2nd disc drive (CPC664, CPC6128, CPC6128+)|2nd disc drive (CPC664, CPC6128, CPC6128+)]]
* [[Connector:Analogue joystick (CPC Plus only)|Analogue joystick (CPC Plus only)]]
* [[Connector:Aux socket (CPC Plus only)|Aux socket (CPC Plus only)]] (Lightgun)
* [[Connector:Cartridge Slot (CPC Plus only)|Cartridge Slot (CPC Plus only)]]
* [[Connector:Cassette recorder|Cassette recorder]]
* [[Connector:Digital joystick|Digital joystick]]
* [[Connector:Expansion port|Expansion port]]
* [[Connector:Monitor|Monitor]]
* [[Connector:Printer port|Printer port]]
* [[Connector:Stereo sound|Stereo sound]]

== Emulator file format specifications ==

* [[Format:CDT tape image file format|CDT - tape image file format]]
* [[Format:CPR CPC Plus cartridge file format|CPR - CPC Plus cartridge file format]]
* [[Format:DSC disk image file format|DSC - disk image file format]] (hardly used anymore)
* [[Format:DSK disk image file format|DSK - disk image file format]]
* [[Format:SNA snapshot file format| SNA - snapshot file format]]

== Hardware extensions ==

* [[M4_Board|M4-Wifi]]
* [[Programming:CPC Booster|CPC Booster]]
* [[Programming:SYMBiFACE II|SYMBiFACE II]]
* [[Peripherals]] (includes tech info, as far as known)

== Internal Components ==

* [[Default I/O Port Summary]] - map of built-in I/O ports of the CPC
* [[765 FDC]] - Floppy Disc Controller
* [[8255]] - PIO - I/O controller
* [[Arnold V Specs Revised]] - Arnold V (CPC+) Technical Specification
* [[AY-3-8912]] - Sound chip / keyboard controller
* [[Cassette data information]] - Information about the cassette storage system
* [[CRTC]] - Video chip
* [[Gate Array]] - Custom chip (frequency generation, colors, bank switching)
* [[PAL16L8]] - Controls RAM bank switching (see [[Gate Array]] for programming details)
* [[Power Supply for CPC and CPC plus]]
* [[Printer Port]]
* [[Mainboard Versions]]

== Service Manuals ==

* [[Service Manuals]].
* [[Soft968:_CPC_464/664/6128_Firmware]].

== Protections ==

* [[8k Speedlock]]
* [[Alkatraz]]
* [[Speedlock]]
* [[Lenslok]]

== Specifications ==

*[[List of file formats|List of file formats]]
*[[Format:SGX (SymbOS graphic files)|SGX (SymbOS graphic files)]]
*[[Format:VID (SymbOS video files)|VID (SymbOS video files)]]
*[[Emulator IDs|List of Emulator IDs]]
*[[Class]] definitions of CPCs.

= Weblinks =

* https://acpc.me/#ACME/DOCS_TECHNIQUES

[[Category:Hardware|*]] [[Category:Manual|*]][[Category:CPC Internal Components]][[Category:Cpctech.org]][[Category:Software|*]][[Category:DIY| ]]

Gate Array and ASIC Pin-Outs

2022-03-18T13:25:54Z

Bread80wiki: Added links to gate array and PAL pages

[[Category:Electronic Component]]
== 40pin Gate Array 40007 (20RA043) ==
Old CPC464 version (with cooling plate).
1 /CPU ADDR
2 READY
3 /CAS
4 /244EN
5 /MWE
6 /CAS ADDR
7 /RAS
8 XTAL
9 VCC2
10 /INTERRUPT
11 /SYNC (video)
12 /ROMEN
13 /RAMRD
14 HSYNC
15 VSYNC
16 /IORQ
17 /M1
18 /MREQ
19 /RD
20 A15
21 A14
22 VCC1
23 DISPEN
24 D0
25 D1
26 D2
27 D3
28 D4
29 D5
30 D6
31 D7
32 VIDEO B (video)
33 VCC2
34 VIDEO G (video)
35 GND
36 VIDEO R (video)
37 /RESET
38 VCC1
39 PHI
40 MA0/CCLK
VCC1=+5V (direct), VCC2=+5V (via resistor)

== 40pin Gate Array 40008 ==
An updated, pin compatible version of the 40007. The 40008 like the 40007 required a heatsink.

== 40pin Gate Array 40010 (HSG3130 or HSG3170) ==
Newer version of Gate Array with a rearranged pin-out. The 40010 didn't required a cooling plate.

1 D5
2 D6
3 D7
4 CCLK
5 /SYNC (video)
6 VCC
7 /RESET
8 B (video)
9 DISPEN
10 G (video)
11 HSYNC
12 R (video)
13 VSYNC
14 /CPU
15 GND
16 /CAS
17 /MREQ
18 /IORQ
19 /PHI
20 /M1
21 /RD
22 READY
23 /244EN
24 CK16
25 VCC
26 GND
27 /ROMEN
28 A15
29 /RAMRD
30 A14
31 /CASAD
32 /INTERRUPT
33 /MWE
34 /RAS
35 D0
36 GND
37 D1
38 D2
39 D3
40 D4

== 20pin PAL/HAL PAC 16L8AC AMG40030 ==
Assists the 40pin Gate Array chip (for 128K RAM banking).
1 SELECT (D7 AND D6)
2 D0
3 /RESET
4 RAMDIS
5 D1
6 D2
7 NCAS
8 A15
9 A14
10 GND
11 /CPU
12 A15OUT
13 NC*
14 NC*
15 NC*
16 /CAS1
17 /CAS0
18 /IOWR
19 A14OUT
20 VCC
When PAL not installed: Close LK5,LK6,LK8 for 64K version.
(* NC but signals exist on those pins)

== 100pin Gate Array AMS40226 (ARN4) ==
Pre-ASIC (late cost-down models).
See CPC6128 "ULA/DS" section in Amendment Service Manual.
Aside from Gate Array, it includes CRTC, probably PAL, FDC select/motor, DRAM
addr/data bus, RESET signals.
1 SCLKI
2 VCC
3 GND
4 /ROM1 (BIOS,BAS)
5 /ROM2 (AMSDOS)
6 RA7
7 RA6
8 RA5
9 RA4
10 RA3
11 RA2
12 RA1
13 RA0
14 VCC
15 GND
16 /CAS0
17 /CAS1
18 /WE
19 /RAS
20 RD7
21 RD6
22 RD5
23 RD4
24 RD3
25 RD2
26 RD1
27 RD0
28 /FDC (DISC)
29 RESET
30 WCLK (DISC)
31 /MOTOR (DISC)
32 CLK8
33 PLLCK (CLK8, too?)
34 RDTA
35 DATA (undocumented optional output to FDC)
36 WINDOW (undocumented optional output to FDC)
37 RED
38 GRE
39 BLU
40 GND
41 VCC
42 /SYNC
43 CLK4
44 /EXP (DISC?)
45 LPEN (CRTC)
46 CURS (CRTC)
47 RAMDIS
48 /RAMRD
49 ROMDIS
50 /ROMEN
51 /RESET
52 GND
53 VCC
54 /BRST (BUS RESET)
55 READY
56 /INT
57 /WR
58 /RD
59 /IORQ
60 /M1
61 /MREQ
62 D0
63 D1
64 D2
65 D3
66 GND
67 VCC
68 D4
69 D5
70 D6
71 D7
72 A0
73 A1
74 A2
75 A3
76 A4
77 A5
78 A6
79 A7
80 A8
81 A9
82 A10
83 A11
84 A12
85 A13
86 A14
87 A15
88 /IOW
89 GND
90 VCC
91 /IOR
92 /PSTB (Printer Select) (Ann OR /IOW) (this is not STROBE)
93 MA11
94 CLK1 (PSG)
95 VSYNC
96 /SRST (S RESET)
97 L4N6 (GNDed in CPC6128) (maybe VCC in 64K versions?)
98 /TST1
99 /TST2
100 SCLKO
Printer port 74LS273 chip is replaced by TWO chips: 74LS174 and 74LS175 (the
latter one includes strobe inversion).
Pin 35/36 are not documented on schematic, but from PCB layout they can be connected to FDC by links. These are output of internal FDC data separator.

== 160pin ASIC (CPC+/GX4000) ==
Includes Gate Array, CRTC, PPI, 8bit printer port, FDC select/motor, keyboard
mux, analog I/O, CLK dividers, new CPC+ features (video, dma), cart rom bank,
cart ACID counterpart, 128K RAM banking, DRAM addr/data bus, RESET signals.
Lacks external PB0 and PC0-3 pins. PB/PC are one-directional. PB5 combines
AMSDOS bank and /EXP input.
1 OSCO
2 OSCI
3 GND
4 ADC0
5 ADC1
6 ADC2
7 ADC3
8 ADC4
9 ADC5
10 GND
11 AHOLD
12 MUX2
13 MUX1
14 MUX0
15 COMP
16 CLK1 (PSG.1MHz)
17 PA0 (PSG.D0)
18 PA1 (PSG.D1)
19 PA2 (PSG.D2)
20 VCC
21 PA3 (PSG.D3)
22 PA4 (PSG.D4)
23 PA5 (PSG.D5)
24 PA6 (PSG.D6)
25 PA7 (PSG.D7)
26 PC6 (PSG.BC1)
27 PC7 (PSG.BDIR)
28 GND
29 /ROM
30 CA18
31 CA17
32 CA16
33 CA15
34 CA14
35 A15
36 A14
37 A13
38 A12
39 A11
40 A10
41 A9
42 A8
43 A7
44 A6
45 A5
46 A4
47 A3
48 A2
49 A1
50 GND
51 A0
52 RSET (RESET)
53 /IOR
54 /IOW
55 /FDC (DISC)
56 VCC
57 /WCLK (DISC)
58 D7
59 D6
60 D5
61 D4
62 D3
63 D2
64 D1
65 D0
66 /M1
67 PC4 (CAS.MOTOR)
68 PB7 (CAS.IN)
69 PC5 (CAS.OUT)
70 GND
71 KY10
72 KY9
73 KY8
74 KY7
75 KY6
76 KY5
77 KY4
78 KY3
79 KY2
80 KY1
81 RA7
82 RA3
83 RA4
84 RA2
85 RA5
86 RA1
87 RA6
88 RA0
89 GND
90 /RAS
91 /CAS1
92 /WE
93 /CAS0
94 RD0
95 RD1
96 RD2
97 RD3
98 RD4
99 RD5
100 VCC
101 RD6
102 RD7
103 /MOTOR (DISC)
104 BLU0
105 BLU1
106 BLU2
107 BLU3
108 GND
109 GRN0
110 GRN1
111 GRN2
112 GRN3
113 RED0
114 RED1
115 RED2
116 RED3
117 CLK16
118 /SYNC (video)
119 PB5 (LK5) (/EXP)
120 PB4 (LK4) (50Hz/60Hz)
121 VCC
122 PB3 (LK3) (maker)
123 PB2 (LK2) (maker)
124 PB1 (LK1) (maker)
125 CLK4 (4MHz)
126 LPEN (CRTC)
127 RAMDIS
128 CURS (CRTC)
129 ROMDIS
130 GND
131 /ROMRD
132 /RESET
133 /ROMEN
134 READY
135 /INT
136 /WR
137 /IORQ
138 /RD
139 /MREQ
140 GND
141 PALCLK (4.4MHz) (GX4000)
142 TST1
143 TST2
144 TST3
145 PSTB (STROBE)
146 PR0
147 PR1
148 PR2
149 PR3
150 GND
151 PR4
152 PR5
153 PR6
154 PR7
155 PB5 (BUSY)
156 /SRST (s reset)
157 CCLR (ACID)
158 SIN (ACID)
159 /BRST (bus reset)
160 VCC

== 16pin ACID Amstrad 40908 (1L03P1003) ==
The ASIC counterpart in CPC+/GX4000 carts.
1 GND
2 A7
3 CLK4
4 NC
5 CCLR
6 SIN
7 /CE
8 GND
9 A0
10 A1
11 A2
12 A3
13 A4
14 A5
15 A6
16 VCC

== See also ==

*[[Gate Array]]

*[[PAL16L8]]

PAL16L8

2022-03-18T13:22:59Z

Bread80wiki: /* See also */

The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.

== Fixed version (Gerald) ==
Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.

A14OUT = !( !A14
# !A15 & !Q0 & Q2 );

A15OUT = !( !A15 & !A14
# !A15 & !Q1
# !A15 & !Q0 & !Q2 );

Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q0
# nRESET & A15 & Q0
# nRESET & nIOWR & Q0 );

Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q1
# nRESET & A15 & Q1
# nRESET & nIOWR & Q1 );

Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q2
# nRESET & A15 & Q2
# nRESET & nIOWR & Q2 );

nCAS0 = ( nCAS
# RAMDIS & !nCPU & nCAS0
# !A15 & A14 & !nCPU & Q2 & nCAS0
# A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS1 );

nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
# !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
# !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
# !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );

[[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement

[[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.

== Initial replacement equation (Porchy) ==

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

A15OUT = (!X2 & !X1 & A14
# !X3 & !X2 & A14
# A15);

!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
# !X1 & RESET & IOWR
# !X1 & !D7ANDD6 & RESET
# !X1 & A15 & RESET);

!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
# !X2 & RESET & IOWR
# !X2 & !D7ANDD6 & RESET
# !X2 & A15 & RESET);

!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
# !X3 & RESET & IOWR
# !X3 & !D7ANDD6 & RESET
# !X3 & A15 & RESET);

!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
# !NCAS & CAS0 & !CAS1);

!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
# X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
# !X3 & A15 & !NCAS & !RAMDIS & CAS1
# !X1 & !A14 & !NCAS & !RAMDIS & CAS1
# !X3 & !A14 & !NCAS & !RAMDIS & CAS1
# !NCAS & !RAMDIS & CPU & CAS1
# !NCAS & !CAS0 & CAS1);

A14OUT = (A15 & A14
# !X1 & A14
# X3 & A14);

[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum

== See also ==

*For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).

*[[Gate Array and ASIC Pin-Outs]]

[[Category:Datasheet]]

PAL16L8

2022-03-18T13:21:14Z

Bread80wiki: Added link to pin-out

The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.

== Fixed version (Gerald) ==
Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.

A14OUT = !( !A14
# !A15 & !Q0 & Q2 );

A15OUT = !( !A15 & !A14
# !A15 & !Q1
# !A15 & !Q0 & !Q2 );

Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q0
# nRESET & A15 & Q0
# nRESET & nIOWR & Q0 );

Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q1
# nRESET & A15 & Q1
# nRESET & nIOWR & Q1 );

Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q2
# nRESET & A15 & Q2
# nRESET & nIOWR & Q2 );

nCAS0 = ( nCAS
# RAMDIS & !nCPU & nCAS0
# !A15 & A14 & !nCPU & Q2 & nCAS0
# A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS1 );

nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
# !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
# !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
# !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );

[[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement

[[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.

== Initial replacement equation (Porchy) ==

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

A15OUT = (!X2 & !X1 & A14
# !X3 & !X2 & A14
# A15);

!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
# !X1 & RESET & IOWR
# !X1 & !D7ANDD6 & RESET
# !X1 & A15 & RESET);

!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
# !X2 & RESET & IOWR
# !X2 & !D7ANDD6 & RESET
# !X2 & A15 & RESET);

!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
# !X3 & RESET & IOWR
# !X3 & !D7ANDD6 & RESET
# !X3 & A15 & RESET);

!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
# !NCAS & CAS0 & !CAS1);

!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
# X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
# !X3 & A15 & !NCAS & !RAMDIS & CAS1
# !X1 & !A14 & !NCAS & !RAMDIS & CAS1
# !X3 & !A14 & !NCAS & !RAMDIS & CAS1
# !NCAS & !RAMDIS & CPU & CAS1
# !NCAS & !CAS0 & CAS1);

A14OUT = (A15 & A14
# !X1 & A14
# X3 & A14);

[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum

== See also ==

For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).

[[Gate Array and ASIC Pin-Outs]]

[[Category:Datasheet]]

PAL16L8

2022-03-18T13:06:15Z

Bread80wiki: Added link to gate array page

The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.

On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.

== Fixed version (Gerald) ==
Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.

A14OUT = !( !A14
# !A15 & !Q0 & Q2 );

A15OUT = !( !A15 & !A14
# !A15 & !Q1
# !A15 & !Q0 & !Q2 );

Q0 = ( D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q0
# nRESET & A15 & Q0
# nRESET & nIOWR & Q0 );

Q1 = ( D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q1
# nRESET & A15 & Q1
# nRESET & nIOWR & Q1 );

Q2 = ( D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
# !D7ANDD6 & nRESET & Q2
# nRESET & A15 & Q2
# nRESET & nIOWR & Q2 );

nCAS0 = ( nCAS
# RAMDIS & !nCPU & nCAS0
# !A15 & A14 & !nCPU & Q2 & nCAS0
# A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS1 );

nCAS1 = !( !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
# !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
# !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
# !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
# !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
# !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );

[[File:CPC6128.JED]] : Fixed version of Amstrad 40031 GAL replacement

[[File:CPC6128.hex]] : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.

== Initial replacement equation (Porchy) ==

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

A15OUT = (!X2 & !X1 & A14
# !X3 & !X2 & A14
# A15);

!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
# !X1 & RESET & IOWR
# !X1 & !D7ANDD6 & RESET
# !X1 & A15 & RESET);

!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
# !X2 & RESET & IOWR
# !X2 & !D7ANDD6 & RESET
# !X2 & A15 & RESET);

!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
# !X3 & RESET & IOWR
# !X3 & !D7ANDD6 & RESET
# !X3 & A15 & RESET);

!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
# X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
# !NCAS & CAS0 & !CAS1);

!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
# X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
# !X3 & A15 & !NCAS & !RAMDIS & CAS1
# !X1 & !A14 & !NCAS & !RAMDIS & CAS1
# !X3 & !A14 & !NCAS & !RAMDIS & CAS1
# !NCAS & !RAMDIS & CPU & CAS1
# !NCAS & !CAS0 & CAS1);

A14OUT = (A15 & A14
# !X1 & A14
# X3 & A14);

[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum

== See also ==

For RAM banking settings see Register 3 of the [[Gate_Array|Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).

[[Category:Datasheet]]

Gate Array

2022-03-18T12:57:27Z

Bread80wiki: /* Register 3 - RAM Banking */

Gate Array

Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).

== Introduction ==

The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.

The Gate Array is described here is the one found in a standard CPC.

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

== Controlling the Gate Array ==

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
|''Data Bit 7''||''Data Bit 6''||''Function''
|-
| 0 || 0 || Select pen
|-
| 0 || 1 || Select colour for selected pen
|-
| 1 || 0 || Select screen mode, ROM configuration and interrupt control
|-
| 1 || 1 || RAM Memory Management (note 1)
|-
|}

===== Note =====

This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.

== Register 0 - Palette Index (Pen selection) ==

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 1 || Select border
|-
| 3 || x || rowspan="4" | Ignored
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

<br>

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || 0 || Select pen
|-
| 3 || x || rowspan="4" | Pen number
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 1 - Palette Data (Colour selection) ==

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"
|-
| 6 || 1
|-
| 5 || - || not used
|-
| 4 || x || rowspan="5" | Colour number x
|-
| 3 || x
|-
| 2 || x
|-
| 1 || x
|-
| 0 || x
|}

== Register 2 - Select screen mode and ROM configuration ==

This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.

=== Screen mode selection ===

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit 1'' || ''Bit 0'' || ''Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
|-
| 0 || 1 || Mode 1, 320x200 resolution, 4 colours
|-
| 1 || 0 || Mode 2, 640x200 resolution, 2 colours
|-
| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)
|}

* Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

=== ROM configuration selection ===

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

=== Summary ===

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function
|-
| 6 || 0
|-
| 5 || - || not used
|-
| 4 || x || Interrupt generation control
|-
| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable
|-
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Screen Mode slection
|-
| 0 || x
|}

== Register 3 - RAM Banking ==

This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL]] that assists the Gate Array chip.

{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
| ''Bit'' || ''Value'' || ''Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function 3
|-
| 6 || 1
|-
| 5 || b || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || b
|-
| 3 || b
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
|-
| 1 || x
|-
| 0 || x
|}

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

-Address- 0 1 2 3 4 5 6 7
0000-3FFF RAM_0 RAM_0 RAM_4 RAM_0 RAM_0 RAM_0 RAM_0 RAM_0
4000-7FFF RAM_1 RAM_1 RAM_5 RAM_3 RAM_4 RAM_5 RAM_6 RAM_7
8000-BFFF RAM_2 RAM_2 RAM_6 RAM_2 RAM_2 RAM_2 RAM_2 RAM_2
C000-FFFF RAM_3 RAM_7 RAM_7 RAM_7 RAM_3 RAM_3 RAM_3 RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

== Programming the Gate Array - Examples ==

Defining the colours, <br>Setting pen 0 to Bright White.
<pre>LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration,
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET
</pre>

=== Misc ===

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

=== Note ===

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]
<pre>ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41
;Gate array function (set colour)
;and colour number
out (c),c
ret
</pre>

== Palette R,G,B definitions ==

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

=== Palette sorted by Hardware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 1 (41h) || (13) || White || 50|| 50|| 50|| bgcolor="#808080" |
|-
| 2 (42h) || 19 || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 3 (43h) || 25 || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 4 (44h) || 1 || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 5 (45h) || 7 || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 6 (46h) || 10 || Cyan || 0|| 50|| 50|| bgcolor="#008080" |
|-
| 7 (47h) || 16 || Pink ||100|| 50|| 50|| bgcolor="#ff8080" |
|-
| 8 (48h) || (7) || Purple ||100|| 0|| 50|| bgcolor="#ff0080" |
|-
| 9 (49h) || (25) || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" |
|-
| 10 (4Ah) || 24 || Bright Yellow ||100||100|| 0|| bgcolor="#ffff00" |
|-
| 11 (4Bh) || 26 || Bright White ||100||100||100|| bgcolor="#ffffff" |
|-
| 12 (4Ch) || 6 || Bright Red ||100|| 0|| 0|| bgcolor="#ff0000" |
|-
| 13 (4Dh) || 8 || Bright Magenta||100|| 0||100|| bgcolor="#ff00ff" |
|-
| 14 (4Eh) || 15 || Orange ||100|| 50|| 0|| bgcolor="#ff8000" |
|-
| 15 (4Fh) || 17 || Pastel Magenta||100|| 50||100|| bgcolor="#ff80ff" |
|-
| 16 (50h) || (1) || Blue || 0|| 0|| 50|| bgcolor="#000080" |
|-
| 17 (51h) || (19) || Sea Green || 0||100|| 50|| bgcolor="#00ff80" |
|-
| 18 (52h) || 18 || Bright Green || 0||100|| 0|| bgcolor="#00ff00" |
|-
| 19 (53h) || 20 || Bright Cyan || 0||100||100|| bgcolor="#00ffff" |
|-
| 20 (54h) || 0 || Black || 0|| 0|| 0|| bgcolor="#000000" |
|-
| 21 (55h) || 2 || Bright Blue || 0|| 0||100|| bgcolor="#0000ff" |
|-
| 22 (56h) || 9 || Green || 0|| 50|| 0|| bgcolor="#008000" |
|-
| 23 (57h) || 11 || Sky Blue || 0|| 50||100|| bgcolor="#0080ff" |
|-
| 24 (58h) || 4 || Magenta || 50|| 0|| 50|| bgcolor="#800080" |
|-
| 25 (59h) || 22 || Pastel Green || 50||100|| 50|| bgcolor="#80ff80" |
|-
| 26 (5Ah) || 21 || Lime || 50||100|| 0|| bgcolor="#80ff00" |
|-
| 27 (5Bh) || 23 || Pastel Cyan || 50||100||100|| bgcolor="#80ffff" |
|-
| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" |
|-
| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| bgcolor="#8000ff" |
|-
| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| bgcolor="#808000" |
|-
| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| bgcolor="#8080ff" |
|}

=== Palette sorted by Firmware Colour Numbers ===

{| class="FCK__ShowTableBorders"
|-
| ''Firmware Number'' || ''Hardware Number'' || ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0|| 54h ||Black || 0|| 0|| 0||bgcolor="#000000"|
|-
| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50||bgcolor="#000080"|
|-
| 2|| 55h ||Bright Blue || 0|| 0||100||bgcolor="#0000ff"|
|-
| 3|| 5Ch ||Red || 50|| 0|| 0||bgcolor="#800000"|
|-
| 4|| 58h ||Magenta || 50|| 0|| 50||bgcolor="#800080"|
|-
| 5|| 5Dh ||Mauve || 50|| 0||100||bgcolor="#8000ff"|
|-
| 6|| 4Ch ||Bright Red ||100|| 0|| 0||bgcolor="#ff0000"|
|-
| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50||bgcolor="#ff0080"|
|-
| 8|| 4Dh ||Bright Magenta ||100|| 0||100||bgcolor="#ff00ff"|
|-
| 9|| 56h ||Green || 0|| 50|| 0||bgcolor="#008000"|
|-
|10|| 46h ||Cyan || 0|| 50|| 50||bgcolor="#008080"|
|-
|11|| 57h ||Sky Blue || 0|| 50||100||bgcolor="#0080ff"|
|-
|12|| 5Eh ||Yellow || 50|| 50|| 0||bgcolor="#808000"|
|-
|13|| 40h (or 41h) ||White || 50|| 50|| 50||bgcolor="#808080"|
|-
|14|| 5Fh ||Pastel Blue || 50|| 50||100||bgcolor="#8080ff"|
|-
|15|| 4Eh ||Orange ||100|| 50|| 0||bgcolor="#ff8000"|
|-
|16|| 47h ||Pink ||100|| 50|| 50||bgcolor="#ff8080"|
|-
|17|| 4Fh ||Pastel Magenta ||100|| 50||100||bgcolor="#ff80ff"|
|-
|18|| 52h ||Bright Green || 0||100|| 0||bgcolor="#00ff00"|
|-
|19|| 42h (or 51h) ||Sea Green || 0||100|| 50||bgcolor="#00ff80"|
|-
|20|| 53h ||Bright Cyan || 0||100||100||bgcolor="#00ffff"|
|-
|21|| 5Ah ||Lime || 50||100|| 0||bgcolor="#80ff00"|
|-
|22|| 59h ||Pastel Green || 50||100|| 50||bgcolor="#80ff80"|
|-
|23|| 5Bh ||Pastel Cyan || 50||100||100||bgcolor="#80ffff"|
|-
|24|| 4Ah ||Bright Yellow ||100||100|| 0||bgcolor="#ffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100||bgcolor="#ffffff"|
|}

=== Intensities ===

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
* [[CPC Palette]] - some more details

=== To calculate the colour value ===

'''Red'''

0% => do not add anything

50% => add 3

100% => add 6

'''Green'''

0% => do not add anything

50% => add 9

100% => add 18

'''Blue'''

0% => do not add anything

50% => add 1

100% => add 2

=== Green Screen Colours ===

On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)

== Pictures ==

<gallery>
Image:40010_am2_metal.jpg|40010 GA Metal Layer
Image:40010_am2_acid.jpg|40010 GA with Metal Layer removed
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>

==See also==

*[[Gate Array and ASIC Pin-Outs]]

*[[Video modes]] : for other informations on colours and pixels.

*[[CRTC]] : the other video stuff.
*[[ASIC]] : for Plus users

*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.

[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]