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Amstrad Whole Memory Guide - The display system

2020-02-12T21:40:07Z

2f1cafc: /* Workspace */added screen pack table

In all, the Display System takes up some 4000 bytes of code and fixed data in ROM, and its workspace spans about 380 bytes of RAM, not to mention the 16K byte screen RAM. There are more than 100 entry points. Fortunately, the system divides into three maln parts:

* The Screen Pack deals directly with screen handling, colour selection and screen read and write.

* The Text VDU handles matters relating to text display, including the implementation of stream selection. It also deals with the control codes and their parameters.

* The Graphics VDU handles the graphic display.

Each of these parts requires a chapter to itself, but it will be useful to offer some general information first.

== The Screen RAM ==

In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.

The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incremented after each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows;

* Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true.

* Address bits A11-A13 are driven from RA0-RA3

* Address bits A11-A10 are driven from MA0-MA9

* Address bit A0 is driven from the CRT Controller clock.

The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the CRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes.

In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row.

In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row.

In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row.

The way the CRT Controller counts are used complicates the calculation of screen addresses. Numbering columns and rows from 0:

<code>Address = Base + Offset + N*Column + 86*Row + 2048 per scan line.</code>

where N is the number of bits per pixel in the current mode.

For a given scan line, the bits are taken in sequence. The next scan line is located by increasing the addresses by 0800.

Fortunately, the system will work out screen addresses on the basis of column, line, base and offset.

Observant readers may notice a slight anomaly. If <code>N*Column = 79</code>, and <code>Row = 25</code>, the column and row terms in the above equation fotal 1999, so there are 48 locations in each scan line that are spare. The MA counter in the CRTC does not address them.

However, there is the Offset term to be taken into account. Making offset = &50 moves the screen up one line. Making the offset $869 would move the display up by one scan line, but offset is limited to 07FF by the routine normally used to set it. When Offset is used, the Start Address in the CRTC is modified, and the missing 48 bytes may then come into play. There is a lot of scope for gentle experiment here.

== Streams ==

The system provides for the definition of eight 'streams' of sereen data, each with its own independent parameters, which are:

* Window
* Cursor Position
* Pen and Paper
* Cursor Enable
* Screen Enable
* Opaque or Transparent
* Text or Graphics Write
* Roll Type

All eight sets of parameters are held in store, the set in current use being copied into a common area.

Bach stream may reserve for itself a rectangular window. If two windows overlap, the streams may overwrite each other in the overlap area. Any area not so reserved may be accessed by stream 0, which is the default if no stream is specified.

== Parameters ==

A certain amount of care is needed in dealing with screen parameters, as their definition can vary. A distinction is made between 'physical' and 'logical' values, the former numbering columns and rows from 0 upwards, while the latter start at 1. There are also distinctions between absolute and relative values.

Similar distinctions arise with Graphics parameters, user coordinates being relative to the origin set by the user, while standard coordinates are relative to the default origin.

== Workspace ==

As many workspace locations are common to more than one section of the display system, the addresses for the whole screen workspace in Version 1.0 are given here

==== Screen Pack ====

{| border="1" cellpadding="4"
|-
| B1C8 || Mode
|-
| B1C9 - B1CA || Offset
|-
| B1CB || Base (High byte)
|-
| B1CC - B1CE || Jump instruction
|-
| B1CF - B1D6 || Pixel masks
|-
| B1D7 || Flash time 2
|-
| B1D8 || Flash time 1
|-
| B1D9 - B1E9 || Colour table 2
|-
| B1EA - B1FA || Colour table 1
|-
| B1FB || Table select flag
|-
| B1FC || Flash count
|-
| B1FD || Colour time
|-
| B1FE - B206 || Event block
|-
| B207 || Bits/pixel negated
|}

== Scanned pages ==

<gallery>
Image:AWMG page39.jpg|page 39
Image:AWMG page40.jpg|page 40
Image:AWMG page41.jpg|page 41
Image:AWMG page42.jpg|page 42
Image:AWMG page43.jpg|page 43
Image:AWMG page44.jpg|page 44
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The display system

2020-02-12T21:14:14Z

2f1cafc: /* Workspace */typo

In all, the Display System takes up some 4000 bytes of code and fixed data in ROM, and its workspace spans about 380 bytes of RAM, not to mention the 16K byte screen RAM. There are more than 100 entry points. Fortunately, the system divides into three maln parts:

* The Screen Pack deals directly with screen handling, colour selection and screen read and write.

* The Text VDU handles matters relating to text display, including the implementation of stream selection. It also deals with the control codes and their parameters.

* The Graphics VDU handles the graphic display.

Each of these parts requires a chapter to itself, but it will be useful to offer some general information first.

== The Screen RAM ==

In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.

The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incremented after each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows;

* Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true.

* Address bits A11-A13 are driven from RA0-RA3

* Address bits A11-A10 are driven from MA0-MA9

* Address bit A0 is driven from the CRT Controller clock.

The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the CRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes.

In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row.

In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row.

In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row.

The way the CRT Controller counts are used complicates the calculation of screen addresses. Numbering columns and rows from 0:

<code>Address = Base + Offset + N*Column + 86*Row + 2048 per scan line.</code>

where N is the number of bits per pixel in the current mode.

For a given scan line, the bits are taken in sequence. The next scan line is located by increasing the addresses by 0800.

Fortunately, the system will work out screen addresses on the basis of column, line, base and offset.

Observant readers may notice a slight anomaly. If <code>N*Column = 79</code>, and <code>Row = 25</code>, the column and row terms in the above equation fotal 1999, so there are 48 locations in each scan line that are spare. The MA counter in the CRTC does not address them.

However, there is the Offset term to be taken into account. Making offset = &50 moves the screen up one line. Making the offset $869 would move the display up by one scan line, but offset is limited to 07FF by the routine normally used to set it. When Offset is used, the Start Address in the CRTC is modified, and the missing 48 bytes may then come into play. There is a lot of scope for gentle experiment here.

== Streams ==

The system provides for the definition of eight 'streams' of sereen data, each with its own independent parameters, which are:

* Window
* Cursor Position
* Pen and Paper
* Cursor Enable
* Screen Enable
* Opaque or Transparent
* Text or Graphics Write
* Roll Type

All eight sets of parameters are held in store, the set in current use being copied into a common area.

Bach stream may reserve for itself a rectangular window. If two windows overlap, the streams may overwrite each other in the overlap area. Any area not so reserved may be accessed by stream 0, which is the default if no stream is specified.

== Parameters ==

A certain amount of care is needed in dealing with screen parameters, as their definition can vary. A distinction is made between 'physical' and 'logical' values, the former numbering columns and rows from 0 upwards, while the latter start at 1. There are also distinctions between absolute and relative values.

Similar distinctions arise with Graphics parameters, user coordinates being relative to the origin set by the user, while standard coordinates are relative to the default origin.

== Workspace ==

As many workspace locations are common to more than one section of the display system, the addresses for the whole screen workspace in Version 1.0 are given here

== Scanned pages ==

<gallery>
Image:AWMG page39.jpg|page 39
Image:AWMG page40.jpg|page 40
Image:AWMG page41.jpg|page 41
Image:AWMG page42.jpg|page 42
Image:AWMG page43.jpg|page 43
Image:AWMG page44.jpg|page 44
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The display system

2019-10-02T11:55:32Z

2f1cafc:

In all, the Display System takes up some 4000 bytes of code and fixed data in ROM, and its workspace spans about 380 bytes of RAM, not to mention the 16K byte screen RAM. There are more than 100 entry points. Fortunately, the system divides into three maln parts:

* The Screen Pack deals directly with screen handling, colour selection and screen read and write.

* The Text VDU handles matters relating to text display, including the implementation of stream selection. It also deals with the control codes and their parameters.

* The Graphics VDU handles the graphic display.

Each of these parts requires a chapter to itself, but it will be useful to offer some general information first.

== The Screen RAM ==

In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.

The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incremented after each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows;

* Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true.

* Address bits A11-A13 are driven from RA0-RA3

* Address bits A11-A10 are driven from MA0-MA9

* Address bit A0 is driven from the CRT Controller clock.

The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the CRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes.

In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row.

In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row.

In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row.

The way the CRT Controller counts are used complicates the calculation of screen addresses. Numbering columns and rows from 0:

<code>Address = Base + Offset + N*Column + 86*Row + 2048 per scan line.</code>

where N is the number of bits per pixel in the current mode.

For a given scan line, the bits are taken in sequence. The next scan line is located by increasing the addresses by 0800.

Fortunately, the system will work out screen addresses on the basis of column, line, base and offset.

Observant readers may notice a slight anomaly. If <code>N*Column = 79</code>, and <code>Row = 25</code>, the column and row terms in the above equation fotal 1999, so there are 48 locations in each scan line that are spare. The MA counter in the CRTC does not address them.

However, there is the Offset term to be taken into account. Making offset = &50 moves the screen up one line. Making the offset $869 would move the display up by one scan line, but offset is limited to 07FF by the routine normally used to set it. When Offset is used, the Start Address in the CRTC is modified, and the missing 48 bytes may then come into play. There is a lot of scope for gentle experiment here.

== Streams ==

The system provides for the definition of eight 'streams' of sereen data, each with its own independent parameters, which are:

* Window
* Cursor Position
* Pen and Paper
* Cursor Enable
* Screen Enable
* Opaque or Transparent
* Text or Graphics Write
* Roll Type

All eight sets of parameters are held in store, the set in current use being copied into a common area.

Bach stream may reserve for itself a rectangular window. If two windows overlap, the streams may overwrite each other in the overlap area. Any area not so reserved may be accessed by stream 0, which is the default if no stream is specified.

== Parameters ==

A certain amount of care is needed in dealing with screen parameters, as their definition can vary. A distinction is made between 'physical' and 'logical' values, the former numbering columns and rows from 0 upwards, while the latter start at 1. There are also distinctions between absolute and relative values.

Similar distinctions arise with Graphics parameters, user coordinates being relative to the origin set by the user, while standard coordinates are relative to the default origin.

== Workspace ==

As many workspace locations are common to more than one section of the display system, the addresses for the whole screen workspace in Version 1.6 are given here

== Scanned pages ==

<gallery>
Image:AWMG page39.jpg|page 39
Image:AWMG page40.jpg|page 40
Image:AWMG page41.jpg|page 41
Image:AWMG page42.jpg|page 42
Image:AWMG page43.jpg|page 43
Image:AWMG page44.jpg|page 44
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The display system

2019-09-30T13:21:54Z

2f1cafc: OCR'd page 42

In all, the Display System takes up some 4000 bytes of code and fixed data in ROM, and its workspace spans about 380 bytes of RAM, not to mention the 16K byte screen RAM. There are more than 100 entry points. Fortunately, the system divides into three maln parts:

* The Screen Pack deals directly with screen handling, colour selection and screen read and write.

* The Text VDU handles matters relating to text display, including the implementation of stream selection. It also deals with the control codes and their parameters.

* The Graphics VDU handles the graphic display.

Each of these parts requires a chapter to itself, but it will be useful to offer some general information first.

== The Screen RAM ==

In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.

The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incremented after each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is 1initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows;

* Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true.

* Address bits A11-A13 are driven from RA0-RA3

* Address bits A11-A10 are driven from MA0-MA9

* Address bit A0 is driven from the CRT Controller clock.

The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the GCRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes.

In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row.

In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row.

In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row.

The way the CRT Controller counts are used complicates the calculation of screen addresses. Numbering columns and rows from 0:

<code>Address = Base + Offset + N*Column + 86*Row + 2048 per scan line.</code>

where N is the number of bits per pixel in the current mode.

For a given scan line, the bits are taken in sequence. The next scan line is located by increasing the addresses by 0800.

Fortunately, the system will work out screen addresses on the basis of column, line, base and offset.

Observant readers may notice a slight anomaly. If <code>N*Column = 79</code>, and <code>Row = 25</code>, the column and row terms in the above equation fotal 1999, so there are 48 locations in each scan line that are spare. The MA counter in the CRTC does not address them.

However, there is the Offset term to be taken into account. Making offset = &50 moves the screen up one line. Making the offset $869 would move the display up by one scan line, but offset is limited to 07FF by the routine normally used to set it. When Offset is used, the Start Address in the CRTC is modified, and the missing 48 bytes may then come into play. There is a lot of scope for gentle experiment here.

== Streams ==

The system provides for the definition of eight 'streams' of sereen data, each with its own independent parameters, which are:

* Window
* Cursor Position
* Pen and Paper
* Cursor Enable
* Screen Enable
* Opaque or Transparent
* Text or Graphics Write
* Roll Type

All eight sets of parameters are held in store, the set in current use being copied into a common area.

Bach stream may reserve for itself a rectangular window. If two windows overlap, the streams may overwrite each other in the overlap area. Any area not so reserved may be accessed by stream 0, which is the default if no stream is specified.

== Parameters ==

A certain amount of care is needed in dealing with screen parameters, as their definition can vary. A distinction is made between 'physical' and 'logical' values, the former numbering columns and rows from 0 upwards, while the latter start at 1. There are also distinctions between absolute and relative values.

Similar distinctions arise with Graphics parameters, user coordinates being relative to the origin set by the user, while standard coordinates are relative to the default origin.

== Workspace ==

As many workspace locations are common to more than one section of the display system, the addresses for the whole screen workspace in Version 1.6 are given here

== Scanned pages ==

<gallery>
Image:AWMG page39.jpg|page 39
Image:AWMG page40.jpg|page 40
Image:AWMG page41.jpg|page 41
Image:AWMG page42.jpg|page 42
Image:AWMG page43.jpg|page 43
Image:AWMG page44.jpg|page 44
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The display system

2019-09-30T13:16:10Z

2f1cafc: OCR'd page 41

In all, the Display System takes up some 4000 bytes of code and fixed data in ROM, and its workspace spans about 380 bytes of RAM, not to mention the 16K byte screen RAM. There are more than 100 entry points. Fortunately, the system divides into three maln parts:

* The Screen Pack deals directly with screen handling, colour selection and screen read and write.

* The Text VDU handles matters relating to text display, including the implementation of stream selection. It also deals with the control codes and their parameters.

* The Graphics VDU handles the graphic display.

Each of these parts requires a chapter to itself, but it will be useful to offer some general information first.

== The Screen RAM ==

In theory, the Screen RAM could be any 16K byte area of memory starting at a multiple of 4000, but the 8000-BFFF block would overwrite workspace and RAM routines, while 0000-3FFF would overwrite the RST Area, so the choice narrows to 4000-7FFF or C000-FFFF, and it is usually more convenient to adopt the latter area, leaving the central half of RAM free for other purposes.

The Screen RAM is accessed by the Video Gate Array on a basis of addresses supplied by the CRT Controller, but the addresses are not used in a straightforward manner. The CRT Controller embodies two counters. One, output on RA0-RA4, is incremented after each line of the display has been scanned. When this count reaches the value set for the number of scan lines in the character height it is zeroed, and the second counter, output on MA0-MA13, is incremented. This counter is 1initialised to the Start Address set in the CRT Controller, which is 3000 when the C000-FFFF area is in use. These outputs are used as follows;

* Address bits A14,A15 are driven from MA12,MA13. Since the MA counter works from a Start Address of 3000, both these bits are true.

* Address bits A11-A13 are driven from RA0-RA3

* Address bits A11-A10 are driven from MA0-MA9

* Address bit A0 is driven from the CRT Controller clock.

The scan line takes 40 microseconds to traverse the visible part of the display, and during each microsecond the Video Gate Array requires two bytes of screen data. These are transferred directly from RAM to the Video Gate Array, the processor being meanwhile held in Wait. The process is so timed that the GCRTC clock changes state between the two transfers. Once all the bytes have been read, the normal processor action is allowed to continue. The bytes are used in different ways in the three screen modes.

In Mode 2, each byte defines one row of a character pattern matrix, each bit determining which of two colours should be given to a pixel, and eighty characters are displayed in each screen row.

In Mode 1, two bytes are required to define each matrix row, two bits being used to give each pixel one of four colours. Successive pixels are defined by bits 3,7; 2,6; 1,5; and 0,4. This sequence is repeated in the second byte From each pair of bits, the Video Gate Array determines which palette entry should be used, and sets the colour accordingly. Since each matrix row requires two bytes, only forty characters can be displayed per screen row.

In Mode 0, four bits are required to define one of sixteen colours for each pixel. This means that four bytes are required for each matrix row. The first pixel is defined by bits 1,5,3,7 of the first byte, the second by bits 0,4,2,6 and so on. Twenty characters can be displayed in each screen row.

The way the CRT Controller counts are used complicates the calculation of screen addresses. Numbering columns and rows from 0:

<code>Address = Base + Offset + N*Column + 86*Row + 2048 per scan line.</code>

where N is the number of bits per pixel in the current mode.

For a given scan line, the bits are taken in sequence. The next scan line is located by increasing the addresses by 0800.

Fortunately, the system will work out screen addresses on the basis of column, line, base and offset.

Observant readers may notice a slight anomaly. If <code>N*Column = 79</code>, and <code>Row = 25</code>, the column and row terms in the above equation fotal 1999, so there are 48 locations in each scan line that are spare. The MA counter in the CRTC does not address them.

However, there is the Offset term to be taken into account. Making offset = &50 moves the screen up one line. Making the offset $869 would move the display up by one scan line, but offset is limited to 07FF by the routine normally used to set it. When Offset is used, the Start Address in the CRTC is modified, and the missing 48 bytes may then come into play. There is a lot of scope for gentle experiment here.

== Streams ==

The system provides for the definition of eight 'streams' of sereen data, each with its own independent parameters, which are:

* Window
* Cursor Position
* Pen and Paper
* Cursor Enable
* Screen Enable
* Opaque or Transparent
* Text or Graphics Write
* Roll Type

All eight sets of parameters are held in store, the set in current use being copied into a common area.

Bach stream may reserve for itself a rectangular window. If two windows overlap, the streams may overwrite each other in the overlap area. Any area not so reserved may be accessed by stream 0, which is the default if no stream is specified.

== Scanned pages ==

<gallery>
Image:AWMG page39.jpg|page 39
Image:AWMG page40.jpg|page 40
Image:AWMG page41.jpg|page 41
Image:AWMG page42.jpg|page 42
Image:AWMG page43.jpg|page 43
Image:AWMG page44.jpg|page 44
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The display system

2019-09-26T19:21:56Z

2f1cafc: /* The Screen RAM */OCR page 40

Amstrad Whole Memory Guide - The machine pack

2019-09-26T13:21:38Z

2f1cafc: OCR of page 22

Broadly speaking, the Machine Pack is reponsible for the control of hardware peripherals, but it will be convenient to include the main initialisation processes under this heading, since they are largely concerned with peripheral setting-up.

Several of the Machine Pack routines depend on the action of other routines to set up data. To understand this data in full, you need to read 'The Ins and Outs of the AMSTRAD CPC464', which gives full details of the peripheral codes. Only the more essential codes will be defined here.

== MAIN RESET ==

At switch—on, or in response to instruction code &C7, location 0000 is entered. At switch-on, lower ROM is enabled, but the ROM routines are later copied to the corresponding RAM locations in this area, so the enable state of the lower ROM is then unimportant. However, the first action of the reset routine is to output &89 to the Video Gate array on I/0 address 7FXX, and this enables lower ROM, disables upper ROM, and also sets up Mode 1. There being no further room in the RST Area the routine jumps to 0580 to continue reset action.

Interrupt is disabled, and &82 is output to F7XX. This sets the PPI (Parallel Peripheral Interface) to output on ports A and C, input on port B. Zero outputs to F4XX and F6XX clear ports A and C, while an output of &7F to EFXX initialises the printer port. Bit 7 is low, the other bits are high.

The CRT Controller is then set up. There are two alternative sets of values for this, one for 50 Hz frame scan and the other for 60 Hz. The set to be used is determined by reading port B, bit 4. If this bit is true, 50 Hz values are used, while the 60 Hz values are used if the bit is false, this being determined by the presence of Link 4 on the main printed circuit board.

The tables are read backwards, which can be a little confusing at first, and the outputs alternate between BCXX, which selects the register to be set, and BDXX, which performs the actual setting.

Then MC START PROGRAM is entered at 060E with DE=065C and HL=0000. The contents of DE point to the display routine for the main title, which is called at an appropriate point. The zero value in HL means that ROM 0 will be entered at C006. This will normally invoke the BASIC interpreter, unless an external ROM responds to 0. C006 is the standard upper ROM entry point.

Before discussing MC START PROGRAM, it will be convenient to look at a program which calls it, having first loaded the necessary data:

== MC BOOT PROGRAM: BD13,05DC ==

On entry to this function, HL must hold the address of a loading routine, which must be designed to return with carry set and the program start address in HL if the load is successful, or with carry clear if the load fails.

The stack is reset by SP=C000, this being the normal stack position, and sound RESET is called to silence the Sound Generator. Interrupt is disabled, and &FF is output to port F8FF, requiring that all external peripherals devices should be reset.

KL CHOKE OFF is called to clear the B100-B1BF area to zeroes, though the previous contents of (B1A9/B) are first saved. (B1A9/A) holds the last-used foreground ROM entry address, which is copied to DE, while (B1AB) holds the last-used foreground ROM number, which is copied to B. (Note that the number of the ROM in current use is held in (B1A8), which is not preserved here.) If (B1AB) holds &FF the routine returns with C, D and E all zeroed.

Back in the main BOOT routine, HL is restored to its value on entry and DE, BC and HL are pushed. KM RESET is called to initialise the Key Manager, TXT RESET is called to initialise the text screen, assisted by a call to SCR RESET, and U ROM ENABLE is called to bring the upper ROM into action.

HL is popped, and the loading program it defines is entered, using an odd little subroutine that consists solely of the JP (HL) instruction. BC and DE are popped.

If the loader returned with carry set, MC START PROGRAM is entered at 060B. Otherwise, DE and HL are exchanged, putting the address obtained by KL CHOKE OFF into HL, C=B, and MC START PROGRAM is entered at 060E with DE=06E8, the entry address of a routine that reports 'LOAD FAILED'. The previously-selected ROM is entered.

== MC START PROGRAM: BD16,060B ==

If the normal entry to this function, at 060B, is used, DE is set to 0726 (pointing to a Return instruction), but it is also possible to enter at 060E, with DE pointing to a subroutine to be run during the latter part of the START PROGRAM routine. In either case, HL must hold the entry address to be used, and C must hold the number of the ROM to be employed, though the contents of C may be irrelevant if HL points to a RAM area.

Interrupt is disabled, and interrupt mode 1 is selected. The alternative BC, DE and HL registers are brought into action.

An output of 0 to DFXX selects upper ROM 0, and an output of &FF on I/0 address F8FF should reset external peripherals. Workspace in the B100-B8FF range is zeroed, and the Video Gate Array receives an output of &89 on address 7FXX. (Mode 1, enable lower, disable upper.) The normal BC, DE and HL registers are re-selected. XOR A zeroes A and clears carry, and EX AF ,AF' exchanges AF registers. This sets up the initial conditions required by the interrupt system.

The stack pointer is again set to C000, its normal base, and HL, BC and DE are pushed. A series of calls then performs the main initialisation;

* To 0044, copying the RAM routines from RAM, with KL CHOKE OFF following.

* JUMP RESTORE resets the jumpblock entries.

* KM INITIALISE resets the Key Manager.

* SOUND RESET initialises the Sound system.

* TXT INITIALISE initialises the Text VDU.

* GRA INITIALISE initialises the Graphics VDU.

* CAS INITIALISE initialises the Cassette Manager.

* MC RESET PRINTER standardises the printer system.

* SCR INITIALISE initialises the Screen Pack.

The details of these routines will be examined in the appropriate place, but it can be said that everything - or nearly everything - is brought to a standard state. This can be annoying to someone who likes to set up non-standard conditions, but it has the great advantage that every program starts on the same basis.

Interrupt is now enabled, and the routine defined in DE on entry is called. This may be the initial title display, or a 'load failed' report, as defined below. The main program then pops BG and HL and jumps to 0077, which is the actual entry routine. This key routine is not accessible via the Jumpblock, which might be useful, because the system concept requires a fulll reset before a program is entered.

If HL holds 0000, the default entry to C006 in ROM 0 is executed, but otherwise the ROM is defined in A and the entry address in HL.

{| class="wikitable"
|0077 || If HL=0000, HL=C006, A=0 || Default Values.
|-
| || (B1A8)=A || ROM number.
|-
| || (B1AB)=A || Part of qualifier.
|-
| || (B1A9/A)=HL || Qualifier address.
|-
| || HL=ABFF || Initial HIMEM.
|-
| || DE=0040 || Initial LOMEM.
|-
| || BC=B0FF || Top of usable memory.
|+ A FAR CALL DF A9 Bl enters the specified routine. On return, a full reset from 0000 is executed.
|}

This completes the MG START PROGRAM routine, apart from the routines called near the end:

065C This calls 0712, which reads port B, picking up bits 1-3, which are determined by links. According to the links set, the display announces that the name of the machine is one of the following:

* Arnold
* Amstrad
* Orion
* Schneider
* Awa
* Solovox
* Saisho
* Triumph
* Isp

The actual output to the display is handled by 06EB, which is also called with HL=066D to output the rest of the title, and finally with HL=0693 to complete the display.

06E8 HL=@6F4, pointing to '<code>***PROGRAM LOAD FAILED***</code>'

== Scanned pages ==

<gallery>
Image:AWMG page19.jpg|page 19
Image:AWMG page20.jpg|page 20
Image:AWMG page21.jpg|page 21
Image:AWMG page22.jpg|page 22
Image:AWMG page23.jpg|page 23
Image:AWMG page24.jpg|page 24
Image:AWMG page25.jpg|page 25
Image:AWMG page26.jpg|page 26
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The machine pack

2019-09-25T21:33:43Z

2f1cafc: OCR'd page 21

Broadly speaking, the Machine Pack is reponsible for the control of hardware peripherals, but it will be convenient to include the main initialisation processes under this heading, since they are largely concerned with peripheral setting-up.

Several of the Machine Pack routines depend on the action of other routines to set up data. To understand this data in full, you need to read 'The Ins and Outs of the AMSTRAD CPC464', which gives full details of the peripheral codes. Only the more essential codes will be defined here.

== MAIN RESET ==

At switch—on, or in response to instruction code &C7, location 0000 is entered. At switch-on, lower ROM is enabled, but the ROM routines are later copied to the corresponding RAM locations in this area, so the enable state of the lower ROM is then unimportant. However, the first action of the reset routine is to output &89 to the Video Gate array on I/0 address 7FXX, and this enables lower ROM, disables upper ROM, and also sets up Mode 1. There being no further room in the RST Area the routine jumps to 0580 to continue reset action.

Interrupt is disabled, and &82 is output to F7XX. This sets the PPI (Parallel Peripheral Interface) to output on ports A and C, input on port B. Zero outputs to F4XX and F6XX clear ports A and C, while an output of &7F to EFXX initialises the printer port. Bit 7 is low, the other bits are high.

The CRT Controller is then set up. There are two alternative sets of values for this, one for 50 Hz frame scan and the other for 60 Hz. The set to be used is determined by reading port B, bit 4. If this bit is true, 50 Hz values are used, while the 60 Hz values are used if the bit is false, this being determined by the presence of Link 4 on the main printed circuit board.

The tables are read backwards, which can be a little confusing at first, and the outputs alternate between BCXX, which selects the register to be set, and BDXX, which performs the actual setting.

Then MC START PROGRAM is entered at 060E with DE=065C and HL=0000. The contents of DE point to the display routine for the main title, which is called at an appropriate point. The zero value in HL means that ROM 0 will be entered at C006. This will normally invoke the BASIC interpreter, unless an external ROM responds to 0. C006 is the standard upper ROM entry point.

Before discussing MC START PROGRAM, it will be convenient to look at a program which calls it, having first loaded the necessary data:

== MC BOOT PROGRAM: BD13,05DC ==

On entry to this function, HL must hold the address of a loading routine, which must be designed to return with carry set and the program start address in HL if the load is successful, or with carry clear if the load fails.

The stack is reset by SP=C000, this being the normal stack position, and sound RESET is called to silence the Sound Generator. Interrupt is disabled, and &FF is output to port F8FF, requiring that all external peripherals devices should be reset.

KL CHOKE OFF is called to clear the B100-B1BF area to zeroes, though the previous contents of (B1A9/B) are first saved. (B1A9/A) holds the last-used foreground ROM entry address, which is copied to DE, while (B1AB) holds the last-used foreground ROM number, which is copied to B. (Note that the number of the ROM in current use is held in (B1A8), which is not preserved here.) If (B1AB) holds &FF the routine returns with C, D and E all zeroed.

Back in the main BOOT routine, HL is restored to its value on entry and DE, BC and HL are pushed. KM RESET is called to initialise the Key Manager, TXT RESET is called to initialise the text screen, assisted by a call to SCR RESET, and U ROM ENABLE is called to bring the upper ROM into action.

HL is popped, and the loading program it defines is entered, using an odd little subroutine that consists solely of the JP (HL) instruction. BC and DE are popped.

If the loader returned with carry set, MC START PROGRAM is entered at 060B. Otherwise, DE and HL are exchanged, putting the address obtained by KL CHOKE OFF into HL, C=B, and MC START PROGRAM is entered at 060E with DE=06E8, the entry address of a routine that reports 'LOAD FAILED'. The previously-selected ROM is entered.

== MC START PROGRAM: BD16,060B ==

If the normal entry to this function, at 060B, is used, DE is set to 0726 (pointing to a Return instruction), but it is also possible to enter at 060E, with DE pointing to a subroutine to be run during the latter part of the START PROGRAM routine. In either case, HL must hold the entry address to be used, and C must hold the number of the ROM to be employed, though the contents of C may be irrelevant if HL points to a RAM area.

Interrupt is disabled, and interrupt mode 1 is selected. The alternative BC, DE and HL registers are brought into action.

An output of 0 to DFXX selects upper ROM 0, and an output of &FF on I/0 address F8FF should reset external peripherals. Workspace in the B100-B8FF range is zeroed, and the Video Gate Array receives an output of &89 on address 7FXX. (Mode 1, enable lower, disable upper.) The normal BC, DE and HL registers are re-selected. XOR A zeroes A and clears carry, and EX AF ,AF' exchanges AF registers. This sets up the initial conditions required by the interrupt system.

The stack pointer is again set to C000, its normal base, and HL, BC and DE are pushed. A series of calls then performs the main initialisation;

* To 0044, copying the RAM routines from RAM, with KL CHOKE OFF following.

* JUMP RESTORE resets the jumpblock entries.

* KM INITIALISE resets the Key Manager.

* SOUND RESET initialises the Sound system.

* TXT INITIALISE initialises the Text VDU.

* GRA INITIALISE initialises the Graphics VDU.

* CAS INITIALISE initialises the Cassette Manager.

== Scanned pages ==

<gallery>
Image:AWMG page19.jpg|page 19
Image:AWMG page20.jpg|page 20
Image:AWMG page21.jpg|page 21
Image:AWMG page22.jpg|page 22
Image:AWMG page23.jpg|page 23
Image:AWMG page24.jpg|page 24
Image:AWMG page25.jpg|page 25
Image:AWMG page26.jpg|page 26
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The machine pack

2019-09-25T19:44:05Z

2f1cafc: /* MC Boot Program: BD13,05DC */OCR page 20

Amstrad Whole Memory Guide - The display system

2019-09-25T19:29:27Z

2f1cafc:

Amstrad Whole Memory Guide - The machine pack

2019-09-25T19:08:01Z

2f1cafc: /* Main Reset */subsection

Amstrad Whole Memory Guide - The machine pack

2019-09-25T19:07:08Z

2f1cafc: section headers, rewrap

== Chapter 3: The Machine Pack ==

Broadly speaking, the Machine Pack is reponsible for the control of hardware peripherals, but it will be convenient to include the main initialisation processes under this heading, since they are largely concerned with peripheral setting-up.

Several of the Machine Pack routines depend on the action of other routines to set up data. To understand this data in full, you need to read 'The Ins and Outs of the AMSTRAD CPC464', which gives full details of the peripheral codes. Only the more essential codes will be defined here.

=== Main Reset ===

At switch—on, or in response to instruction code &C7, location 0000 is entered. At switch-on, lower ROM is enabled, but the ROM routines are later copied to the corresponding RAM locations in this area, so the enable state of the lower ROM is then unimportant. However, the first action of the reset routine is to output &89 to the Video Gate array on I/0 address 7FXX, and this enables lower ROM, disables upper ROM, and also sets up Mode 1. There being no further room in the RST Area the routine jumps to 0580 to continue reset action.

Interrupt is disabled, and &82 is output to F7XX. This sets the PPI (Parallel Peripheral Interface) to output on ports A and C, input on port B. Zero outputs to F4XX and F6XX clear ports A and C, while an output of &7F to EFXX initialises the printer port. Bit 7 is low, the other bits are high.

The CRT Controller is then set up. There are two alternative sets of values for this, one for 50 Hz frame scan and the other for 60 Hz. The set to be used is determined by reading port B, bit 4. If this bit is true, 50 Hz values are used, while the 60 Hz values are used if the bit is false, this being determined by the presence of Link 4 on the main printed circuit board.

== Scanned pages ==

<gallery>
Image:AWMG page19.jpg|page 19
Image:AWMG page20.jpg|page 20
Image:AWMG page21.jpg|page 21
Image:AWMG page22.jpg|page 22
Image:AWMG page23.jpg|page 23
Image:AWMG page24.jpg|page 24
Image:AWMG page25.jpg|page 25
Image:AWMG page26.jpg|page 26
</gallery>

[[Category:CPC Firmware]]

Amstrad Whole Memory Guide - The machine pack

2019-09-25T19:00:25Z

2f1cafc: ocr'd page 19

Chapter 3 in the book [[Amstrad Whole Memory Guide]].

Chapter 3
THE MACHINE PACK

Broadly speaking, the Machine Pack is reponsible for the control of
hardware peripherals, but it will be convenient to include the main
initialisation processes under this heading, since they are largely
concerned with peripheral setting-up.

Several of the Machine Pack routines depend on the action of
other routines to set up data. To understand this data in full,
you need to read 'The Ins and Outs of the AMSTRAD CPC464', which
gives full details of the peripheral codes. Only the more
essential codes will be defined here.

Main Reset

At switch—on, or in response to instruction code &C7, location 0000 is
entered. At switch-on, lower ROM is enabled, but the ROM routines are
later copied to the corresponding RAM locations in this area, so the
enable state of the lower ROM is then unimportant. However, the first
action of the reset routine is to output &89 to the Video Gate array
on I/0 address 7FXX, and this enables lower ROM, disables upper ROM,
and also sets up Mode 1. There being no further room in the RST Area
the routine jumps to 0580 to continue reset action.

Interrupt is disabled, and &82 is output to F7XX. This sets the
PPI (Parallel Peripheral Interface) to output on ports A and C,
input on port B. Zero outputs to F4XX and F6XX clear ports A and
C, while an output of &7F to EFXX initialises the printer port.
Bit 7 is low, the other bits are high.

The CRT Controller is then set up. There are two alternative sets of
values for this, one for 50 Hz frame scan and the other for 60 Hz. The
set to be used is determined by reading port B, bit 4. If this bit is
true, 50 Hz values are used, while the 60 Hz values are used if the
bit is false, this being determined by the presence of Link 4 on the
main printed circuit board.

== Scanned pages ==

<gallery>
Image:AWMG page19.jpg|page 19
Image:AWMG page20.jpg|page 20
Image:AWMG page21.jpg|page 21
Image:AWMG page22.jpg|page 22
Image:AWMG page23.jpg|page 23
Image:AWMG page24.jpg|page 24
Image:AWMG page25.jpg|page 25
Image:AWMG page26.jpg|page 26
</gallery>

[[Category:CPC Firmware]]